caravel address map fix 0x300F_FFFF
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl index f082733..68f6db6 100755 --- a/openlane/pinmux/config.tcl +++ b/openlane/pinmux/config.tcl
@@ -46,11 +46,12 @@ $script_dir/../../verilog/rtl/pinmux/src/pinmux_reg.sv \ $script_dir/../../verilog/rtl/pinmux/src/gpio_intr.sv \ $script_dir/../../verilog/rtl/pinmux/src/pwm.sv \ + $script_dir/../../verilog/rtl/pinmux/src/timer.sv \ $script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv \ $script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv \ - $script_dir/../../verilog/rtl/lib/ser_inf_32b.sv \ $script_dir/../../verilog/rtl/lib/registers.v \ $script_dir/../../verilog/rtl/lib/ctech_cells.sv \ + $script_dir/../../verilog/rtl/lib/reset_sync.sv \ "
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg index 42c2cac..4c64993 100644 --- a/openlane/pinmux/pin_order.cfg +++ b/openlane/pinmux/pin_order.cfg
@@ -91,38 +91,6 @@ irq_lines\[2\] irq_lines\[1\] irq_lines\[0\] -fuse_mhartid\[31\] -fuse_mhartid\[30\] -fuse_mhartid\[29\] -fuse_mhartid\[28\] -fuse_mhartid\[27\] -fuse_mhartid\[26\] -fuse_mhartid\[25\] -fuse_mhartid\[24\] -fuse_mhartid\[23\] -fuse_mhartid\[22\] -fuse_mhartid\[21\] -fuse_mhartid\[20\] -fuse_mhartid\[19\] -fuse_mhartid\[18\] -fuse_mhartid\[17\] -fuse_mhartid\[16\] -fuse_mhartid\[15\] -fuse_mhartid\[14\] -fuse_mhartid\[13\] -fuse_mhartid\[12\] -fuse_mhartid\[11\] -fuse_mhartid\[10\] -fuse_mhartid\[9\] -fuse_mhartid\[8\] -fuse_mhartid\[7\] -fuse_mhartid\[6\] -fuse_mhartid\[5\] -fuse_mhartid\[4\] -fuse_mhartid\[3\] -fuse_mhartid\[2\] -fuse_mhartid\[1\] -fuse_mhartid\[0\] cfg_cska_pinmux\[3\] cfg_cska_pinmux\[2\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index d0ccab1..097c11b 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -51,7 +51,7 @@ set ::env(SYNTH_DEFINES) [list SYNTHESIS ] set ::env(SYNTH_PARAMS) "CH_CLK_WD 4,\ - CH_DATA_WD 69 \ + CH_DATA_WD 37 \ " set ::env(SYNTH_READ_BLACKBOX_LIB) 1
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index e722a83..f4bd653 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -147,39 +147,7 @@ #W -ch_data_out\[68\] 0750 0 2 -ch_data_out\[67\] -ch_data_out\[66\] -ch_data_out\[65\] -ch_data_out\[64\] -ch_data_out\[63\] -ch_data_out\[62\] -ch_data_out\[61\] -ch_data_out\[60\] -ch_data_out\[59\] -ch_data_out\[58\] -ch_data_out\[57\] -ch_data_out\[56\] -ch_data_out\[55\] -ch_data_out\[54\] -ch_data_out\[53\] -ch_data_out\[52\] -ch_data_out\[51\] -ch_data_out\[50\] -ch_data_out\[49\] -ch_data_out\[48\] -ch_data_out\[47\] -ch_data_out\[46\] -ch_data_out\[45\] -ch_data_out\[44\] -ch_data_out\[43\] -ch_data_out\[42\] -ch_data_out\[41\] -ch_data_out\[40\] -ch_data_out\[39\] -ch_data_out\[38\] -ch_data_out\[37\] -ch_data_out\[36\] +ch_data_out\[36\] 0750 0 2 ch_data_out\[35\] ch_data_out\[34\] ch_data_out\[33\] @@ -732,39 +700,7 @@ s1_wbd_ack_i s1_wbd_cyc_o -ch_data_in\[68\] 1400 0 2 -ch_data_in\[67\] -ch_data_in\[66\] -ch_data_in\[65\] -ch_data_in\[64\] -ch_data_in\[63\] -ch_data_in\[62\] -ch_data_in\[61\] -ch_data_in\[60\] -ch_data_in\[59\] -ch_data_in\[58\] -ch_data_in\[57\] -ch_data_in\[56\] -ch_data_in\[55\] -ch_data_in\[54\] -ch_data_in\[53\] -ch_data_in\[52\] -ch_data_in\[51\] -ch_data_in\[50\] -ch_data_in\[49\] -ch_data_in\[48\] -ch_data_in\[47\] -ch_data_in\[46\] -ch_data_in\[45\] -ch_data_in\[44\] -ch_data_in\[43\] -ch_data_in\[42\] -ch_data_in\[41\] -ch_data_in\[40\] -ch_data_in\[39\] -ch_data_in\[38\] -ch_data_in\[37\] -ch_data_in\[36\] +ch_data_in\[36\] 1400 0 2 ch_data_in\[35\] ch_data_in\[34\] ch_data_in\[33\]
diff --git a/openlane/yifive/pin_order.cfg b/openlane/yifive/pin_order.cfg index 8a9b2a8..0fbd01f 100644 --- a/openlane/yifive/pin_order.cfg +++ b/openlane/yifive/pin_order.cfg
@@ -21,38 +21,6 @@ irq_lines\[2\] irq_lines\[1\] irq_lines\[0\] -fuse_mhartid\[31\] -fuse_mhartid\[30\] -fuse_mhartid\[29\] -fuse_mhartid\[28\] -fuse_mhartid\[27\] -fuse_mhartid\[26\] -fuse_mhartid\[25\] -fuse_mhartid\[24\] -fuse_mhartid\[23\] -fuse_mhartid\[22\] -fuse_mhartid\[21\] -fuse_mhartid\[20\] -fuse_mhartid\[19\] -fuse_mhartid\[18\] -fuse_mhartid\[17\] -fuse_mhartid\[16\] -fuse_mhartid\[15\] -fuse_mhartid\[14\] -fuse_mhartid\[13\] -fuse_mhartid\[12\] -fuse_mhartid\[11\] -fuse_mhartid\[10\] -fuse_mhartid\[9\] -fuse_mhartid\[8\] -fuse_mhartid\[7\] -fuse_mhartid\[6\] -fuse_mhartid\[5\] -fuse_mhartid\[4\] -fuse_mhartid\[3\] -fuse_mhartid\[2\] -fuse_mhartid\[1\] -fuse_mhartid\[0\] cfg_cska_riscv\[3\] cfg_cska_riscv\[2\]
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 5aa1b71..6deeae1 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -1,7 +1,7 @@ set ::env(IO_PCT) "0.2" set ::env(SYNTH_MAX_FANOUT) "5" set ::env(SYNTH_CAP_LOAD) "1" -set ::env(SYNTH_TIMING_DERATE) 0.05 +set ::env(SYNTH_TIMING_DERATE) 0.01 set ::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) 0.25 set ::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) 0.25 set ::env(SYNTH_CLOCK_TRANSITION) 0.15 @@ -111,15 +111,15 @@ set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[21]}] set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[22]}] set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[23]}] -#set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}] +set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}] set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[25]}] set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[26]}] set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[27]}] set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[28]}] -#set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}] -#set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}] -#set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}] -#set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}] +set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}] +set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}] +set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}] +set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}] set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[33]}] set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[34]}] set_input_delay $input_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[35]}] @@ -131,22 +131,22 @@ set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}] set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io1}] -############################################################################### -# User SPI constraints -# Reducing the Tight SPI spec -# As spi cs# asserted atleast 2 cycle before transaction, we are not constrainting it -# In Spi Interace Data lanuch by negedge and capture at Posedge, So effective Interface hold and setup should not be -# any issue. Any timing issue, we need to reduce the SPI interface clock -################################################################################# - -set user_spi_out [list mprj_io[29] mprj_io[30] mprj_io[31] mprj_io[32]] -set user_spi_in [list mprj_io[29] mprj_io[30] mprj_io[31] mprj_io[32]] - -set_input_delay -clock spi_clk -clock_fall -min 0 -add_delay $user_spi_in -set_input_delay -clock spi_clk -clock_fall -max 10 -add_delay $user_spi_in - -set_output_delay -clock spi_clk -clock_fall -min -0 -add_delay $user_spi_out -set_output_delay -clock spi_clk -clock_fall -max 10 -add_delay $user_spi_out +################################################################################ +## User SPI constraints +## Reducing the Tight SPI spec +## As spi cs# asserted atleast 2 cycle before transaction, we are not constrainting it +## In Spi Interace Data lanuch by negedge and capture at Posedge, So effective Interface hold and setup should not be +## any issue. Any timing issue, we need to reduce the SPI interface clock +################################################################################## +# +#set user_spi_out [list mprj_io[29] mprj_io[30] mprj_io[31] mprj_io[32]] +#set user_spi_in [list mprj_io[29] mprj_io[30] mprj_io[31] mprj_io[32]] +# +#set_input_delay -clock spi_clk -clock_fall -min 0 -add_delay $user_spi_in +#set_input_delay -clock spi_clk -clock_fall -max 10 -add_delay $user_spi_in +# +#set_output_delay -clock spi_clk -clock_fall -min -0 -add_delay $user_spi_out +#set_output_delay -clock spi_clk -clock_fall -max 10 -add_delay $user_spi_out set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index ddbf7d0..384be25 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_qspi user_i2cm riscv_regress user_basic user_usb user_uart_master uart_master +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c index 3e42aaa..d3af045 100644 --- a/verilog/dv/risc_boot/risc_boot.c +++ b/verilog/dv/risc_boot/risc_boot.c
@@ -18,27 +18,11 @@ // This include is relative to $CARAVEL_PATH (see Makefile) #include "verilog/dv/caravel/defs.h" #include "verilog/dv/caravel/stub.c" +#include "../c_func/inc/user_reg_map.h" // User Project Slaves (0x3000_0000) -#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000) - -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30020000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30020004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30020008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3002000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30020010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30020014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30020018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3002001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30020020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30020024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30020028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3002002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30020030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30020034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30020038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3002003C) +#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30080000) #define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000) #define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004) @@ -178,11 +162,11 @@ // Remove All Reset - reg_mprj_globl_reg2 = 0x11F; + reg_pinmux_gbl_cfg0 = 0x11F; // Enable UART Multi Functional Ports - reg_mprj_globl_reg14 = 0x100; + reg_pinmux_gpio_multi_func = 0x100; // configure the user uart reg_mprj_uart_reg0 = 0x7;
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S index 19f8703..db5057f 100644 --- a/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S +++ b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
@@ -11,9 +11,10 @@ #define MCAUSE_TMR_IRQ (1 << 31 | IRQ_M_TIMER) // IPIC -#define IRQ_LINES_ADDR 0x10020020 // simulation -#define TRIG_EXT_IRQ_ADDR 0x10020020 // external irq is triggered when tb memory is set to non-zero // Bit [15:0] -#define TRIG_SW_IRQ_ADDR 0x10020020 // software irq is triggered when tb memory is set to non-zero // Bit [16] +#define IRQ_LINES_MASK 0x1002000C // Interrupt Mask +#define IRQ_LINES_ADDR 0x10020010 // simulation +#define TRIG_EXT_IRQ_ADDR 0x10020010 // external irq is triggered when tb memory is set to non-zero // Bit [15:0] +#define TRIG_SW_IRQ_ADDR 0x10020010 // software irq is triggered when tb memory is set to non-zero // Bit [16] #define IPIC_EOI 0xBF4 // end of interrupt #define IPIC_SOI 0xBF5 // start of interrupt @@ -28,7 +29,7 @@ #define IPIC_ICSR_IS (1 << 4) // in service // Interrupt lines in use -#define IPIC_IRQ_LINE9 9 +#define IPIC_IRQ_LINE7 7 #define EXT_IRQ_LINE_COMMON 0 #include "timer.h" @@ -154,8 +155,11 @@ csrw mie, zero // disable all interrupts li t0, IRQ_LINES_ADDR sh zero, (t0) // set all exterinal interrupt lines low + li t0, IRQ_LINES_MASK + li t1, 0xFFFFF + sw t1, (t0) // Enable Interrupt Mask #ifdef IPIC_ENABLED - li t0, IPIC_IRQ_LINE9 + li t0, IPIC_IRQ_LINE7 csrw IPIC_IDX, t0 // set IPIC to expect interupt on line 9... li t0, (IPIC_ICSR_IE | IPIC_ICSR_IM) csrw IPIC_ICSR, t0 // ....enable interrupt,set edge interrupt mode @@ -164,7 +168,7 @@ csrs mie, t0 // enable external interrupt li t0, TRIG_EXT_IRQ_ADDR #ifdef IPIC_ENABLED - li t1, (1 << IPIC_IRQ_LINE9) + li t1, (1 << IPIC_IRQ_LINE7) #else li t1, (1 << EXT_IRQ_LINE_COMMON) #endif
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index 97b1d80..44caa21 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -77,9 +77,9 @@ `include "uprj_netlists.v" `include "mt48lc8m8a2.v" `include "is62wvs1288.v" +`include "user_reg_map.v" -`define ADDR_SPACE_PINMUX 32'h3002_0000 localparam [31:0] YCR1_SIM_EXIT_ADDR = 32'h0000_00F8; localparam [31:0] YCR1_SIM_PRINT_ADDR = 32'hF000_0000; @@ -231,9 +231,8 @@ $dumpvars(1, user_risc_regress_tb); $dumpvars(1, user_risc_regress_tb.u_top); $dumpvars(0, user_risc_regress_tb.u_top.u_riscv_top); - $dumpvars(0, user_risc_regress_tb.u_top.u_qspi_master); $dumpvars(0, user_risc_regress_tb.u_top.u_intercon); - $dumpvars(0, user_risc_regress_tb.u_top.u_mbist); + $dumpvars(0, user_risc_regress_tb.u_top.u_pinmux); end `endif @@ -282,29 +281,29 @@ $display("Monitor: Core reset removal"); // Remove Wb Reset - wb_user_core_write('h3080_0000,'h1); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; //------------ fuse_mhartid= 0x00 - wb_user_core_write('h3002_0004,'h0); + //wb_user_core_write('h3002_0004,'h0); repeat (2) @(posedge clock); #1; // Remove WB and SPI Reset, Keep SDARM and CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); // CS#2 Switch to QSPI Mode - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); // Enable the DCACHE Remap to SRAM region //wb_user_core_write('h3080_000C,{4'b0000,4'b1111, 24'h0}); // // Remove all the reset - wb_user_core_write('h3080_0000,'h8F); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); end
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v index 4636dce..004f8d7 100644 --- a/verilog/dv/uart_master/uart_master_tb.v +++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -23,6 +23,8 @@ `include "caravel_netlists.v" `include "spiflash.v" `include "uart_agent.v" +`include "user_reg_map.v" +`define ADDR_SPACE_PINMUX 32'h3002_0000 module uart_master_tb; reg clock; @@ -133,7 +135,7 @@ // Remove Wb Reset - uartm_reg_write('h3080_0000,'h1); + uartm_reg_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; @@ -141,19 +143,19 @@ $display("Monitor: Writing expected value"); test_fail = 0; - uartm_reg_write(32'h30020058,32'h11223344); - uartm_reg_write(32'h3002005C,32'h22334455); - uartm_reg_write(32'h30020060,32'h33445566); - uartm_reg_write(32'h30020064,32'h44556677); - uartm_reg_write(32'h30020068,32'h55667788); - uartm_reg_write(32'h3002006C,32'h66778899); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899); - uartm_reg_read_check(32'h30020058,32'h11223344); - uartm_reg_read_check(32'h3002005C,32'h22334455); - uartm_reg_read_check(32'h30020060,32'h33445566); - uartm_reg_read_check(32'h30020064,32'h44556677); - uartm_reg_read_check(32'h30020068,32'h55667788); - uartm_reg_read_check(32'h3002006C,32'h66778899); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899); $display("###################################################"); if(test_fail == 0) begin
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index dedd260..9ee701c 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -75,6 +75,7 @@ `timescale 1 ns/10 ps `include "uprj_netlists.v" +`include "user_reg_map.v" module user_basic_tb; @@ -182,67 +183,67 @@ // cfg_usb_clk_ctrl = reg_0[31:24]; $display("Step-1, CPU: CLOCK1, RTC: CLOCK2 *2, USB: CLOCK2, WBS:CLOCK1"); test_step = 1; - wb_user_core_write('h3080_0000,{8'h0,4'h0,8'h0,4'h0,8'h00}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h0,4'h0,8'h0,4'h0,8'h00}); clock_monitor(CLK1_PERIOD,CLK2_PERIOD*2,CLK2_PERIOD,CLK1_PERIOD); $display("Step-2, CPU: CLOCK2, RTC: CLOCK2/(2+1), USB: CLOCK2/2, WBS:CLOCK2"); test_step = 2; - wb_user_core_write('h3080_0000,{8'h80,4'h8,8'h1,4'h8,8'h00}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h80,4'h8,8'h1,4'h8,8'h00}); clock_monitor(CLK2_PERIOD,(3)*CLK2_PERIOD,2*CLK2_PERIOD,CLK2_PERIOD); $display("Step-3, CPU: CLOCK1/2, RTC: CLOCK2/(2+2), USB: CLOCK2/(2+1), WBS:CLOCK1/2"); test_step = 3; - wb_user_core_write('h3080_0000,{8'h81,4'h4,8'h2,4'h4,8'h00}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h81,4'h4,8'h2,4'h4,8'h00}); clock_monitor(2*CLK1_PERIOD,(4)*CLK2_PERIOD,3*CLK2_PERIOD,2*CLK1_PERIOD); $display("Step-4, CPU: CLOCK1/3, RTC: CLOCK2/(2+3), USB: CLOCK2/(2+2), WBS:CLOCK1/3"); test_step = 4; - wb_user_core_write('h3080_0000,{8'h82,4'h5,8'h3,4'h5,8'h00}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h82,4'h5,8'h3,4'h5,8'h00}); clock_monitor(3*CLK1_PERIOD,5*CLK2_PERIOD,4*CLK2_PERIOD,3*CLK1_PERIOD); $display("Step-5, CPU: CLOCK1/4, RTC: CLOCK2/(2+4), USB: CLOCK2/(2+3), WBS:CLOCK1/4"); test_step = 5; - wb_user_core_write('h3080_0000,{8'h83,4'h6,8'h4,4'h6,8'h00}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h83,4'h6,8'h4,4'h6,8'h00}); clock_monitor(4*CLK1_PERIOD,6*CLK2_PERIOD,5*CLK2_PERIOD,4*CLK1_PERIOD); $display("Step-6, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+5), USB: CLOCK2/(2+4), WBS:CLOCK1/(2+3)"); test_step = 6; - wb_user_core_write('h3080_0000,{8'h84,4'h7,8'h5,4'h7,8'h00}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h84,4'h7,8'h5,4'h7,8'h00}); clock_monitor(5*CLK1_PERIOD,7*CLK2_PERIOD,6*CLK2_PERIOD,5*CLK1_PERIOD); $display("Step-7, CPU: CLOCK2/(2), RTC: CLOCK2/(2+6), USB: CLOCK2/(2+5), WBS:CLOCK2/(2)"); test_step = 7; - wb_user_core_write('h3080_0000,{8'h85,4'hC,8'h6,4'hC,8'h00}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h85,4'hC,8'h6,4'hC,8'h00}); clock_monitor(2*CLK2_PERIOD,8*CLK2_PERIOD,7*CLK2_PERIOD,2*CLK2_PERIOD); $display("Step-8, CPU: CLOCK2/3, RTC: CLOCK2/(2+7), USB: CLOCK2/(2+6), WBS:CLOCK2/3"); test_step = 8; - wb_user_core_write('h3080_0000,{8'h86,4'hD,8'h7,4'hD,8'h00}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h86,4'hD,8'h7,4'hD,8'h00}); clock_monitor(3*CLK2_PERIOD,9*CLK2_PERIOD,8*CLK2_PERIOD,3*CLK2_PERIOD); $display("Step-9, CPU: CLOCK2/4, RTC: CLOCK2/(2+8), USB: CLOCK2/(2+7), WBS:CLOCK2/4"); test_step = 9; - wb_user_core_write('h3080_0000,{8'h87,4'hE,8'h8,4'hE,8'h00}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h87,4'hE,8'h8,4'hE,8'h00}); clock_monitor(4*CLK2_PERIOD,10*CLK2_PERIOD,9*CLK2_PERIOD,4*CLK2_PERIOD); $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+128), USB: CLOCK2/(2+8), WBS:CLOCK1/(2+3)"); test_step = 10; - wb_user_core_write('h3080_0000,{8'h88,4'hF,8'h80,4'hF,8'h00}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h88,4'hF,8'h80,4'hF,8'h00}); clock_monitor(5*CLK2_PERIOD,130*CLK2_PERIOD,10*CLK2_PERIOD,5*CLK2_PERIOD); $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+255), USB: CLOCK2/(2+9), WBS:CLOCK2/(2+3)"); test_step = 10; - wb_user_core_write('h3080_0000,{8'h89,4'hF,8'hFF,4'hF,8'h00}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h89,4'hF,8'hFF,4'hF,8'h00}); clock_monitor(5*CLK2_PERIOD,257*CLK2_PERIOD,11*CLK2_PERIOD,5*CLK2_PERIOD); $display("###################################################"); $display("Monitor: Checking the chip signature :"); // Remove Wb/PinMux Reset - wb_user_core_write('h3080_0000,'h1); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); - wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343); - wb_user_core_read_check(32'h3002005C,read_data,32'h1003_2022); - wb_user_core_read_check(32'h30020060,read_data,32'h0003_8000); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h1603_2022); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0003_9000); end
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index f0bed30..148833e 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -65,16 +65,9 @@ `timescale 1 ns / 1 ns -`include "s25fl256s.sv" `include "uprj_netlists.v" -`include "mt48lc8m8a2.v" `include "i2c_slave_model.v" - - -`define ADDR_SPACE_UART 32'h3001_0000 -`define ADDR_SPACE_I2CM 32'h3001_0040 -`define ADDR_SPACE_PINMUX 32'h3002_0000 - +`include "user_reg_map.v" module tb_top; @@ -151,18 +144,18 @@ repeat (10) @(posedge clock); #1; // Enable I2M Block & WB Reset and Enable I2CM Mux Select - wb_user_core_write('h3080_0000,'h01); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h01); // Enable I2C Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h200); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h200); // Remove i2m reset - wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h010); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h010); repeat (100) @(posedge clock); @(posedge clock); - $display("---------- Initialize I2C Master ----------"); + $display("---------- Initialize I2C Master: %x ----------",`ADDR_SPACE_I2CM); //Wrire Prescale registers wb_user_core_write(`ADDR_SPACE_I2CM+(8'h0<<2),8'hC7); @@ -352,48 +345,6 @@ end `endif -//------------------------------------------------------ -// Integrate the Serial flash with qurd support to -// user core using the gpio pads -// ---------------------------------------------------- - - wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; - // Creating Pad Delay - wire #1 io_oeb_29 = io_oeb[29]; - wire #1 io_oeb_30 = io_oeb[30]; - wire #1 io_oeb_31 = io_oeb[31]; - wire #1 io_oeb_32 = io_oeb[32]; - tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; - tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; - tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; - tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; - - assign io_in[29] = flash_io0; - assign io_in[30] = flash_io1; - assign io_in[31] = flash_io2; - assign io_in[32] = flash_io3; - - - // Quard flash - s25fl256s #(.mem_file_name("user_uart.hex"), - .otp_file_name("none"), - .TimingModel("S25FL512SAGMFI010_F_30pF")) - u_spi_flash_256mb - ( - // Data Inputs/Outputs - .SI (flash_io0), - .SO (flash_io1), - // Controls - .SCK (flash_clk), - .CSNeg (flash_csb), - .WPNeg (flash_io2), - .HOLDNeg (flash_io3), - .RSTNeg (!wb_rst_i) - - ); - - //--------------------------- // I2C
diff --git a/verilog/dv/user_pwm/Makefile b/verilog/dv/user_pwm/Makefile new file mode 100644 index 0000000..220c33c --- /dev/null +++ b/verilog/dv/user_pwm/Makefile
@@ -0,0 +1,97 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +## Caravel Pointers +CARAVEL_ROOT ?= ../../../caravel +CARAVEL_PATH ?= $(CARAVEL_ROOT) +CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel +CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog +CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl +CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel + + +## User Project Pointers +UPRJ_VERILOG_PATH ?= ../../../verilog +UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl +UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl +UPRJ_BEHAVIOURAL_MODELS = ../model +UPRJ_BEHAVIOURAL_AGENTS = ../agents +UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes +UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/i2cm/src/includes +UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/usb1_host/src/includes + +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf + +## RISCV GCC +GCC_PATH?=/ef/apps/bin +GCC_PREFIX?=riscv32-unknown-elf +PDK_PATH?=/opt/pdk/sky130A + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF + +.SUFFIXES: + +PATTERN = user_pwm + +all: ${PATTERN:=.vcd} + + +vvp: ${PATTERN:=.vvp} + +%.vvp: %_tb.v +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ + -I $(UPRJ_INCLUDE_PATH3) \ + $< -o $@ + else + iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ + -I $(UPRJ_INCLUDE_PATH3) \ + $< -o $@ + endif +else + iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + $< -o $@ +endif + +%.vcd: %.vvp + vvp $< + +%.hex: + echo @"This is user boot test, noting to compile the mangment core code" + + +# ---- Clean ---- + +clean: + rm -f *.vvp *.vcd *.log *.fst + +.PHONY: clean hex all
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v new file mode 100644 index 0000000..575d604 --- /dev/null +++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -0,0 +1,454 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Standalone User validation Test bench //// +//// //// +//// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// +//// http://www.opencores.org/cores/yifive/ //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// pwm interfaface through External WB i/F. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 01 Oct 2021, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns / 1 ns + + +`define TB_GLBL user_pwm_tb + +`include "uprj_netlists.v" +`include "user_reg_map.v" + + +module user_pwm_tb; + reg clock; + reg wb_rst_i; + reg power1, power2; + reg power3, power4; + + reg wbd_ext_cyc_i; // strobe/request + reg wbd_ext_stb_i; // strobe/request + reg [31:0] wbd_ext_adr_i; // address + reg wbd_ext_we_i; // write + reg [31:0] wbd_ext_dat_i; // data output + reg [3:0] wbd_ext_sel_i; // byte enable + + wire [31:0] wbd_ext_dat_o; // data input + wire wbd_ext_ack_o; // acknowlegement + wire wbd_ext_err_o; // error + + // User I/O + wire [37:0] io_oeb; + wire [37:0] io_out; + wire [37:0] io_in; + + + reg [1:0] spi_chip_no; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + reg test_fail; + reg [31:0] read_data; + reg [31:0] OneMsPeriod; + integer test_step; + wire clock_mon; + + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + OneMsPeriod = 1000; + clock = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(1, `TB_GLBL); + $dumpvars(0, `TB_GLBL.u_top.u_wb_host); + $dumpvars(0, `TB_GLBL.u_top.u_pinmux); + $dumpvars(0, `TB_GLBL.u_top.u_intercon); + end + `endif + + initial begin + $dumpon; + + #200; // Wait for reset removal + repeat (10) @(posedge clock); + $display("Monitor: Standalone User Risc Boot Test Started"); + + // Remove Wb Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + // Enable PWM Multi Functional Ports + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h03F); + + repeat (2) @(posedge clock); + #1; + + // Remove the reset + // Remove WB and SPI/UART Reset, Keep CORE under Reset + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); + + // config 1us based on system clock - 1000/25ns = 40 + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39); + + test_fail = 0; + repeat (200) @(posedge clock); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + + $display("Step-1, PWM-0: 1ms/2 = 500Hz; PWM-1: 1ms/3; PWM-2: 1ms/4, PWM-3: 1ms/5, PWM-4: 1ms/6, PWM-5: 1ms/7"); + test_step = 1; + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM0,'h0000_0000); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM1,'h0000_0001); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM2,'h0001_0001); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM3,'h0001_0002); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM4,'h0002_0002); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM5,'h0002_0003); + pwm_monitor(OneMsPeriod*2,OneMsPeriod*3,OneMsPeriod*4,OneMsPeriod*5,OneMsPeriod*6,OneMsPeriod*7); + + repeat (100) @(posedge clock); + // $display("+1000 cycles"); + + if(test_fail == 0) begin + `ifdef GL + $display("Monitor: PWM Mode (GL) Passed"); + `else + $display("Monitor: PWM Mode (RTL) Passed"); + `endif + end else begin + `ifdef GL + $display("Monitor: PWM Mode (GL) Failed"); + `else + $display("Monitor: PWM Mode (RTL) Failed"); + `endif + end + $display("###################################################"); + $finish; + end + + initial begin + wb_rst_i <= 1'b1; + #100; + wb_rst_i <= 1'b0; // Release reset + end +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + +wire pwm0 = io_out[4]; +wire pwm1 = io_out[8]; +wire pwm2 = io_out[9]; +wire pwm3 = io_out[12]; +wire pwm4 = io_out[13]; +wire pwm5 = io_out[14]; + + +task pwm_monitor; +input [31:0] pwm0_period; +input [31:0] pwm1_period; +input [31:0] pwm2_period; +input [31:0] pwm3_period; +input [31:0] pwm4_period; +input [31:0] pwm5_period; +begin + force clock_mon = pwm0; + check_clock_period("PWM0 Clock",pwm0_period); + release clock_mon; + + force clock_mon = pwm1; + check_clock_period("PWM1 Clock",pwm1_period); + release clock_mon; + + force clock_mon = pwm2; + check_clock_period("PWM2 Clock",pwm2_period); + release clock_mon; + + force clock_mon = pwm3; + check_clock_period("PWM3 Clock",pwm3_period); + release clock_mon; + + force clock_mon = pwm4; + check_clock_period("PWM4 Clock",pwm4_period); + release clock_mon; + + force clock_mon = pwm5; + check_clock_period("PWM5 Clock",pwm5_period); + release clock_mon; +end +endtask + + +//---------------------------------- +// Check the clock period +//---------------------------------- +task check_clock_period; +input [127:0] clk_name; +input [31:0] clk_period; // in NS +time prev_t, next_t, periodd; +begin + $timeformat(-12,3,"ns",10); + repeat(1) @(posedge clock_mon); + repeat(1) @(posedge clock_mon); + prev_t = $realtime; + repeat(2) @(posedge clock_mon); + next_t = $realtime; + periodd = (next_t-prev_t)/2; + periodd = (periodd)/1e3; + if(clk_period != periodd) begin + $display("STATUS: FAIL => %s Exp Period: %d ms Rxd: %d ms",clk_name,clk_period,periodd); + test_fail = 1; + end else begin + $display("STATUS: PASS => %s Period: %d ms ",clk_name,clk_period); + end +end +endtask + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (1'b1), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in ('1) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + + end +`endif + + + +//---------------------------------------------------- +// Task +// -------------------------------------------------- +task test_err; +begin + test_fail = 1; +end +endtask + +task wb_user_core_write; +input [31:0] address; +input [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h1; // write + wbd_ext_dat_i =data; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read; +input [31:0] address; +output [31:0] data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + `TB_GLBL.test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask + + +`ifdef GL + +wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; + +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; +wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; + +`endif + +/** +`ifdef GL +//----------------------------------------------------------------------------- +// RISC IMEM amd DMEM Monitoring TASK +//----------------------------------------------------------------------------- + +`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top + +always@(posedge `RISC_CORE.wb_clk) begin + if(`RISC_CORE.wbd_imem_ack_i) + $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i); + if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o); + if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i); +end + +`endif +**/ + +endmodule +`default_nettype wire
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v index 4a35096..5b5f7a4 100644 --- a/verilog/dv/user_qspi/user_qspi_tb.v +++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -83,25 +83,8 @@ `include "uprj_netlists.v" `include "mt48lc8m8a2.v" `include "is62wvs1288.v" +`include "user_reg_map.v" - // REGISTER MAP - `define QSPIM_GLBL_CTRL 32'h10000000 - `define QSPIM_DMEM_G0_RD_CTRL 32'h10000004 - `define QSPIM_DMEM_G0_WR_CTRL 32'h10000008 - `define QSPIM_DMEM_G1_RD_CTRL 32'h1000000C - `define QSPIM_DMEM_G1_WR_CTRL 32'h10000010 - - `define QSPIM_DMEM_CS_AMAP 32'h10000014 - `define QSPIM_DMEM_CA_AMASK 32'h10000018 - - `define QSPIM_IMEM_CTRL1 32'h1000001C - `define QSPIM_IMEM_CTRL2 32'h10000020 - `define QSPIM_IMEM_ADDR 32'h10000024 - `define QSPIM_IMEM_WDATA 32'h10000028 - `define QSPIM_IMEM_RDATA 32'h1000002C - `define QSPIM_SPI_STATUS 32'h10000030 - - `define ADDR_SPACE_PINMUX 32'h3002_0000 module user_qspi_tb; reg clock; @@ -219,97 +202,97 @@ $display("Monitor: Standalone User Risc Boot Test Started"); // Remove Wb Reset - wb_user_core_write('h3080_0000,'h1); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; // Remove only WB and SPI Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h2); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h2); - wb_user_core_write('h3080_0004,'h0); // Change the Bank Sel 0 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 test_fail = 0; repeat (200) @(posedge clock); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 // CS#2 SSPI Indirect RAM READ ACCESS- - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h03020100); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000004); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h07060504); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000008); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0b0a0908); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000000C); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0f0e0d0c); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h03020100); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000004); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h07060504); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000008); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0b0a0908); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000000C); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0f0e0d0c); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h11111111); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000204); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h22222222); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000208); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h33333333); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000020C); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h44444444); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h11111111); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000204); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h22222222); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000208); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h33333333); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000020C); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h44444444); // CS#2 SSPI Indiect Write DATA - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00112233); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h44556677); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h8899AABB); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'hCCDDEEFF); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00112233); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h44556677); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h8899AABB); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'hCCDDEEFF); // CS#2 SSPI Indirect READ DATA - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00112233); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h44556677); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h8899AABB); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'hCCDDEEFF); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00112233); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h44556677); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h8899AABB); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'hCCDDEEFF); // CS#2 Switch to QSPI Mode - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); // CS#2 QUAD Indirect Write DATA - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h01234557); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h89ABCDEF); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h12345678); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h9ABCDEF0); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h01234557); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h89ABCDEF); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h12345678); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h9ABCDEF0); // CS#2 QUAD Indirect READ DATA - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h01234557); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h89ABCDEF); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h12345678); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9ABCDEF0); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h01234557); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h89ABCDEF); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h12345678); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9ABCDEF0); // CS#2 Switch From QSPI to SSPI Mode - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'hFF}); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'hFF}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); ///////////////////// End of CS#1 Indirect Memory Access Testing /////////////////////////////////// $display("#############################################"); $display(" Read Identification (RDID:0x9F) "); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,2'b00,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h9F}); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00190201); + wb_user_core_write(`ADDR_SPACE_QSPI+`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,2'b00,P_SINGLE,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h9F}); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00190201); $display("#############################################"); $display("Testing Direct SPI Memory Read "); $display(" SPI Mode: QDDR (Dual 4 bit) "); @@ -317,25 +300,25 @@ $display("SEQ: Command -> Address -> Read Data "); $display("#############################################"); // QDDR Config - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0100,2'b10,P_MODE_SWITCH_AT_ADDR,P_QDDR,P_SINGLE,8'h00,8'hED}); - wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 - wb_user_core_read_check(32'h00000200,read_data,32'h00000093); - wb_user_core_read_check(32'h00000204,read_data,32'h00000113); - wb_user_core_read_check(32'h00000208,read_data,32'h00000193); - wb_user_core_read_check(32'h0000020C,read_data,32'h00000213); - wb_user_core_read_check(32'h00000210,read_data,32'h00000293); - wb_user_core_read_check(32'h00000214,read_data,32'h00000313); - wb_user_core_read_check(32'h00000218,read_data,32'h00000393); - wb_user_core_read_check(32'h0000021C,read_data,32'h00000413); - wb_user_core_read_check(32'h00000300,read_data,32'h0005A023); - wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591); - wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5); - wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); - wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); - wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h03130291); - wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_QSPI+`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0100,2'b10,P_MODE_SWITCH_AT_ADDR,P_QDDR,P_SINGLE,8'h00,8'hED}); + wb_user_core_write(`ADDR_SPACE_QSPI+`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630); $dumpoff; $display("#############################################"); $display("Testing Direct SPI Memory Read "); @@ -343,50 +326,50 @@ $display("Prefetch : 1DW, OPCODE:READ(0x3) "); $display("SEQ: Command -> Address -> Read Data "); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAR,4'b0000,2'b10,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,8'h00,8'h03}); - wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 - wb_user_core_read_check(32'h00000200,read_data,32'h00000093); - wb_user_core_read_check(32'h00000204,read_data,32'h00000113); - wb_user_core_read_check(32'h00000208,read_data,32'h00000193); - wb_user_core_read_check(32'h0000020C,read_data,32'h00000213); - wb_user_core_read_check(32'h00000210,read_data,32'h00000293); - wb_user_core_read_check(32'h00000214,read_data,32'h00000313); - wb_user_core_read_check(32'h00000218,read_data,32'h00000393); - wb_user_core_read_check(32'h0000021C,read_data,32'h00000413); - wb_user_core_read_check(32'h00000300,read_data,32'h0005A023); - wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591); - wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5); - wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); - wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); - wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h03130291); - wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAR,4'b0000,2'b10,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,8'h00,8'h03}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read "); $display(" SPI Mode: Normal/Single Bit "); $display("Prefetch : 1DW, OPCODE:FASTREAD(0xB) "); $display("SEQ: Command -> Address -> Dummy -> Read Data"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CADR,4'b0000,2'b10,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,8'h00,8'h0B}); - wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 - wb_user_core_read_check(32'h00000200,read_data,32'h00000093); - wb_user_core_read_check(32'h00000204,read_data,32'h00000113); - wb_user_core_read_check(32'h00000208,read_data,32'h00000193); - wb_user_core_read_check(32'h0000020C,read_data,32'h00000213); - wb_user_core_read_check(32'h00000210,read_data,32'h00000293); - wb_user_core_read_check(32'h00000214,read_data,32'h00000313); - wb_user_core_read_check(32'h00000218,read_data,32'h00000393); - wb_user_core_read_check(32'h0000021C,read_data,32'h00000413); - wb_user_core_read_check(32'h00000300,read_data,32'h0005A023); - wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591); - wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5); - wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); - wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); - wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h03130291); - wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CADR,4'b0000,2'b10,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,8'h00,8'h0B}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read "); @@ -394,25 +377,25 @@ $display("Prefetch : 1DW, OPCODE:DOR(0x3B) "); $display("SEQ: Command -> Address -> Dummy -> Read Data"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CADR,4'b0000,2'b10,P_MODE_SWITCH_AT_DATA,P_DOUBLE,P_SINGLE,8'h00,8'h3B}); - wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 - wb_user_core_read_check(32'h00000200,read_data,32'h00000093); - wb_user_core_read_check(32'h00000204,read_data,32'h00000113); - wb_user_core_read_check(32'h00000208,read_data,32'h00000193); - wb_user_core_read_check(32'h0000020C,read_data,32'h00000213); - wb_user_core_read_check(32'h00000210,read_data,32'h00000293); - wb_user_core_read_check(32'h00000214,read_data,32'h00000313); - wb_user_core_read_check(32'h00000218,read_data,32'h00000393); - wb_user_core_read_check(32'h0000021C,read_data,32'h00000413); - wb_user_core_read_check(32'h00000300,read_data,32'h0005A023); - wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591); - wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5); - wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); - wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); - wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h03130291); - wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CADR,4'b0000,2'b10,P_MODE_SWITCH_AT_DATA,P_DOUBLE,P_SINGLE,8'h00,8'h3B}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read with Prefetch"); @@ -420,302 +403,302 @@ $display("Prefetch : 8DW, OPCODE:URAD READ(0xEB) "); $display("SEQ: Command -> Address -> Dummy -> Read Data"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); - wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 - wb_user_core_read_check(32'h00000200,read_data,32'h00000093); - wb_user_core_read_check(32'h00000204,read_data,32'h00000113); - wb_user_core_read_check(32'h00000208,read_data,32'h00000193); - wb_user_core_read_check(32'h0000020C,read_data,32'h00000213); - wb_user_core_read_check(32'h00000210,read_data,32'h00000293); - wb_user_core_read_check(32'h00000214,read_data,32'h00000313); - wb_user_core_read_check(32'h00000218,read_data,32'h00000393); - wb_user_core_read_check(32'h0000021C,read_data,32'h00000413); - wb_user_core_read_check(32'h00000300,read_data,32'h0005A023); - wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591); - wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5); - wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); - wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); - wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h03130291); - wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read with Prefetch:3DW"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); - wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 - wb_user_core_read_check(32'h00000200,read_data,32'h00000093); - wb_user_core_read_check(32'h00000204,read_data,32'h00000113); - wb_user_core_read_check(32'h00000208,read_data,32'h00000193); - wb_user_core_read_check(32'h0000020C,read_data,32'h00000213); - wb_user_core_read_check(32'h00000210,read_data,32'h00000293); - wb_user_core_read_check(32'h00000214,read_data,32'h00000313); - wb_user_core_read_check(32'h00000218,read_data,32'h00000393); - wb_user_core_read_check(32'h0000021C,read_data,32'h00000413); - wb_user_core_read_check(32'h00000300,read_data,32'h0005A023); - wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591); - wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5); - wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); - wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); - wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h03130291); - wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read with Prefetch:2DW"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); - wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 - wb_user_core_read_check(32'h00000200,read_data,32'h00000093); - wb_user_core_read_check(32'h00000204,read_data,32'h00000113); - wb_user_core_read_check(32'h00000208,read_data,32'h00000193); - wb_user_core_read_check(32'h0000020C,read_data,32'h00000213); - wb_user_core_read_check(32'h00000210,read_data,32'h00000293); - wb_user_core_read_check(32'h00000214,read_data,32'h00000313); - wb_user_core_read_check(32'h00000218,read_data,32'h00000393); - wb_user_core_read_check(32'h0000021C,read_data,32'h00000413); - wb_user_core_read_check(32'h00000300,read_data,32'h0005A023); - wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591); - wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5); - wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); - wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); - wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h03130291); - wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read with Prefetch:1DW"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); - wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 - wb_user_core_read_check(32'h00000200,read_data,32'h00000093); - wb_user_core_read_check(32'h00000204,read_data,32'h00000113); - wb_user_core_read_check(32'h00000208,read_data,32'h00000193); - wb_user_core_read_check(32'h0000020C,read_data,32'h00000213); - wb_user_core_read_check(32'h00000210,read_data,32'h00000293); - wb_user_core_read_check(32'h00000214,read_data,32'h00000313); - wb_user_core_read_check(32'h00000218,read_data,32'h00000393); - wb_user_core_read_check(32'h0000021C,read_data,32'h00000413); - wb_user_core_read_check(32'h00000300,read_data,32'h0005A023); - wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591); - wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5); - wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); - wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); - wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h03130291); - wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read with Prefetch:7DW"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); - wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 - wb_user_core_read_check(32'h00000200,read_data,32'h00000093); - wb_user_core_read_check(32'h00000204,read_data,32'h00000113); - wb_user_core_read_check(32'h00000208,read_data,32'h00000193); - wb_user_core_read_check(32'h0000020C,read_data,32'h00000213); - wb_user_core_read_check(32'h00000210,read_data,32'h00000293); - wb_user_core_read_check(32'h00000214,read_data,32'h00000313); - wb_user_core_read_check(32'h00000218,read_data,32'h00000393); - wb_user_core_read_check(32'h0000021C,read_data,32'h00000413); - wb_user_core_read_check(32'h00000300,read_data,32'h0005A023); - wb_user_core_read_check(32'h00000304,read_data,32'h9DE30591); - wb_user_core_read_check(32'h00000308,read_data,32'h02B7FEE5); - wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); - wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); - wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h03130291); - wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00000313); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00000413); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000300,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000304,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000308,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000030C,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000310,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000314,read_data,32'h004902B7); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display(" Testing Single Word Indirect SPI Memory Read"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000204); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000208); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000020C); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000210); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000214); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000313); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000218); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000393); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000021C); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000413); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000304); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000308); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000030C); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000310); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000314); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h004902B7); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000318); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h03130291); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000031C); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000204); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000208); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000020C); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000210); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000214); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000313); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000218); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000393); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000021C); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000413); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000304); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000308); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000030C); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000310); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000314); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h004902B7); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000318); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h03130291); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000031C); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'ha0230630); repeat (100) @(posedge clock); $display("#############################################"); $display(" Testing Two Word Indirect SPI Memory Read"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h8,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000208); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000210); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000313); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000218); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000393); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000413); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000308); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000310); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h004902B7); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000318); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h03130291); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h8,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000208); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000210); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000313); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000218); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000413); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000308); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000310); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h004902B7); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000318); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'ha0230630); repeat (100) @(posedge clock); $display("#############################################"); $display(" Testing Three Word Indirect SPI Memory Read"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'hC,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000020C); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000313); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000030C); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h004902B7); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'hC,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000020C); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000313); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h0000030C); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h004902B7); repeat (100) @(posedge clock); $display("#############################################"); $display(" Testing Four Word Indirect SPI Memory Read"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000210); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000313); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000393); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000413); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000310); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h004902B7); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h03130291); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000210); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000313); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000413); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000310); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h004902B7); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'ha0230630); repeat (100) @(posedge clock); $display("#############################################"); $display(" Testing Five Word Indirect SPI Memory Read"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h14,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h14,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023); $display("#############################################"); $display(" Testing Eight Word Indirect SPI Memory Read"); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h20,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000093); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000113); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000193); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000213); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000293); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000313); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000393); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00000413); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000300); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0005A023); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h43050049); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0062A023); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h004902B7); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h03130291); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'ha0230630); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h20,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000093); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000113); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000193); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000213); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000293); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000313); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000393); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00000413); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000300); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0005A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h9DE30591); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h02B7FEE5); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h43050049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h0062A023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h004902B7); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h03130291); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'ha0230630); $display("#############################################"); $display(" Sector Erase Command "); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 // WEN COMMAND - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06}); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); // Sector Erase - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b10,P_FSM_CA,8'h00,8'hD8}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b10,P_FSM_CA,8'h00,8'hD8}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); // RDSR - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05}); read_data = 32'hFFFF_FFFF; while (read_data[1:0] == 2'b11) begin - wb_user_core_read(`QSPIM_IMEM_RDATA,read_data); + wb_user_core_read(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data); repeat (10) @(posedge clock); end @@ -723,435 +706,435 @@ $display(" Page Write Command Address: 0x00 "); $display("#############################################"); // WEN COMMAND - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06}); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); // Page Programing - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010000); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010001); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010002); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010003); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010004); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010005); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010006); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010007); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010008); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010009); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010010); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010011); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010012); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010013); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010014); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010015); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010016); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010017); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010018); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010019); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010020); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010021); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010022); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010023); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010024); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010025); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010026); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010027); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010028); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010029); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010030); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010031); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010032); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010033); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010034); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010035); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010036); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010037); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010038); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010039); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010040); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010041); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010042); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010043); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010044); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010045); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010046); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010047); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010048); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010049); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010050); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010051); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010052); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010053); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010054); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010055); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010056); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010057); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010058); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00010059); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010000); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010001); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010002); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010003); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010004); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010005); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010006); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010007); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010008); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010009); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010010); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010011); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010012); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010013); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010014); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010015); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010016); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010017); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010018); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010019); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010020); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010021); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010022); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010023); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010024); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010025); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010026); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010027); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010028); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010029); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010030); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010031); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010032); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010033); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010034); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010035); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010036); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010037); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010038); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010039); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010040); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010041); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010042); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010043); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010044); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010045); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010046); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010047); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010048); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010049); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010050); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010051); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010052); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010053); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010054); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010055); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010056); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010057); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010058); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00010059); // RDSR - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05}); read_data = 32'hFFFF_FFFF; while (read_data[1:0] == 2'b11) begin - wb_user_core_read(`QSPIM_IMEM_RDATA,read_data); + wb_user_core_read(`ADDR_SPACE_QSPI+`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data); repeat (10) @(posedge clock); end $display("#############################################"); $display(" Page Read through Direct Access "); $display("#############################################"); - wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 - wb_user_core_read_check(32'h00000000,read_data,32'h00010000); - wb_user_core_read_check(32'h00000004,read_data,32'h00010001); - wb_user_core_read_check(32'h00000008,read_data,32'h00010002); - wb_user_core_read_check(32'h0000000C,read_data,32'h00010003); - wb_user_core_read_check(32'h00000010,read_data,32'h00010004); - wb_user_core_read_check(32'h00000014,read_data,32'h00010005); - wb_user_core_read_check(32'h00000018,read_data,32'h00010006); - wb_user_core_read_check(32'h0000001C,read_data,32'h00010007); - wb_user_core_read_check(32'h00000020,read_data,32'h00010008); - wb_user_core_read_check(32'h00000024,read_data,32'h00010009); - wb_user_core_read_check(32'h00000028,read_data,32'h00010010); - wb_user_core_read_check(32'h0000002C,read_data,32'h00010011); - wb_user_core_read_check(32'h00000030,read_data,32'h00010012); - wb_user_core_read_check(32'h00000034,read_data,32'h00010013); - wb_user_core_read_check(32'h00000038,read_data,32'h00010014); - wb_user_core_read_check(32'h0000003C,read_data,32'h00010015); - wb_user_core_read_check(32'h00000040,read_data,32'h00010016); - wb_user_core_read_check(32'h00000044,read_data,32'h00010017); - wb_user_core_read_check(32'h00000048,read_data,32'h00010018); - wb_user_core_read_check(32'h0000004C,read_data,32'h00010019); - wb_user_core_read_check(32'h00000050,read_data,32'h00010020); - wb_user_core_read_check(32'h00000054,read_data,32'h00010021); - wb_user_core_read_check(32'h00000058,read_data,32'h00010022); - wb_user_core_read_check(32'h0000005C,read_data,32'h00010023); - wb_user_core_read_check(32'h00000060,read_data,32'h00010024); - wb_user_core_read_check(32'h00000064,read_data,32'h00010025); - wb_user_core_read_check(32'h00000068,read_data,32'h00010026); - wb_user_core_read_check(32'h0000006C,read_data,32'h00010027); - wb_user_core_read_check(32'h00000070,read_data,32'h00010028); - wb_user_core_read_check(32'h00000074,read_data,32'h00010029); - wb_user_core_read_check(32'h00000078,read_data,32'h00010030); - wb_user_core_read_check(32'h0000007C,read_data,32'h00010031); - wb_user_core_read_check(32'h00000080,read_data,32'h00010032); - wb_user_core_read_check(32'h00000084,read_data,32'h00010033); - wb_user_core_read_check(32'h00000088,read_data,32'h00010034); - wb_user_core_read_check(32'h0000008C,read_data,32'h00010035); - wb_user_core_read_check(32'h00000090,read_data,32'h00010036); - wb_user_core_read_check(32'h00000094,read_data,32'h00010037); - wb_user_core_read_check(32'h00000098,read_data,32'h00010038); - wb_user_core_read_check(32'h0000009C,read_data,32'h00010039); - wb_user_core_read_check(32'h000000A0,read_data,32'h00010040); - wb_user_core_read_check(32'h000000A4,read_data,32'h00010041); - wb_user_core_read_check(32'h000000A8,read_data,32'h00010042); - wb_user_core_read_check(32'h000000AC,read_data,32'h00010043); - wb_user_core_read_check(32'h000000B0,read_data,32'h00010044); - wb_user_core_read_check(32'h000000B4,read_data,32'h00010045); - wb_user_core_read_check(32'h000000B8,read_data,32'h00010046); - wb_user_core_read_check(32'h000000BC,read_data,32'h00010047); - wb_user_core_read_check(32'h000000C0,read_data,32'h00010048); - wb_user_core_read_check(32'h000000C4,read_data,32'h00010049); - wb_user_core_read_check(32'h000000C8,read_data,32'h00010050); - wb_user_core_read_check(32'h000000CC,read_data,32'h00010051); - wb_user_core_read_check(32'h000000D0,read_data,32'h00010052); - wb_user_core_read_check(32'h000000D4,read_data,32'h00010053); - wb_user_core_read_check(32'h000000D8,read_data,32'h00010054); - wb_user_core_read_check(32'h000000DC,read_data,32'h00010055); - wb_user_core_read_check(32'h000000E0,read_data,32'h00010056); - wb_user_core_read_check(32'h000000E4,read_data,32'h00010057); - wb_user_core_read_check(32'h000000E8,read_data,32'h00010058); - wb_user_core_read_check(32'h000000EC,read_data,32'h00010059); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000000,read_data,32'h00010000); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000004,read_data,32'h00010001); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000008,read_data,32'h00010002); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000000C,read_data,32'h00010003); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000010,read_data,32'h00010004); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000014,read_data,32'h00010005); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000018,read_data,32'h00010006); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000001C,read_data,32'h00010007); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000020,read_data,32'h00010008); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000024,read_data,32'h00010009); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000028,read_data,32'h00010010); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000002C,read_data,32'h00010011); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000030,read_data,32'h00010012); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000034,read_data,32'h00010013); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000038,read_data,32'h00010014); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000003C,read_data,32'h00010015); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000040,read_data,32'h00010016); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000044,read_data,32'h00010017); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000048,read_data,32'h00010018); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000004C,read_data,32'h00010019); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000050,read_data,32'h00010020); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000054,read_data,32'h00010021); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000058,read_data,32'h00010022); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000005C,read_data,32'h00010023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000060,read_data,32'h00010024); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000064,read_data,32'h00010025); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000068,read_data,32'h00010026); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000006C,read_data,32'h00010027); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000070,read_data,32'h00010028); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000074,read_data,32'h00010029); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000078,read_data,32'h00010030); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000007C,read_data,32'h00010031); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000080,read_data,32'h00010032); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000084,read_data,32'h00010033); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000088,read_data,32'h00010034); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000008C,read_data,32'h00010035); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000090,read_data,32'h00010036); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000094,read_data,32'h00010037); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000098,read_data,32'h00010038); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000009C,read_data,32'h00010039); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000A0,read_data,32'h00010040); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000A4,read_data,32'h00010041); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000A8,read_data,32'h00010042); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000AC,read_data,32'h00010043); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000B0,read_data,32'h00010044); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000B4,read_data,32'h00010045); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000B8,read_data,32'h00010046); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000BC,read_data,32'h00010047); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000C0,read_data,32'h00010048); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000C4,read_data,32'h00010049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000C8,read_data,32'h00010050); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000CC,read_data,32'h00010051); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000D0,read_data,32'h00010052); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000D4,read_data,32'h00010053); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000D8,read_data,32'h00010054); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000DC,read_data,32'h00010055); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000E0,read_data,32'h00010056); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000E4,read_data,32'h00010057); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000E8,read_data,32'h00010058); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000000EC,read_data,32'h00010059); repeat (100) @(posedge clock); $display("#############################################"); $display(" Page Read through Indirect Access "); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000000); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010000); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010001); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010002); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010003); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010004); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010005); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010006); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010007); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010008); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010009); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010010); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010011); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010012); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010013); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010014); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010015); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010016); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010017); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010018); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010019); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010020); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010021); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010022); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010023); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010024); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010025); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010026); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010027); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010028); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010029); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010030); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010031); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010032); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010033); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010034); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010035); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010036); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010037); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010038); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010039); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010040); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010041); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010042); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010043); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010044); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010045); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010046); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010047); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010048); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010049); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010050); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010051); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010052); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010053); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010054); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010055); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010056); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010057); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010058); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00010059); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010000); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010001); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010002); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010003); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010004); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010005); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010006); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010007); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010008); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010009); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010010); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010011); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010012); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010013); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010014); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010015); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010016); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010017); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010018); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010019); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010020); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010021); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010022); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010024); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010025); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010026); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010027); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010028); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010029); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010030); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010031); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010032); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010033); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010034); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010035); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010036); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010037); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010038); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010039); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010040); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010041); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010042); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010043); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010044); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010045); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010046); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010047); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010048); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010050); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010051); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010052); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010053); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010054); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010055); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010056); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010057); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010058); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00010059); repeat (100) @(posedge clock); $display("#############################################"); $display(" Page Write Command Address: 0x200 "); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 // WEN COMMAND - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06}); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h06}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0); // Page Programing - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020000); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020001); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020002); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020003); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020004); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020005); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020006); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020007); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020008); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020009); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020010); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020011); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020012); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020013); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020014); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020015); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020016); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020017); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020018); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020019); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020020); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020021); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020022); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020023); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020024); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020025); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020026); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020027); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020028); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020029); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020030); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020031); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020032); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020033); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020034); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020035); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020036); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020037); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020038); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020039); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020040); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020041); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020042); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020043); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020044); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020045); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020046); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020047); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020048); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020049); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020050); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020051); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020052); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020053); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020054); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020055); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020056); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020057); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020058); - wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00020059); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020000); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020001); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020002); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020003); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020004); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020005); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020006); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020007); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020008); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020009); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020010); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020011); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020012); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020013); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020014); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020015); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020016); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020017); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020018); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020019); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020020); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020021); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020022); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020023); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020024); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020025); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020026); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020027); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020028); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020029); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020030); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020031); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020032); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020033); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020034); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020035); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020036); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020037); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020038); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020039); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020040); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020041); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020042); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020043); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020044); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020045); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020046); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020047); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020048); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020049); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020050); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020051); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020052); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020053); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020054); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020055); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020056); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020057); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020058); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h00020059); // RDSR - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b00,P_FSM_CR,8'h00,8'h05}); read_data = 32'hFFFF_FFFF; while (read_data[1:0] == 2'b11) begin - wb_user_core_read(`QSPIM_IMEM_RDATA,read_data); + wb_user_core_read(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data); repeat (10) @(posedge clock); end $display("#############################################"); $display(" Page Read through Direct Access "); $display("#############################################"); - wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 - wb_user_core_read_check(32'h00000200,read_data,32'h00020000); - wb_user_core_read_check(32'h00000204,read_data,32'h00020001); - wb_user_core_read_check(32'h00000208,read_data,32'h00020002); - wb_user_core_read_check(32'h0000020C,read_data,32'h00020003); - wb_user_core_read_check(32'h00000210,read_data,32'h00020004); - wb_user_core_read_check(32'h00000214,read_data,32'h00020005); - wb_user_core_read_check(32'h00000218,read_data,32'h00020006); - wb_user_core_read_check(32'h0000021C,read_data,32'h00020007); - wb_user_core_read_check(32'h00000220,read_data,32'h00020008); - wb_user_core_read_check(32'h00000224,read_data,32'h00020009); - wb_user_core_read_check(32'h00000228,read_data,32'h00020010); - wb_user_core_read_check(32'h0000022C,read_data,32'h00020011); - wb_user_core_read_check(32'h00000230,read_data,32'h00020012); - wb_user_core_read_check(32'h00000234,read_data,32'h00020013); - wb_user_core_read_check(32'h00000238,read_data,32'h00020014); - wb_user_core_read_check(32'h0000023C,read_data,32'h00020015); - wb_user_core_read_check(32'h00000240,read_data,32'h00020016); - wb_user_core_read_check(32'h00000244,read_data,32'h00020017); - wb_user_core_read_check(32'h00000248,read_data,32'h00020018); - wb_user_core_read_check(32'h0000024C,read_data,32'h00020019); - wb_user_core_read_check(32'h00000250,read_data,32'h00020020); - wb_user_core_read_check(32'h00000254,read_data,32'h00020021); - wb_user_core_read_check(32'h00000258,read_data,32'h00020022); - wb_user_core_read_check(32'h0000025C,read_data,32'h00020023); - wb_user_core_read_check(32'h00000260,read_data,32'h00020024); - wb_user_core_read_check(32'h00000264,read_data,32'h00020025); - wb_user_core_read_check(32'h00000268,read_data,32'h00020026); - wb_user_core_read_check(32'h0000026C,read_data,32'h00020027); - wb_user_core_read_check(32'h00000270,read_data,32'h00020028); - wb_user_core_read_check(32'h00000274,read_data,32'h00020029); - wb_user_core_read_check(32'h00000278,read_data,32'h00020030); - wb_user_core_read_check(32'h0000027C,read_data,32'h00020031); - wb_user_core_read_check(32'h00000280,read_data,32'h00020032); - wb_user_core_read_check(32'h00000284,read_data,32'h00020033); - wb_user_core_read_check(32'h00000288,read_data,32'h00020034); - wb_user_core_read_check(32'h0000028C,read_data,32'h00020035); - wb_user_core_read_check(32'h00000290,read_data,32'h00020036); - wb_user_core_read_check(32'h00000294,read_data,32'h00020037); - wb_user_core_read_check(32'h00000298,read_data,32'h00020038); - wb_user_core_read_check(32'h0000029C,read_data,32'h00020039); - wb_user_core_read_check(32'h000002A0,read_data,32'h00020040); - wb_user_core_read_check(32'h000002A4,read_data,32'h00020041); - wb_user_core_read_check(32'h000002A8,read_data,32'h00020042); - wb_user_core_read_check(32'h000002AC,read_data,32'h00020043); - wb_user_core_read_check(32'h000002B0,read_data,32'h00020044); - wb_user_core_read_check(32'h000002B4,read_data,32'h00020045); - wb_user_core_read_check(32'h000002B8,read_data,32'h00020046); - wb_user_core_read_check(32'h000002BC,read_data,32'h00020047); - wb_user_core_read_check(32'h000002C0,read_data,32'h00020048); - wb_user_core_read_check(32'h000002C4,read_data,32'h00020049); - wb_user_core_read_check(32'h000002C8,read_data,32'h00020050); - wb_user_core_read_check(32'h000002CC,read_data,32'h00020051); - wb_user_core_read_check(32'h000002D0,read_data,32'h00020052); - wb_user_core_read_check(32'h000002D4,read_data,32'h00020053); - wb_user_core_read_check(32'h000002D8,read_data,32'h00020054); - wb_user_core_read_check(32'h000002DC,read_data,32'h00020055); - wb_user_core_read_check(32'h000002E0,read_data,32'h00020056); - wb_user_core_read_check(32'h000002E4,read_data,32'h00020057); - wb_user_core_read_check(32'h000002E8,read_data,32'h00020058); - wb_user_core_read_check(32'h000002EC,read_data,32'h00020059); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000200,read_data,32'h00020000); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000204,read_data,32'h00020001); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000208,read_data,32'h00020002); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000020C,read_data,32'h00020003); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000210,read_data,32'h00020004); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000214,read_data,32'h00020005); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000218,read_data,32'h00020006); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000021C,read_data,32'h00020007); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000220,read_data,32'h00020008); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000224,read_data,32'h00020009); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000228,read_data,32'h00020010); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000022C,read_data,32'h00020011); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000230,read_data,32'h00020012); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000234,read_data,32'h00020013); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000238,read_data,32'h00020014); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000023C,read_data,32'h00020015); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000240,read_data,32'h00020016); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000244,read_data,32'h00020017); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000248,read_data,32'h00020018); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000024C,read_data,32'h00020019); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000250,read_data,32'h00020020); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000254,read_data,32'h00020021); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000258,read_data,32'h00020022); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000025C,read_data,32'h00020023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000260,read_data,32'h00020024); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000264,read_data,32'h00020025); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000268,read_data,32'h00020026); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000026C,read_data,32'h00020027); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000270,read_data,32'h00020028); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000274,read_data,32'h00020029); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000278,read_data,32'h00020030); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000027C,read_data,32'h00020031); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000280,read_data,32'h00020032); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000284,read_data,32'h00020033); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000288,read_data,32'h00020034); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000028C,read_data,32'h00020035); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000290,read_data,32'h00020036); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000294,read_data,32'h00020037); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h00000298,read_data,32'h00020038); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h0000029C,read_data,32'h00020039); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002A0,read_data,32'h00020040); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002A4,read_data,32'h00020041); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002A8,read_data,32'h00020042); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002AC,read_data,32'h00020043); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002B0,read_data,32'h00020044); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002B4,read_data,32'h00020045); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002B8,read_data,32'h00020046); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002BC,read_data,32'h00020047); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002C0,read_data,32'h00020048); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002C4,read_data,32'h00020049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002C8,read_data,32'h00020050); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002CC,read_data,32'h00020051); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002D0,read_data,32'h00020052); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002D4,read_data,32'h00020053); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002D8,read_data,32'h00020054); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002DC,read_data,32'h00020055); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002E0,read_data,32'h00020056); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002E4,read_data,32'h00020057); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002E8,read_data,32'h00020058); + wb_user_core_read_check(`ADDR_SPACE_QSPI+32'h000002EC,read_data,32'h00020059); repeat (10) @(posedge clock); $display("#############################################"); $display(" Page Read through Indirect Access "); $display("#############################################"); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); - wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'hF0,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_ADDR,32'h00000200); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020000); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020001); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020002); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020003); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020004); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020005); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020006); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020007); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020008); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020009); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020010); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020011); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020012); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020013); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020014); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020015); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020016); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020017); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020018); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020019); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020020); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020021); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020022); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020023); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020024); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020025); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020026); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020027); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020028); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020029); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020030); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020031); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020032); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020033); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020034); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020035); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020036); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020037); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020038); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020039); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020040); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020041); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020042); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020043); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020044); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020045); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020046); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020047); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020048); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020049); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020050); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020051); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020052); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020053); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020054); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020055); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020056); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020057); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020058); - wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00020059); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020000); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020001); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020002); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020003); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020004); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020005); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020006); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020007); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020008); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020009); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020010); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020011); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020012); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020013); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020014); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020015); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020016); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020017); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020018); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020019); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020020); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020021); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020022); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020023); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020024); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020025); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020026); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020027); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020028); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020029); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020030); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020031); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020032); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020033); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020034); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020035); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020036); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020037); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020038); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020039); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020040); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020041); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020042); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020043); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020044); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020045); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020046); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020047); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020048); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020049); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020050); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020051); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020052); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020053); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020054); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020055); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020056); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020057); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020058); + wb_user_core_read_check(`ADDR_SPACE_QSPI+`QSPIM_IMEM_RDATA,read_data,32'h00020059); repeat (100) @(posedge clock); // $display("+1000 cycles");
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v index 97b8ae9..2961b83 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v +++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -77,6 +77,7 @@ `include "s25fl256s.sv" `include "uprj_netlists.v" `include "mt48lc8m8a2.v" +`include "user_reg_map.v" `define ADDR_SPACE_PINMUX 32'h3002_0000 module user_risc_boot_tb; @@ -127,8 +128,8 @@ `ifdef WFDUMP initial begin - $dumpfile("risc_boot.vcd"); - $dumpvars(2, user_risc_boot_tb); + $dumpfile("simx.vcd"); + $dumpvars(3, user_risc_boot_tb); end `endif @@ -139,12 +140,12 @@ $display("Monitor: Standalone User Risc Boot Test Started"); // Remove Wb Reset - wb_user_core_write('h3080_0000,'h1); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; // Remove all the reset - wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); // Repeat cycles of 1000 clock edges as needed to complete testbench @@ -165,22 +166,22 @@ // 0x3000002C = 0x66778899; test_fail = 0; - wb_user_core_read(32'h30020058,read_data); + wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data); if(read_data != 32'h11223344) test_fail = 1; - wb_user_core_read(32'h3002005C,read_data); + wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data); if(read_data != 32'h22334455) test_fail = 1; - wb_user_core_read(32'h30020060,read_data); + wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data); if(read_data != 32'h33445566) test_fail = 1; - wb_user_core_read(32'h30020064,read_data); + wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data); if(read_data!= 32'h44556677) test_fail = 1; - wb_user_core_read(32'h30020068,read_data); + wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data); if(read_data!= 32'h55667788) test_fail = 1; - wb_user_core_read(32'h3002006C,read_data) ; + wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data) ; if(read_data != 32'h66778899) test_fail = 1;
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v index 8330de7..512e40d 100644 --- a/verilog/dv/user_sspi/user_sspi_tb.v +++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -66,16 +66,13 @@ `timescale 1 ns / 1 ns -// Note in caravel, 0x30XX_XXXX only come to user interface -// So, using wb_host bank select we have changing MSB address [31:24] = 0x10 -`define ADDR_SPACE_UART 32'h3001_0000 -`define ADDR_SPACE_SSPI 32'h3001_00C0 -`define ADDR_SPACE_PINMUX 32'h3002_0000 `define TB_GLBL user_sspi_tb `include "uprj_netlists.v" `include "is62wvs1288.v" +`include "user_reg_map.v" + module user_sspi_tb; @@ -141,23 +138,23 @@ $display("Monitor: Standalone User Risc Boot Test Started"); // Remove Wb Reset - wb_user_core_write('h3080_0000,'h1); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable SPI Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h400); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400); repeat (2) @(posedge clock); #1; // Remove the reset // Remove WB and SPI/UART Reset, Keep CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h01F); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); test_fail = 0; sspi_init(); repeat (200) @(posedge clock); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 $display("############################################"); $display(" Testing IS62/65WVS1288GALL SSRAM Read/Write Access "); $display("############################################");
diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile new file mode 100644 index 0000000..cda351b --- /dev/null +++ b/verilog/dv/user_timer/Makefile
@@ -0,0 +1,97 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +## Caravel Pointers +CARAVEL_ROOT ?= ../../../caravel +CARAVEL_PATH ?= $(CARAVEL_ROOT) +CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel +CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog +CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl +CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel + + +## User Project Pointers +UPRJ_VERILOG_PATH ?= ../../../verilog +UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl +UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl +UPRJ_BEHAVIOURAL_MODELS = ../model +UPRJ_BEHAVIOURAL_AGENTS = ../agents +UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes +UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/i2cm/src/includes +UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/usb1_host/src/includes + +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf + +## RISCV GCC +GCC_PATH?=/ef/apps/bin +GCC_PREFIX?=riscv32-unknown-elf +PDK_PATH?=/opt/pdk/sky130A + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF + +.SUFFIXES: + +PATTERN = user_timer + +all: ${PATTERN:=.vcd} + + +vvp: ${PATTERN:=.vvp} + +%.vvp: %_tb.v +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ + -I $(UPRJ_INCLUDE_PATH3) \ + $< -o $@ + else + iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ + -I $(UPRJ_INCLUDE_PATH3) \ + $< -o $@ + endif +else + iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + $< -o $@ +endif + +%.vcd: %.vvp + vvp $< + +%.hex: + echo @"This is user boot test, noting to compile the mangment core code" + + +# ---- Clean ---- + +clean: + rm -f *.vvp *.vcd *.log *.fst + +.PHONY: clean hex all
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v new file mode 100644 index 0000000..f2d7f11 --- /dev/null +++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -0,0 +1,488 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Standalone User validation Test bench //// +//// //// +//// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// +//// http://www.opencores.org/cores/yifive/ //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// timer interfaface through External WB i/F. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 01 Oct 2021, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns / 1 ns + +`define TB_GLBL user_timer_tb + +`include "uprj_netlists.v" +`include "user_reg_map.v" + + +module user_timer_tb; + reg clock; + reg wb_rst_i; + reg power1, power2; + reg power3, power4; + + reg wbd_ext_cyc_i; // strobe/request + reg wbd_ext_stb_i; // strobe/request + reg [31:0] wbd_ext_adr_i; // address + reg wbd_ext_we_i; // write + reg [31:0] wbd_ext_dat_i; // data output + reg [3:0] wbd_ext_sel_i; // byte enable + + wire [31:0] wbd_ext_dat_o; // data input + wire wbd_ext_ack_o; // acknowlegement + wire wbd_ext_err_o; // error + + // User I/O + wire [37:0] io_oeb; + wire [37:0] io_out; + wire [37:0] io_in; + + + reg [1:0] spi_chip_no; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + reg test_fail; + reg [31:0] read_data; + reg [31:0] OneUsPeriod; + integer test_step; + wire clock_mon; + + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + OneUsPeriod = 1; + clock = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(1, `TB_GLBL); + $dumpvars(0, `TB_GLBL.u_top.u_pinmux); + end + `endif + + initial begin + $dumpon; + + #200; // Wait for reset removal + repeat (10) @(posedge clock); + $display("Monitor: Standalone User Risc Boot Test Started"); + + // Remove Wb Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + repeat (2) @(posedge clock); + #1; + + // Remove the reset + // Remove WB and SPI/UART Reset, Keep CORE under Reset + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); + + // config 1us based on system clock - 1000/25ns = 40 + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39); + + // Enable Timer Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'h700); + + test_fail = 0; + repeat (200) @(posedge clock); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 10 + + $display("Step-1, Timer-0: 1us * 100 = 100us; Timer-1: 200us; Timer-2: 300us"); + test_step = 1; + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0001_0063); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0001_00C7); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0001_012B); + timer_monitor(OneUsPeriod*100,OneUsPeriod*200,OneUsPeriod*300); + + $display("Checking the Timer Interrupt generation and clearing"); + + // Disable the Timer - To avoid multiple interrupt generation + // during status check and interrupt clearing + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0000_0063); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0000_00C7); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0000_012B); + + wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data); + if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin + $display("STATUS: Timer Interrupt detected "); + // Clearing the Timer Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h700); + wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data); + if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin + $display("ERROR: Timer Interrupt not cleared "); + test_fail = 1; + end else begin + $display("STATUS: Timer Interrupt cleared "); + end + end else begin + $display("ERROR: Timer interrupt not detected "); + test_fail = 1; + end + + $display("Step-2, Timer-0: 1us * 200 = 200us; Timer-1: 300us; Timer-2: 400us"); + test_step = 2; + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0001_00C7); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0001_012B); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0001_018F); + timer_monitor(OneUsPeriod*200,OneUsPeriod*300,OneUsPeriod*400); + + $display("Checking the Timer Interrupt generation and clearing"); + + // Disable the Timer - To avoid multiple interrupt generation + // during status check and interrupt clearing + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0000_0063); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0000_00C7); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0000_012B); + + wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data); + if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin + $display("STATUS: Timer Interrupt detected "); + // Clearing the Timer Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h700); + wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data); + if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin + $display("ERROR: Timer Interrupt not cleared "); + test_fail = 1; + end else begin + $display("STATUS: Timer Interrupt cleared "); + end + end else begin + $display("ERROR: Timer interrupt not detected "); + test_fail = 1; + end + + repeat (100) @(posedge clock); + // $display("+1000 cycles"); + + if(test_fail == 0) begin + `ifdef GL + $display("Monitor: Timer Mode (GL) Passed"); + `else + $display("Monitor: Timer Mode (RTL) Passed"); + `endif + end else begin + `ifdef GL + $display("Monitor: Timer Mode (GL) Failed"); + `else + $display("Monitor: Timer Mode (RTL) Failed"); + `endif + end + $display("###################################################"); + $finish; + end + + initial begin + wb_rst_i <= 1'b1; + #100; + wb_rst_i <= 1'b0; // Release reset + end +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + +wire timer_intr0 = u_top.u_pinmux.timer_intr[0]; +wire timer_intr1 = u_top.u_pinmux.timer_intr[1]; +wire timer_intr2 = u_top.u_pinmux.timer_intr[2]; + +// Monitor the Timer interrupt interval +task timer_monitor; +input [31:0] timer0_period; +input [31:0] timer1_period; +input [31:0] timer2_period; +begin + force clock_mon = timer_intr0; + check_clock_period("Timer0",timer0_period); + release clock_mon; + + force clock_mon = timer_intr1; + check_clock_period("Timer1",timer1_period); + release clock_mon; + + force clock_mon = timer_intr2; + check_clock_period("Timer1",timer2_period); + release clock_mon; + +end +endtask + + +//---------------------------------- +// Check the clock period +//---------------------------------- +task check_clock_period; +input [127:0] clk_name; +input [31:0] clk_period; // in NS +time prev_t, next_t, periodd; +begin + $timeformat(-12,3,"ns",10); + repeat(1) @(posedge clock_mon); + repeat(1) @(posedge clock_mon); + prev_t = $realtime; + repeat(2) @(posedge clock_mon); + next_t = $realtime; + periodd = (next_t-prev_t)/2; + periodd = (periodd)/1e3; + if(clk_period != periodd) begin + $display("STATUS: FAIL => %s Exp Period: %d us Rxd: %d us",clk_name,clk_period,periodd); + test_fail = 1; + end else begin + $display("STATUS: PASS => %s Period: %d us ",clk_name,clk_period); + end +end +endtask + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (1'b1), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in ('1) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + + end +`endif + + + +//---------------------------------------------------- +// Task +// -------------------------------------------------- +task test_err; +begin + test_fail = 1; +end +endtask + +task wb_user_core_write; +input [31:0] address; +input [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h1; // write + wbd_ext_dat_i =data; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read; +input [31:0] address; +output [31:0] data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + `TB_GLBL.test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask + + +`ifdef GL + +wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; + +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; +wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; + +`endif + +/** +`ifdef GL +//----------------------------------------------------------------------------- +// RISC IMEM amd DMEM Monitoring TASK +//----------------------------------------------------------------------------- + +`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top + +always@(posedge `RISC_CORE.wb_clk) begin + if(`RISC_CORE.wbd_imem_ack_i) + $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i); + if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o); + if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i); +end + +`endif +**/ + +endmodule +`default_nettype wire
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index f60c07a..df5f4d6 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -78,12 +78,7 @@ `include "uprj_netlists.v" `include "mt48lc8m8a2.v" `include "uart_agent.v" - - -// Note in caravel, 0x30XX_XXXX only come to user interface -// So, using wb_host bank select we have changing MSB address [31:24] = 0x10 -`define ADDR_SPACE_UART 32'h3001_0000 -`define ADDR_SPACE_PINMUX 32'h3002_0000 +`include "user_reg_map.v" module user_uart_tb; @@ -178,15 +173,15 @@ $display("Monitor: Standalone User Uart Test Started"); // Remove Wb Reset - wb_user_core_write('h3080_0000,'h1); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable UART Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h100); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h100); repeat (2) @(posedge clock); #1; // Remove all the reset - wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); repeat (100) @(posedge clock); // wait for Processor Get Ready
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v index d41ff59..3f4f16e 100644 --- a/verilog/dv/user_uart_master/user_uart_master_tb.v +++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -68,6 +68,8 @@ `include "uprj_netlists.v" `include "uart_agent.v" +`include "user_reg_map.v" + `define ADDR_SPACE_UART 32'h3001_0000 @@ -192,7 +194,7 @@ // Remove Wb Reset - uartm_reg_write('h3080_0000,'h1); + uartm_reg_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); repeat (2) @(posedge clock); #1; @@ -200,19 +202,19 @@ $display("Monitor: Writing expected value"); test_fail = 0; - uartm_reg_write(32'h30020058,32'h11223344); - uartm_reg_write(32'h3002005C,32'h22334455); - uartm_reg_write(32'h30020060,32'h33445566); - uartm_reg_write(32'h30020064,32'h44556677); - uartm_reg_write(32'h30020068,32'h55667788); - uartm_reg_write(32'h3002006C,32'h66778899); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); + uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899); - uartm_reg_read_check(32'h30020058,32'h11223344); - uartm_reg_read_check(32'h3002005C,32'h22334455); - uartm_reg_read_check(32'h30020060,32'h33445566); - uartm_reg_read_check(32'h30020064,32'h44556677); - uartm_reg_read_check(32'h30020068,32'h55667788); - uartm_reg_read_check(32'h3002006C,32'h66778899); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); + uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
diff --git a/verilog/dv/user_usb/.user_usb_tb.v.swp b/verilog/dv/user_usb/.user_usb_tb.v.swp deleted file mode 100644 index 13fbb40..0000000 --- a/verilog/dv/user_usb/.user_usb_tb.v.swp +++ /dev/null Binary files differ
diff --git a/verilog/dv/user_usb/tests/.usb_test3.v.swp b/verilog/dv/user_usb/tests/.usb_test3.v.swp deleted file mode 100644 index 39e4f3b..0000000 --- a/verilog/dv/user_usb/tests/.usb_test3.v.swp +++ /dev/null Binary files differ
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v index 73e2b47..96f1446 100644 --- a/verilog/dv/user_usb/user_usb_tb.v +++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -40,16 +40,10 @@ `timescale 1 ns / 1 ns -// Note in caravel, 0x30XX_XXXX only come to user interface -// So, using wb_host bank select we have changing MSB address [31:24] = 0x10 -`define ADDR_SPACE_UART 32'h3001_0000 -`define ADDR_SPACE_USB 32'h3001_0080 -`define ADDR_SPACE_SSPI 32'h3001_00C0 -`define ADDR_SPACE_PINMUX 32'h3002_0000 - `define TB_GLBL user_usb_tb `define USB_BFM u_usb_agent +`include "user_reg_map.v" `include "uprj_netlists.v" `include "usb_agents.v" `include "test_control.v" @@ -176,22 +170,22 @@ wb_user_core_write('h3080_0000,'h1); // Enable SPI Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h400); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400); repeat (2) @(posedge clock); #1; // Set USB clock : 192/4 = 48Mhz - wb_user_core_write('h3080_0000,{8'h82,4'h0,8'h0,4'h0,8'h01}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h82,4'h0,8'h0,4'h0,8'h01}); // Remove the reset // Remove WB and SPI/UART Reset, Keep CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h03F); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h03F); test_fail = 0; repeat (200) @(posedge clock); - wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 10 //usb_test1;
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c index a4da212..f776eb4 100644 --- a/verilog/dv/wb_port/wb_port.c +++ b/verilog/dv/wb_port/wb_port.c
@@ -18,39 +18,14 @@ // This include is relative to $CARAVEL_PATH (see Makefile) #include "verilog/dv/caravel/defs.h" #include "verilog/dv/caravel/stub.c" +#include "../c_func/inc/user_reg_map.h" // User Project Slaves (0x3000_0000) #define reg_mprj_slave (*(volatile uint32_t*)0x30000000) -#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000) -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30020000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30020004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30020008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3002000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30020010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30020014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30020018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3002001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30020020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30020024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30020028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3002002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30020030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30020034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30020038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3002003C) -#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x30020040) -#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x30020044) -#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x30020048) -#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x3002004C) -#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x30020050) -#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x30020054) -#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x30020058) -#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x3002005C) -#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x30020060) -#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x30020064) -#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x30020068) -#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x3002006C) +#define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30080000) + + /* @@ -121,31 +96,30 @@ reg_mprj_wbhost_reg0 = 0x1; // Remove Reset - reg_mprj_globl_reg2 = 0x01F; + reg_pinmux_gbl_cfg0 = 0x01f; - if (reg_mprj_globl_reg0 != 0x82681301) bFail = 1; - if (reg_mprj_globl_reg1 != 0xA55AA55A) bFail = 1; + if (reg_pinmux_chip_id != 0x82681301) bFail = 1; - // Write software Write & Read Register - reg_mprj_globl_reg22 = 0x11223344; - reg_mprj_globl_reg23 = 0x22334455; - reg_mprj_globl_reg24 = 0x33445566; - reg_mprj_globl_reg25 = 0x44556677; - reg_mprj_globl_reg26 = 0x55667788; - reg_mprj_globl_reg27 = 0x66778899; + // write software write & read Register + reg_pinmux_soft_reg_1 = 0x11223344; + reg_pinmux_soft_reg_2 = 0x22334455; + reg_pinmux_soft_reg_3 = 0x33445566; + reg_pinmux_soft_reg_4 = 0x44556677; + reg_pinmux_soft_reg_5 = 0x55667788; + reg_pinmux_soft_reg_6 = 0x66778899; - if (reg_mprj_globl_reg22 != 0x11223344) bFail = 1; + if (reg_pinmux_soft_reg_1 != 0x11223344) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB610000; - if (reg_mprj_globl_reg23 != 0x22334455) bFail = 1; + if (reg_pinmux_soft_reg_2 != 0x22334455) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB620000; - if (reg_mprj_globl_reg24 != 0x33445566) bFail = 1; + if (reg_pinmux_soft_reg_3 != 0x33445566) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB630000; - if (reg_mprj_globl_reg25 != 0x44556677) bFail = 1; + if (reg_pinmux_soft_reg_4 != 0x44556677) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB640000; - if (reg_mprj_globl_reg26 != 0x55667788) bFail = 1; + if (reg_pinmux_soft_reg_5 != 0x55667788) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB650000; - if (reg_mprj_globl_reg27 != 0x66778899) bFail = 1; + if (reg_pinmux_soft_reg_6 != 0x66778899) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB660000; if(bFail == 0) {
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v index 99caccc..5f7e8a7 100644 --- a/verilog/dv/wb_port/wb_port_tb.v +++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -53,7 +53,7 @@ initial begin $dumpfile("simx.vcd"); $dumpvars(1, wb_port_tb); - $dumpvars(0, wb_port_tb.uut.soc); + //$dumpvars(0, wb_port_tb.uut.soc); //$dumpvars(1, wb_port_tb.uut.mprj); $dumpvars(1, wb_port_tb.uut.mprj.u_wb_host); $dumpvars(2, wb_port_tb.uut.mprj.u_pinmux);
diff --git a/verilog/rtl/lib/pulse_gen_type1.sv b/verilog/rtl/lib/pulse_gen_type1.sv index 838fe03..a0c260f 100644 --- a/verilog/rtl/lib/pulse_gen_type1.sv +++ b/verilog/rtl/lib/pulse_gen_type1.sv
@@ -5,7 +5,7 @@ //------------------------------------------------------------------------ module pulse_gen_type1( - output logic clk_pulse, + output logic clk_pulse_o, input logic clk, input logic reset_n, @@ -17,7 +17,7 @@ logic [WD-1:0] cnt; -assign clk_pulse = (cnt == 0) && trigger; +assign clk_pulse_o = (cnt == 0) && trigger; always @ (posedge clk or negedge reset_n) begin
diff --git a/verilog/rtl/lib/pulse_gen_type2.sv b/verilog/rtl/lib/pulse_gen_type2.sv index 9bc759e..c438d34 100644 --- a/verilog/rtl/lib/pulse_gen_type2.sv +++ b/verilog/rtl/lib/pulse_gen_type2.sv
@@ -5,7 +5,7 @@ module pulse_gen_type2 #(parameter WD = 10) ( - output logic clk_pulse, + output logic clk_pulse_o, input logic clk, input logic reset_n, @@ -19,15 +19,15 @@ always @ (posedge clk or negedge reset_n) begin if (reset_n == 1'b0) begin - cnt <= 'b0; - clk_pulse <= 'b0; + cnt <= 'b0; + clk_pulse_o <= 'b0; end else begin if(cnt == cfg_max_cnt) begin - cnt <= 0; - clk_pulse <= 1'b1; + cnt <= 0; + clk_pulse_o <= 1'b1; end else begin - cnt <= cnt +1; - clk_pulse <= 1'b0; + cnt <= cnt +1; + clk_pulse_o <= 1'b0; end end end
diff --git a/verilog/rtl/pinmux/src/gpio_intr.sv b/verilog/rtl/pinmux/src/gpio_intr.sv index 331918d..9bcefee 100644 --- a/verilog/rtl/pinmux/src/gpio_intr.sv +++ b/verilog/rtl/pinmux/src/gpio_intr.sv
@@ -1,6 +1,6 @@ // GPIO Interrupt Generation -module gpio_intr ( +module gpio_intr_gen ( input logic mclk ,// System clk input logic h_reset_n ,// system reset input logic [31:0] gpio_prev_indata ,// previously captured GPIO I/P pins data
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index 4446c89..94217f7 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -73,7 +73,6 @@ output logic reg_ack, // Risc configuration - output logic [31:0] fuse_mhartid, output logic [15:0] irq_lines, output logic soft_irq, output logic [2:0] user_irq, @@ -131,17 +130,31 @@ output logic pulse1m_mclk, output logic [31:0] pinmux_debug + + ); +logic sreset_n; // Sync Reset /* clock pulse */ //******************************************************** -logic pulse1u_mclk ;// 1 UsSecond Pulse for waveform Generator -logic pulse1s_mclk ;// 1Second Pulse for waveform Generator -logic [9:0] cfg_pulse_1us ;// 1us pulse generation config - +logic pulse_1us ; // 1 UsSecond Pulse for waveform Generator +logic pulse_1ms ; // 1 UsSecond Pulse for waveform Generator +logic pulse_1s ; // 1Second Pulse for waveform Generator +logic [9:0] cfg_pulse_1us ; // 1us pulse generation config + + +//--------------------------------------------------------- +// Timer Register +// ------------------------------------------------------- +logic [2:0] cfg_timer_update ; // CPU write to timer register +logic [18:0] cfg_timer0 ; // Timer-0 register +logic [18:0] cfg_timer1 ; // Timer-1 register +logic [18:0] cfg_timer2 ; // Timer-2 register +logic [2:0] timer_intr ; + //--------------------------------------------------- // 6 PWM variabled //--------------------------------------------------- @@ -218,11 +231,18 @@ .clk_out (wbd_clk_pinmux ) ); -gpio_intr u_gpio_intr ( +reset_sync u_rst_sync ( + .scan_mode (1'b0 ), + .dclk (mclk ), // Destination clock domain + .arst_n (h_reset_n ), // active low async reset + .srst_n (sreset_n ) + ); + +gpio_intr_gen u_gpio_intr ( // System Signals // Inputs .mclk (mclk ), - .h_reset_n (h_reset_n ), + .h_reset_n (sreset_n ), // GPIO cfg input pins .gpio_prev_indata (gpio_prev_indata ), @@ -242,38 +262,102 @@ // 1us pulse pulse_gen_type2 #(.WD(10)) u_pulse_1us ( - .clk_pulse (pulse1u_mclk), - .clk (mclk ), - .reset_n (h_reset_n ), - .cfg_max_cnt (cfg_pulse_1us) + .clk_pulse_o (pulse_1us ), + .clk (mclk ), + .reset_n (sreset_n ), + .cfg_max_cnt (cfg_pulse_1us ) ); // 1millisecond pulse pulse_gen_type1 u_pulse_1ms ( - .clk_pulse (pulse1m_mclk), - .clk (mclk ), - .reset_n (h_reset_n ), - .trigger (pulse1u_mclk) + .clk_pulse_o (pulse_1ms ), + .clk (mclk ), + .reset_n (sreset_n ), + .trigger (pulse_1us ) ); // 1 second pulse -pulse_gen_type2 u_pulse_1s ( +pulse_gen_type1 u_pulse_1s ( - .clk_pulse (pulse1s_mclk), - .clk (mclk ), - .reset_n (h_reset_n ), - .cfg_max_cnt (cfg_pulse_1us) + .clk_pulse_o (pulse_1s ), + .clk (mclk ), + .reset_n (sreset_n ), + .trigger (pulse_1ms ) ); + +// Timer + +wire cfg_timer0_enb = cfg_timer0[16]; +wire [1:0] cfg_timer0_clksel = cfg_timer0[18:17]; +wire [15:0] cfg_timer0_compare = cfg_timer0[15:0]; + +timer u_timer_0 + ( + .reset_n (sreset_n ),// system syn reset + .mclk (mclk ),// master clock + .pulse_1us (pulse_1us ), + .pulse_1ms (pulse_1ms ), + .pulse_1s (pulse_1s ), + + .cfg_timer_update (cfg_timer_update[0] ), + .cfg_timer_enb (cfg_timer0_enb ), + .cfg_timer_compare (cfg_timer0_compare ), + .cfg_timer_clksel (cfg_timer0_clksel ),// to select the timer 1us/1ms reference clock + + .timer_intr (timer_intr[0] ) + ); + +// Timer +wire cfg_timer1_enb = cfg_timer1[16]; +wire [1:0] cfg_timer1_clksel = cfg_timer1[18:17]; +wire [15:0] cfg_timer1_compare = cfg_timer1[15:0]; +timer u_timer_1 + ( + .reset_n (sreset_n ),// system syn reset + .mclk (mclk ),// master clock + .pulse_1us (pulse_1us ), + .pulse_1ms (pulse_1ms ), + .pulse_1s (pulse_1s ), + + .cfg_timer_update (cfg_timer_update[1] ), + .cfg_timer_enb (cfg_timer1_enb ), + .cfg_timer_compare (cfg_timer1_compare ), + .cfg_timer_clksel (cfg_timer1_clksel ),// to select the timer 1us/1ms reference clock + + .timer_intr (timer_intr[1] ) + ); + +// Timer +wire cfg_timer2_enb = cfg_timer2[16]; +wire [1:0] cfg_timer2_clksel = cfg_timer2[18:17]; +wire [15:0] cfg_timer2_compare = cfg_timer2[15:0]; +timer u_timer_2 + ( + .reset_n (sreset_n ),// system syn reset + .mclk (mclk ),// master clock + .pulse_1us (pulse_1us ), + .pulse_1ms (pulse_1ms ), + .pulse_1s (pulse_1s ), + + .cfg_timer_update (cfg_timer_update[2] ), + .cfg_timer_enb (cfg_timer2_enb ), + .cfg_timer_compare (cfg_timer2_compare ), + .cfg_timer_clksel (cfg_timer2_clksel ),// to select the timer 1us/1ms reference clock + + .timer_intr (timer_intr[2] ) + ); + + pinmux_reg u_pinmux_reg( // System Signals // Inputs .mclk (mclk ), - .h_reset_n (h_reset_n ), + .h_reset_n (sreset_n ), .cpu_core_rst_n (cpu_core_rst_n ), .cpu_intf_rst_n (cpu_intf_rst_n ), @@ -298,7 +382,6 @@ .ext_intr_in (ext_intr_in ), - .fuse_mhartid (fuse_mhartid ), .irq_lines (irq_lines ), .soft_irq (soft_irq ), .user_irq (user_irq ), @@ -338,22 +421,13 @@ // Outputs .gpio_prev_indata (gpio_prev_indata ) , - // BIST I/F - .bist_en ( ), - .bist_run ( ), - .bist_load ( ), - - .bist_sdi ( ), - .bist_shift ( ), - .bist_sdo ('b0 ), - - .bist_done ('b0 ), - .bist_error ('h0 ), - .bist_correct ('h0 ), - .bist_error_cnt0 ('h0 ), - .bist_error_cnt1 ('h0 ), - .bist_error_cnt2 ('h0 ), - .bist_error_cnt3 ('h0 ) + + .timer_intr (timer_intr ), + .cfg_timer_update (cfg_timer_update ), + .cfg_timer0 (cfg_timer0 ), + .cfg_timer1 (cfg_timer1 ), + .cfg_timer2 (cfg_timer2 ) + ); @@ -361,9 +435,9 @@ // 6 PWM Waveform Generator pwm u_pwm_0 ( .waveform (pwm_wfm[0] ), - .h_reset_n (h_reset_n ), + .h_reset_n (sreset_n ), .mclk (mclk ), - .pulse1m_mclk (pulse1m_mclk ), + .pulse1m_mclk (pulse_1ms ), .cfg_pwm_enb (cfg_pwm_enb[0] ), .cfg_pwm_high (cfg_pwm0_high ), .cfg_pwm_low (cfg_pwm0_low ) @@ -371,9 +445,9 @@ pwm u_pwm_1 ( .waveform (pwm_wfm[1] ), - .h_reset_n (h_reset_n ), + .h_reset_n (sreset_n ), .mclk (mclk ), - .pulse1m_mclk (pulse1m_mclk ), + .pulse1m_mclk (pulse_1ms ), .cfg_pwm_enb (cfg_pwm_enb[1] ), .cfg_pwm_high (cfg_pwm1_high ), .cfg_pwm_low (cfg_pwm1_low ) @@ -381,9 +455,9 @@ pwm u_pwm_2 ( .waveform (pwm_wfm[2] ), - .h_reset_n (h_reset_n ), + .h_reset_n (sreset_n ), .mclk (mclk ), - .pulse1m_mclk (pulse1m_mclk ), + .pulse1m_mclk (pulse_1ms ), .cfg_pwm_enb (cfg_pwm_enb[2] ), .cfg_pwm_high (cfg_pwm2_high ), .cfg_pwm_low (cfg_pwm2_low ) @@ -391,27 +465,27 @@ pwm u_pwm_3 ( .waveform (pwm_wfm[3] ), - .h_reset_n (h_reset_n ), + .h_reset_n (sreset_n ), .mclk (mclk ), - .pulse1m_mclk (pulse1m_mclk ), + .pulse1m_mclk (pulse_1ms ), .cfg_pwm_enb (cfg_pwm_enb[3] ), .cfg_pwm_high (cfg_pwm3_high ), .cfg_pwm_low (cfg_pwm3_low ) ); pwm u_pwm_4 ( .waveform (pwm_wfm[4] ), - .h_reset_n (h_reset_n ), + .h_reset_n (sreset_n ), .mclk (mclk ), - .pulse1m_mclk (pulse1m_mclk ), + .pulse1m_mclk (pulse_1ms ), .cfg_pwm_enb (cfg_pwm_enb[4] ), .cfg_pwm_high (cfg_pwm4_high ), .cfg_pwm_low (cfg_pwm4_low ) ); pwm u_pwm_5 ( .waveform (pwm_wfm[5] ), - .h_reset_n (h_reset_n ), + .h_reset_n (sreset_n ), .mclk (mclk ), - .pulse1m_mclk (pulse1m_mclk ), + .pulse1m_mclk (pulse_1ms ), .cfg_pwm_enb (cfg_pwm_enb[5] ), .cfg_pwm_high (cfg_pwm5_high ), .cfg_pwm_low (cfg_pwm5_low ) @@ -599,7 +673,7 @@ //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] if(cfg_pwm_enb[0]) digital_io_out[4] = pwm_wfm[0]; - if(cfg_port_d_dir_sel[3]) digital_io_out[4] = port_d_out[3]; + else if(cfg_port_d_dir_sel[3]) digital_io_out[4] = port_d_out[3]; //Pin-6 PD4 digital_io[5] if(cfg_port_d_dir_sel[4]) digital_io_out[5] = port_d_out[4];
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index 1b0d310..ebe3b76 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -65,7 +65,6 @@ input logic [1:0] ext_intr_in, // Risc configuration - output logic [31:0] fuse_mhartid, output logic [15:0] irq_lines, output logic soft_irq, output logic [2:0] user_irq, @@ -108,25 +107,13 @@ output logic [31:0] cfg_multi_func_sel ,// multifunction pins // Outputs - output logic [31:0] gpio_prev_indata, // prv data from GPIO I/P pins + output logic [31:0] gpio_prev_indata ,// prv data from GPIO I/P pins - // BIST I/F - output logic bist_en, - output logic bist_run, - output logic bist_load, - - output logic bist_sdi, - output logic bist_shift, - input logic bist_sdo, - - input logic bist_done, - input logic [3:0] bist_error, - input logic [3:0] bist_correct, - input logic [3:0] bist_error_cnt0, - input logic [3:0] bist_error_cnt1, - input logic [3:0] bist_error_cnt2, - input logic [3:0] bist_error_cnt3 - + input logic [2:0] timer_intr , + output logic [2:0] cfg_timer_update , + output logic [31:0] cfg_timer0 , + output logic [31:0] cfg_timer1 , + output logic [31:0] cfg_timer2 ); @@ -170,6 +157,9 @@ logic [31:0] reg_25; // Software-Reg4 logic [31:0] reg_26; // Software-Reg5 logic [31:0] reg_27; // Software-Reg6 +logic [31:0] reg_28; // Software-Reg6 +logic [31:0] reg_29; // Software-Reg6 +logic [31:0] reg_30; // Software-Reg6 logic cs_int; @@ -205,23 +195,12 @@ assign wb_req_pedge = (wb_req_d ==0) && (wb_req==1'b1); -//----------------------------------------------------------------- -// Reg 4/5 are BIST Serial I/F register and it takes minimum 32 -// cycle to respond ACK back -// ---------------------------------------------------------------- -wire ser_acc = sw_wr_en_30 | sw_rd_en_31; -wire non_ser_acc = reg_cs ? !ser_acc : 1'b0; -wire serial_ack; - always @ (posedge mclk or negedge h_reset_n) begin : preg_out_Seq if (h_reset_n == 1'b0) begin reg_rdata <= 'h0; reg_ack <= 1'b0; - end else if (ser_acc && serial_ack) begin - reg_rdata <= serail_dout ; - reg_ack <= 1'b1; - end else if (non_ser_acc && !reg_ack) begin + end else if (reg_cs && !reg_ack) begin reg_rdata <= reg_out ; reg_ack <= 1'b1; end else begin @@ -278,6 +257,7 @@ // Individual register assignments //----------------------------------------------------------------------- + // Chip ID // chip-id[3:0] mapping // 0 - YIFIVE (MPW-2) @@ -293,11 +273,22 @@ assign reg_0 = {manu_id,total_core,chip_id,chip_rev}; -//----------------------------------------------------------------------- -// reg-1, reset value = 32'hA55A_A55A -// ----------------------------------------------------------------- +//------------------------------------------ +// reg-2: GLBL_CFG_0 +//------------------------------------------ +wire [31:0] cfg_glb_ctrl = reg_1; -gen_32b_reg #(32'hA55A_A55A) u_reg_1 ( +ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n)); +ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n)); +ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n)); +ctech_buf u_buf_uart_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n)); +ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n)); +ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n)); + +ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0])); +ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1])); + +gen_32b_reg #(32'h0) u_reg_1 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -309,22 +300,9 @@ .data_out (reg_1 ) ); -assign fuse_mhartid = reg_1; - -//------------------------------------------ +//---------------------------------------------- // reg-2: GLBL_CFG_1 //------------------------------------------ -wire [31:0] cfg_glb_ctrl = reg_2; - -ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n)); -ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n)); -ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n)); -ctech_buf u_buf_uart_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n)); -ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n)); -ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n)); - -ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0])); -ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1])); gen_32b_reg #(32'h0) u_reg_2 ( //List of Inputs @@ -338,9 +316,12 @@ .data_out (reg_2 ) ); -//---------------------------------------------- -// reg-3: GLBL_CFG_1 -//------------------------------------------ +assign cfg_pulse_1us = reg_2[9:0]; +assign cfg_riscv_debug_sel = reg_2[31:30]; + +//----------------------------------------------------------------------- +// reg-3 : Global Interrupt Mask +//----------------------------------------------------------------------- gen_32b_reg #(32'h0) u_reg_3 ( //List of Inputs @@ -354,8 +335,58 @@ .data_out (reg_3 ) ); -assign cfg_pulse_1us = reg_3[9:0]; -assign cfg_riscv_debug_sel = reg_3[31:30]; +//----------------------------------------------------------------------- +// reg-4 : Global Interrupt Status +//----------------------------------------------------------------- +assign irq_lines = reg_3[15:0] & reg_4[15:0]; +assign soft_irq = reg_3[16] & reg_4[16]; +assign user_irq = reg_3[19:17]& reg_4[19:17]; + + +generic_register #(8,0 ) u_reg4_be0 ( + .we ({8{sw_wr_en_4 & + wr_be[0] }} ), + .data_in (sw_reg_wdata[7:0] ), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_4[7:0] ) + ); + + +wire [7:0] hware_intr_req = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr,timer_intr[2:0]}; + +generic_intr_stat_reg #(.WD(8), + .RESET_DEFAULT(0)) u_reg4_be1 ( + //inputs + .clk (mclk ), + .reset_n (h_reset_n ), + .reg_we ({8{sw_wr_en_4 & reg_ack & + wr_be[1] }} ), + .reg_din (sw_reg_wdata[15:8] ), + .hware_req (hware_intr_req ), + + //outputs + .data_out (reg_4[15:8] ) + ); + + + +generic_register #(4,0 ) u_reg4_be2 ( + .we ({4{sw_wr_en_4 & + wr_be[2] }} ), + .data_in (sw_reg_wdata[19:16]), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_4[19:16] ) + ); + +assign reg_4[31:20] = '0; + + //----------------------------------------------------------------------- // Logic for gpio_data_in //----------------------------------------------------------------------- @@ -365,41 +396,25 @@ always @ (posedge mclk or negedge h_reset_n) begin if (h_reset_n == 1'b0) begin - reg_4 <= 'h0 ; + reg_5 <= 'h0 ; gpio_in_data_s <= 32'd0; gpio_in_data_ss <= 32'd0; end else begin gpio_in_data_s <= gpio_in_data; gpio_in_data_ss <= gpio_in_data_s; - reg_4 <= gpio_in_data_ss; + reg_5 <= gpio_in_data_ss; end end -assign cfg_gpio_data_in = reg_4[31:0]; // to be used for edge interrupt detect +assign cfg_gpio_data_in = reg_5[31:0]; // to be used for edge interrupt detect assign gpio_prev_indata = gpio_in_data_ss; //----------------------------------------------------------------------- // Logic for cfg_gpio_out_data //----------------------------------------------------------------------- -assign cfg_gpio_out_data = reg_5[31:0]; // data to the GPIO control blk - -gen_32b_reg #(32'h0) u_reg_5 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_5 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_5 ) - ); -//----------------------------------------------------------------------- -// Logic for cfg_gpio_dir_sel -//----------------------------------------------------------------------- -assign cfg_gpio_dir_sel = reg_6[31:0]; // data to the GPIO O/P pins +assign cfg_gpio_out_data = reg_6[31:0]; // data to the GPIO control blk gen_32b_reg #(32'h0) u_reg_6 ( //List of Inputs @@ -413,9 +428,9 @@ .data_out (reg_6 ) ); //----------------------------------------------------------------------- -// Logic for cfg_gpio_out_type +// Logic for cfg_gpio_dir_sel //----------------------------------------------------------------------- -assign cfg_gpio_out_type = reg_7[31:0]; // to be used for read +assign cfg_gpio_dir_sel = reg_7[31:0]; // data to the GPIO O/P pins gen_32b_reg #(32'h0) u_reg_7 ( //List of Inputs @@ -428,54 +443,23 @@ //List of Outs .data_out (reg_7 ) ); - - //----------------------------------------------------------------------- -// reg-8 -//----------------------------------------------------------------- -assign irq_lines = reg_8[15:0]; -assign soft_irq = reg_8[16]; -assign user_irq = reg_8[19:17]; +// Logic for cfg_gpio_out_type +//----------------------------------------------------------------------- +assign cfg_gpio_out_type = reg_8[31:0]; // to be used for read - -generic_register #(8,0 ) u_reg8_be0 ( - .we ({8{sw_wr_en_8 & - wr_be[0] }} ), - .data_in (sw_reg_wdata[7:0] ), - .reset_n (h_reset_n ), - .clk (mclk ), +gen_32b_reg #(32'h0) u_reg_8 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_8 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), //List of Outs - .data_out (reg_8[7:0] ) - ); + .data_out (reg_8 ) + ); -generic_register #(3,0 ) u_reg8_be1_1 ( - .we ({3{sw_wr_en_8 & - wr_be[1] }} ), - .data_in (sw_reg_wdata[10:8] ), - .reset_n (h_reset_n ), - .clk (mclk ), - - //List of Outs - .data_out (reg_8[10:8] ) - ); - - -assign reg_8[15:11] = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr}; - - -generic_register #(4,0 ) u_reg8_be2 ( - .we ({4{sw_wr_en_8 & - wr_be[2] }} ), - .data_in (sw_reg_wdata[19:16]), - .reset_n (h_reset_n ), - .clk (mclk ), - - //List of Outs - .data_out (reg_8[19:16] ) - ); - -assign reg_8[31:20] = '0; //----------------------------------------------------------------------- @@ -497,67 +481,29 @@ // Interrupt posting is higher priority than int clear by host //-------------------------------------------------------- wire [31:0] gpio_int_status = reg_9; -always @(posedge mclk or negedge h_reset_n) -begin - if(~h_reset_n) - begin - reg_9[31:0] <= 32'h0; - end - else - begin - if(sw_wr_en_9 && wr_be[0]) - begin - reg_9[7:0] <= ((~sw_reg_wdata[7:0] & gpio_int_status[7:0]) | gpio_int_event[7:0]); - end - else if(sw_wr_en_10 && wr_be[0]) - begin - reg_9[7:0] <= ((sw_reg_wdata[7:0] | gpio_int_status[7:0]) | gpio_int_event[7:0]); - end - else - begin - reg_9[7:0] <= (gpio_int_status[7:0] | gpio_int_event[7:0]); - end - if(sw_wr_en_9 && wr_be[1]) - begin - reg_9[15:8] <= ((~sw_reg_wdata[15:8] & gpio_int_status[15:8]) | gpio_int_event[15:8]); - end - else if(sw_wr_en_10 && wr_be[1]) - begin - reg_9[15:8] <= ((sw_reg_wdata[15:8] | gpio_int_status[15:8]) | gpio_int_event[15:8]); - end - else - begin - reg_9[15:8] <= (gpio_int_status[15:8] | gpio_int_event[15:8]); - end - - if(sw_wr_en_9 && wr_be[2]) - begin - reg_9[23:16] <= ((~sw_reg_wdata[23:16] & gpio_int_status[23:16]) | gpio_int_event[23:16]); - end - else if(sw_wr_en_10 && wr_be[2]) - begin - reg_9[23:16] <= ((sw_reg_wdata[23:16] | gpio_int_status[23:16]) | gpio_int_event[23:16]); - end - else - begin - reg_9[23:16] <= (gpio_int_status[23:16] | gpio_int_event[23:16]); - end - - if(sw_wr_en_9 && wr_be[3]) - begin - reg_9[31:24] <= ((~sw_reg_wdata[31:24] & gpio_int_status[31:24]) | gpio_int_event[31:24]); - end - else if(sw_wr_en_10 && wr_be[3]) - begin - reg_9[31:24] <= ((sw_reg_wdata[31:24] | gpio_int_status[31:24]) | gpio_int_event[31:24]); - end - else - begin - reg_9[31:24] <= (gpio_int_status[31:24] | gpio_int_event[31:24]); - end - end -end +generic_intr_stat_reg #(.WD(32), + .RESET_DEFAULT(0)) u_reg_9 ( + //inputs + .clk (mclk ), + .reset_n (h_reset_n ), + .reg_we ({ + {8{sw_wr_en_9 & reg_ack & wr_be[2]}}, + {8{sw_wr_en_9 & reg_ack & wr_be[2]}}, + {8{sw_wr_en_9 & reg_ack & wr_be[1]}}, + {8{sw_wr_en_9 & reg_ack & wr_be[0]}} + } ), + .reg_din (sw_reg_wdata[31:0] ), + .hware_req (gpio_int_event | { + {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[31:24], + {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[23:16], + {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[15:8] , + {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[7:0] + } ), + + //outputs + .data_out (reg_9[31:0] ) + ); //------------------------------------------------- // Returns same value as interrupt status register //------------------------------------------------ @@ -769,7 +715,7 @@ //----------------------------------------- // Software Reg-2, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h1003_2022) u_reg_23 ( +gen_32b_reg #(32'h1603_2022) u_reg_23 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -782,9 +728,9 @@ ); //----------------------------------------- -// Software Reg-3: Poject Revison 3.8 = 0003800 +// Software Reg-3: Poject Revison 3.9 = 0003900 // ---------------------------------------- -gen_32b_reg #(32'h0003_8000) u_reg_24 ( +gen_32b_reg #(32'h0003_9000) u_reg_24 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -844,8 +790,12 @@ //----------------------------------------------------------------------- // reg-28 +// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle +// In first cycle, local register will be updated +// In second cycle, update indication sent to timer block // ----------------------------------------------------------------- -logic [31:0] cfg_bist_ctrl_1; +assign cfg_timer0 = reg_28[18:0]; +assign cfg_timer_update[0] = sw_wr_en_28 & reg_ack; gen_32b_reg #(32'h0) u_reg_28 ( //List of Inputs @@ -856,61 +806,51 @@ .data_in (sw_reg_wdata ), //List of Outs - .data_out (cfg_bist_ctrl_1[31:0] ) + .data_out (reg_28[31:0] ) ); - - -assign bist_en = cfg_bist_ctrl_1[0]; -assign bist_run = cfg_bist_ctrl_1[1]; -assign bist_load = cfg_bist_ctrl_1[2]; - - //----------------------------------------------------------------------- // reg-29 -//----------------------------------------------------------------- -logic [31:0] cfg_bist_status_1; +// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle +// In first cycle, local register will be updated +// In second cycle, update indication sent to timer block +// ----------------------------------------------------------------- +assign cfg_timer1 = reg_29[18:0]; +assign cfg_timer_update[1] = sw_wr_en_29 & reg_ack; -assign cfg_bist_status_1 = { bist_error_cnt3, 1'b0, bist_correct[3], bist_error[3], bist_done, - bist_error_cnt2, 1'b0, bist_correct[2], bist_error[2], bist_done, - bist_error_cnt1, 1'b0, bist_correct[1], bist_error[1], bist_done, - bist_error_cnt0, 1'b0, bist_correct[0], bist_error[0], bist_done - }; +gen_32b_reg #(32'h0) u_reg_29 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_29 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_29[31:0] ) + ); + //----------------------------------------------------------------------- -// reg-30 => Write to Serail I/F -// reg-31 => READ from Serail I/F -//----------------------------------------------------------------- -logic bist_sdi_int; -logic bist_shift_int; -logic bist_sdo_int; -logic [31:0] serail_dout; +// reg-30 +// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle +// In first cycle, local register will be updated +// In second cycle, update indication sent to timer block +// ----------------------------------------------------------------- +assign cfg_timer2 = reg_30[18:0]; +assign cfg_timer_update[2] = sw_wr_en_30 & reg_ack; -assign bist_sdo_int = bist_sdo; -assign bist_shift = bist_shift_int; -assign bist_sdi = bist_sdi_int ; - -ser_inf_32b u_ser_intf - ( - - // Master Port - .rst_n (h_reset_n), // Regular Reset signal - .clk (mclk), // System clock - .reg_wr (sw_wr_en_30 & wb_req_pedge), // Write Request - .reg_rd (sw_rd_en_31 & wb_req_pedge), // Read Request - .reg_wdata (sw_reg_wdata) , // data output - .reg_rdata (serail_dout), // data input - .reg_ack (serial_ack), // acknowlegement - - // Slave Port - .sdi (bist_sdi_int), // Serial SDI - .shift (bist_shift_int), // Shift Signal - .sdo (bist_sdo_int) // Serial SDO - - ); - - - +gen_32b_reg #(32'h0) u_reg_30 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_30 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_30[31:0] ) + ); //----------------------------------------------------------------------- // Register Read Path Multiplexer instantiation @@ -949,10 +889,10 @@ 5'b11001 : reg_out [31:0] = reg_25 [31:0]; 5'b11010 : reg_out [31:0] = reg_26 [31:0]; 5'b11011 : reg_out [31:0] = reg_27 [31:0]; - 5'b11100 : reg_out [31:0] = cfg_bist_ctrl_1 [31:0]; - 5'b11101 : reg_out [31:0] = cfg_bist_status_1 [31:0]; - 5'b11110 : reg_out [31:0] = serail_dout [31:0]; // Previous Shift Data - 5'b11111 : reg_out [31:0] = serail_dout [31:0]; // Latest Shift Data + 5'b11100 : reg_out [31:0] = reg_28 [31:0]; + 5'b11101 : reg_out [31:0] = reg_29 [31:0]; + 5'b11110 : reg_out [31:0] = reg_30 [31:0]; + 5'b11111 : reg_out [31:0] = 32'h0; default : reg_out [31:0] = 32'h0; endcase end
diff --git a/verilog/rtl/pinmux/src/timer.sv b/verilog/rtl/pinmux/src/timer.sv new file mode 100755 index 0000000..55b7349 --- /dev/null +++ b/verilog/rtl/pinmux/src/timer.sv
@@ -0,0 +1,66 @@ + +module timer + ( + input logic reset_n, // system syn reset + input logic mclk, // master clock + input logic pulse_1us, + input logic pulse_1ms, + input logic pulse_1s, + + input logic cfg_timer_enb, + input logic cfg_timer_update, + input logic [15:0] cfg_timer_compare, + input logic [1:0] cfg_timer_clksel, // to select the timer 1us/1ms reference clock + + output logic timer_intr + + ); + + + + +reg timer_hit_s1; +wire timer_hit; +reg [15:0] timer_counter; +wire timer_pulse; + + +// select between 1us timer and 1ms timer +assign timer_pulse = (cfg_timer_clksel == 2'b00) ? pulse_1us : + (cfg_timer_clksel == 2'b01) ? pulse_1ms : pulse_1s; + + +/************************************************ + Timer Counter +************************************************/ +always @(negedge reset_n or posedge mclk) +begin + if (!reset_n) + timer_counter <= 16'b0; + else if (cfg_timer_update || (timer_pulse && timer_hit)) + timer_counter <= cfg_timer_compare; + else if (timer_pulse && cfg_timer_enb) + timer_counter <= timer_counter - 1; +end + + + +/*********************************************** + Timer Interrupt Generation +***********************************************/ + assign timer_hit = (timer_counter == 1'b0); + + assign timer_intr = !timer_hit_s1 && timer_hit && cfg_timer_enb; + + + always @(negedge reset_n or posedge mclk) + begin + if (!reset_n) begin + timer_hit_s1 <= 1'b1; + end else begin + timer_hit_s1 <= timer_hit; + end + end + + +endmodule
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 9aa0469..21ebfe2 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -46,6 +46,7 @@ `include "pinmux/src/pinmux_reg.sv" `include "pinmux/src/gpio_intr.sv" `include "pinmux/src/pwm.sv" + `include "pinmux/src/timer.sv" `include "lib/pulse_gen_type1.sv" `include "lib/pulse_gen_type2.sv"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 3688747..3169451 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -195,6 +195,12 @@ //// 3.8 Mar 10 2022, Dinesh A //// //// 1. usb chip select bug inside uart_* wrapper //// //// 2. in wb_host, increased usb clk ctrl to 4 to 8 bit //// +//// 3.9 Mar 16 2022, Dinesh A //// +//// 1. 3 Timer added //// +//// 2. Pinmux Register address movement //// +//// 3. Risc fuse_mhartid is removed and internal tied //// +//// inside risc core //// +//// 4. caravel wb addressing issue restrict to 0x300FFFFF//// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -441,7 +447,6 @@ wire wbd_clk_pinmux ; wire wbd_int_rst_n ; -wire [31:0] fuse_mhartid ; wire [15:0] irq_lines ; wire soft_irq ; @@ -465,7 +470,6 @@ wire [3:0] cfg_cska_pinmux_rp ; // clock skew adjust for pinmux wire [3:0] cfg_cska_qspi_co_rp ; // clock skew adjust for global reg -wire [31:0] fuse_mhartid_rp ; // Repeater wire [15:0] irq_lines_rp ; // Repeater wire soft_irq_rp ; // Repeater @@ -670,8 +674,6 @@ .core_clk (cpu_clk ), .rtc_clk (rtc_clk ), - // Fuses - .fuse_mhartid (fuse_mhartid_rp ), // IRQ .irq_lines (irq_lines_rp ), @@ -909,7 +911,7 @@ wb_interconnect #( `ifndef SYNTHESIS .CH_CLK_WD (4 ), - .CH_DATA_WD (69 ) + .CH_DATA_WD (37 ) `endif ) u_intercon ( `ifdef USE_POWER_PINS @@ -930,7 +932,6 @@ soft_irq, irq_lines[15:0], - fuse_mhartid[31:0], cfg_cska_qspi_co[3:0], cfg_cska_pinmux[3:0], @@ -942,7 +943,6 @@ soft_irq_rp, irq_lines_rp[15:0], - fuse_mhartid_rp[31:0], cfg_cska_qspi_co_rp[3:0], cfg_cska_pinmux_rp[3:0], @@ -1145,7 +1145,6 @@ // Risc configuration - .fuse_mhartid (fuse_mhartid ), .irq_lines (irq_lines ), .soft_irq (soft_irq ), .user_irq (user_irq ),
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v new file mode 100644 index 0000000..1926c76 --- /dev/null +++ b/verilog/rtl/user_reg_map.v
@@ -0,0 +1,76 @@ + +// Note in caravel, 0x300X_XXXX only come to user interface +// So, using wb_host bank select we have changing MSB address [31:16] = 0x1000 +// +`define ADDR_SPACE_QSPI 32'h3000_0000 +`define ADDR_SPACE_UART 32'h3001_0000 +`define ADDR_SPACE_I2CM 32'h3001_0040 +`define ADDR_SPACE_USB 32'h3001_0080 +`define ADDR_SPACE_SSPI 32'h3001_00C0 +`define ADDR_SPACE_PINMUX 32'h3002_0000 +`define ADDR_SPACE_WBHOST 32'h3008_0000 + +//-------------------------------------------------- +// WB Host Register +//-------------------------------------------------- +`define WBHOST_GLBL_CFG 8'h00 // reg_0 - Global Config +`define WBHOST_BANK_SEL 8'h04 // reg_1 - Bank Select +`define WBHOST_CLK_CTRL1 8'h08 // reg_2 - Clock Control-1 +`define WBHOST_CLK_CTRL2 8'h0C // reg_3 - Clock Control-2 + +//-------------------------------------------------- +// Pinmux Register +// ------------------------------------------------- + +`define PINMUX_CHIP_ID 8'h00 // reg_0 - Chip ID +`define PINMUX_GBL_CFG0 8'h04 // reg_1 - Global Config-2 +`define PINMUX_GBL_CFG1 8'h08 // reg_2 - Global Config-1 +`define PINMUX_GBL_INTR_MSK 8'h0C // reg_3 - Global Interrupt Mask +`define PINMUX_GBL_INTR 8'h10 // reg_4 - Global Interrupt +`define PINMUX_GPIO_IDATA 8'h14 // reg_5 - GPIO Data In +`define PINMUX_GPIO_ODATA 8'h18 // reg_6 - GPIO Data Out +`define PINMUX_GPIO_DSEL 8'h1C // reg_7 - GPIO Direction Select +`define PINMUX_GPIO_TYPE 8'h20 // reg_8 - GPIO TYPE - Static/Waveform +`define PINMUX_GPIO_INTR_STAT 8'h24 // reg_9 - GPIO Interrupt status +`define PINMUX_GPIO_INTR_CLR 8'h24 // reg_9 - GPIO Interrupt Clear +`define PINMUX_GPIO_INTR_SET 8'h28 // reg_10 - GPIO Interrupt Set +`define PINMUX_GPIO_INTR_MASK 8'h2C // reg_11 - GPIO Interrupt Mask +`define PINMUX_GPIO_POS_INTR 8'h30 // reg_12 - GPIO Posedge Interrupt +`define PINMUX_GPIO_NEG_INTR 8'h34 // reg_13 - GPIO Neg Interrupt +`define PINMUX_GPIO_MULTI_FUNC 8'h38 // reg_14 - GPIO Multi Function +`define PINMUX_SOFT_REG_0 8'h3C // reg_15 - Soft Register +`define PINMUX_CFG_PWM0 8'h40 // reg_16 - PWM Reg-0 +`define PINMUX_CFG_PWM1 8'h44 // reg_17 - PWM Reg-1 +`define PINMUX_CFG_PWM2 8'h48 // reg_18 - PWM Reg-2 +`define PINMUX_CFG_PWM3 8'h4C // reg_19 - PWM Reg-3 +`define PINMUX_CFG_PWM4 8'h50 // reg_20 - PWM Reg-4 +`define PINMUX_CFG_PWM5 8'h54 // reg_21 - PWM Reg-5 +`define PINMUX_SOFT_REG_1 8'h58 // reg_22 - Sof Register +`define PINMUX_SOFT_REG_2 8'h5C // reg_23 - Sof Register +`define PINMUX_SOFT_REG_3 8'h60 // reg_24 - Sof Register +`define PINMUX_SOFT_REG_4 8'h64 // reg_25 - Sof Register +`define PINMUX_SOFT_REG_5 8'h68 // reg_26 - Sof Register +`define PINMUX_SOFT_REG_6 8'h6C // reg_27 - Sof Register +`define PINMUX_CFG_TIMER0 8'h70 // reg_28 - Timer-0 +`define PINMUX_CFG_TIMER1 8'h74 // reg_28 - Timer-1 +`define PINMUX_CFG_TIMER2 8'h78 // reg_28 - Timer-2 + +//---------------------------------------------------------- +// QSPI Register Map +//---------------------------------------------------------- +`define QSPIM_GLBL_CTRL 8'h00 +`define QSPIM_DMEM_G0_RD_CTRL 8'h04 +`define QSPIM_DMEM_G0_WR_CTRL 8'h08 +`define QSPIM_DMEM_G1_RD_CTRL 8'h0C +`define QSPIM_DMEM_G1_WR_CTRL 8'h10 + +`define QSPIM_DMEM_CS_AMAP 8'h14 +`define QSPIM_DMEM_CA_AMASK 8'h18 + +`define QSPIM_IMEM_CTRL1 8'h1C +`define QSPIM_IMEM_CTRL2 8'h20 +`define QSPIM_IMEM_ADDR 8'h24 +`define QSPIM_IMEM_WDATA 8'h28 +`define QSPIM_IMEM_RDATA 8'h2C +`define QSPIM_SPI_STATUS 8'h30 +
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv index eef549a..c0aab56 100644 --- a/verilog/rtl/wb_host/src/wb_host.sv +++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -41,6 +41,16 @@ //// u_cpuclk,u_rtcclk,u_usbclk //// //// 0.3 - Nov 16 2021, Dinesh A //// //// Wishbone out are register for better timing //// +//// 0.4 - Mar 15 2021, Dinesh A //// +//// 1. To fix the bug in caravel mgmt soc address range //// +//// reduction to 0x3000_0000 to 0x300F_FFFF //// +//// Address Map has changes as follows //// +//// 0x3008_0000 to 0x3008_00FF - Local Wishbone Reg //// +//// 0x3000_0000 to 0x3007_FFFF - SOC access with //// +//// indirect Map {Bank_Sel[15:3], wbm_adr_i[18:0]} //// +//// 2.wbm_cyc_i need to qualified with wbm_stb_i //// +//// //// +//// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -146,7 +156,7 @@ logic sw_wr_en_1; logic sw_wr_en_2; logic sw_wr_en_3; -logic [7:0] cfg_bank_sel; +logic [15:0] cfg_bank_sel; logic [31:0] reg_0; // Software_Reg_0 logic [3:0] cfg_wb_clk_ctrl; @@ -245,13 +255,13 @@ wb_arb u_arb( .clk (wbm_clk_i), .rstn (wbm_rst_n), - .req ({1'b0,wbm_uart_stb_i,wbm_stb_i}), + .req ({1'b0,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}), .gnt (grnt) ); // Select the master based on the grant -assign wb_cyc_i = (grnt == 2'b00) ? wbm_cyc_i : wbm_uart_cyc_i; -assign wb_stb_i = (grnt == 2'b00) ? wbm_stb_i : wbm_uart_stb_i; +assign wb_cyc_i = (grnt == 2'b00) ? wbm_cyc_i : wbm_uart_cyc_i; +assign wb_stb_i = (grnt == 2'b00) ? (wbm_cyc_i & wbm_stb_i) : wbm_uart_stb_i; assign wb_adr_i = (grnt == 2'b00) ? wbm_adr_i : wbm_uart_adr_i; assign wb_we_i = (grnt == 2'b00) ? wbm_we_i : wbm_uart_we_i; assign wb_dat_i = (grnt == 2'b00) ? wbm_dat_i : wbm_uart_dat_i; @@ -312,19 +322,19 @@ //----------------------------------------------------------------------- -// Local register decide based on address[31] == 1 +// Local register decide based on address[19] == 1 // // Locally there register are define to control the reset and clock for user // area //----------------------------------------------------------------------- -// caravel user space is 0x3000_0000 to 0x30FF_FFFF +// caravel user space is 0x3000_0000 to 0x3007_FFFF // So we have allocated -// 0x3080_0000 - 0x3080_00FF - Assigned to WB Host Address Space +// 0x3008_0000 - 0x3008_00FF - Assigned to WB Host Address Space // Since We need more than 16MB Address space to access SDRAM/SPI we have // added indirect MSB 8 bit address select option -// So Address will be {Bank_Sel[7:0], wbm_adr_i[23:0} +// So Address will be {Bank_Sel[15:3], wbm_adr_i[18:0]} // --------------------------------------------------------------------- -assign reg_sel = wb_req & (wb_adr_i[23] == 1'b1); +assign reg_sel = wb_req & (wb_adr_i[19] == 1'b1); assign sw_addr = wb_adr_i [3:2]; assign sw_rd_en = reg_sel & !wb_we_i; @@ -372,7 +382,7 @@ case (sw_addr [1:0]) 2'b00 : reg_out [31:0] = reg_0; - 2'b01 : reg_out [31:0] = {24'h0,cfg_bank_sel [7:0]}; + 2'b01 : reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]}; 2'b10 : reg_out [31:0] = cfg_clk_ctrl1 [31:0]; 2'b11 : reg_out [31:0] = cfg_clk_ctrl2 [31:0]; default : reg_out [31:0] = 'h0; @@ -391,14 +401,14 @@ .data_out (reg_0[31:0]) ); -generic_register #(8,8'h10 ) u_bank_sel ( - .we ({8{sw_wr_en_1}} ), - .data_in (wb_dat_i[7:0] ), +generic_register #(16,16'h1000 ) u_bank_sel ( + .we ({16{sw_wr_en_1}} ), + .data_in (wb_dat_i[15:0] ), .reset_n (wbm_rst_n ), .clk (wbm_clk_i ), //List of Outs - .data_out (cfg_bank_sel[7:0] ) + .data_out (cfg_bank_sel[15:0] ) ); @@ -427,7 +437,7 @@ // Since design need more than 16MB address space, we have implemented // indirect access -assign wb_adr_int = {cfg_bank_sel[7:0],wb_adr_i[23:0]}; +assign wb_adr_int = {cfg_bank_sel[15:3],wb_adr_i[18:0]}; async_wb u_async_wb( // Master Port
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c index 2bab521..fe0b434 160000 --- a/verilog/rtl/yifive/ycr1c +++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@ -Subproject commit 2bab521595455a42acee88f7e0fd3747f1806581 +Subproject commit fe0b434aae2822a90d062dc10682a9926c26e2c7