tcm memory access bug fix and riscv regression update
diff --git a/README.md b/README.md
index 28a6d02..7271967 100644
--- a/README.md
+++ b/README.md
@@ -533,6 +533,7 @@
make verify-user_risc_boot
make verify-wb_port SIM=RTL DUMP=OFF
make verify-wb_port SIM=RTL DUMP=ON
+ make verify-riscv_regress
```
# Tool Sets
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index 86fc231..7241d94 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h16m7s,-1,46012.12121212122,0.2475,23006.06060606061,27.04,716.55,5694,0,0,0,0,0,0,-1,1,0,-1,-1,421256,61213,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,310056895.0,4.48,43.44,33.22,9.4,0.43,-1,3565,8555,538,5527,0,0,0,4197,0,0,0,0,0,0,0,4,1341,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h17m10s,-1,46012.12121212122,0.2475,23006.06060606061,27.04,701.62,5694,0,0,0,0,0,0,-1,1,0,-1,-1,421176,61049,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,309535459.0,5.55,42.43,32.83,10.82,0.75,-1,3565,8555,538,5527,0,0,0,4197,0,0,0,0,0,0,0,4,1341,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index d573af1..04c97bd 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h35m5s,-1,53092.1052631579,0.7904,26546.05263157895,30.7,1184.14,20982,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1620249,234724,-2.04,-17.66,-1,-0.03,-1,-2476.75,-21882.2,-1,-0.03,-1,1288559929.0,1.19,62.41,23.31,23.29,0.0,-1,18371,29934,1071,12527,0,0,0,21750,0,0,0,0,0,0,0,4,5144,5851,49,366,10822,0,11188,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.32,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h41m48s,-1,53830.971659919036,0.7904,26915.485829959518,30.93,1195.5,21274,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1674760,240681,-2.04,-17.8,-1,0.0,-1,-2459.49,-21655.63,-1,0.0,-1,1322263875.0,0.0,62.03,24.69,26.16,0.01,-1,18597,30067,1067,12430,0,0,0,21980,0,0,0,0,0,0,0,4,5240,5924,49,366,10822,0,11188,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.32,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 22fcfa7..a6e08b8 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h40m44s,-1,2.529576587795766,10.2784,1.264788293897883,-1,530.43,13,0,0,0,0,0,0,-1,0,0,-1,-1,1176232,8172,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.36,3.16,3.63,0.42,0.66,-1,271,2532,271,2532,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h41m51s,-1,2.529576587795766,10.2784,1.264788293897883,-1,531.06,13,0,0,0,0,0,0,-1,0,0,-1,-1,1176475,8150,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.36,3.16,3.67,0.41,0.59,-1,271,2532,271,2532,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/verilog/dv/agents/uart_agent.v b/verilog/dv/agents/uart_agent.v
index 2ed5686..72121e9 100644
--- a/verilog/dv/agents/uart_agent.v
+++ b/verilog/dv/agents/uart_agent.v
@@ -63,10 +63,10 @@
always @(posedge mclk)
begin
if (clk_count == 'h0) begin
- uart_clk <= ~uart_clk;
- clk_count <= control_setup.divisor;
+ uart_clk = ~uart_clk;
+ clk_count = control_setup.divisor;
end else begin
- clk_count <= clk_count - 1;
+ clk_count = clk_count - 1;
end
end
assign uart_rx_clk = uart_clk;
@@ -124,6 +124,7 @@
stop_err2_cnt = 0;
timeout_err_cnt = 0;
err_cnt = 0;
+ clk_count = 0;
end
endtask
@@ -202,9 +203,6 @@
end
end
-
-// wait another half cycle for tx_done signal
- @(negedge uart_rx_clk);
read <= 0;
-> uart_read_done;
@@ -299,8 +297,6 @@
end
end
-// wait another half cycle for tx_done signal
- @(negedge uart_rx_clk);
read <= 0;
-> uart_read_done;
@@ -397,9 +393,6 @@
end
end
-
-// wait another half cycle for tx_done signal
- @(negedge uart_rx_clk);
read <= 0;
-> uart_read_done;
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 38144e8..4332e90 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -134,6 +134,7 @@
$dumpvars(1,risc_boot_tb.u_spi_flash_256mb);
//$dumpvars(2,risc_boot_tb.uut);
$dumpvars(4,risc_boot_tb.uut.mprj);
+ $dumpvars(0,risc_boot_tb.tb_uart);
//$dumpvars(0,risc_boot_tb.u_user_spiflash);
$display("Waveform Dump started");
end
@@ -152,52 +153,65 @@
uart_fifo_enable = 0; // fifo mode disable
#200; // Wait for reset removal
-
- // Wait for Managment core to boot up
- wait(checkbits == 16'h AB60);
- $display("Monitor: Test User Risc Boot Started");
-
- // Wait for user risc core to boot up
- repeat (25000) @(posedge clock);
- tb_uart.uart_init;
- tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
- uart_stick_parity, uart_timeout, uart_divisor);
-
- for (i=0; i<40; i=i+1)
- uart_write_data[i] = $random;
-
-
-
+
fork
- begin
- for (i=0; i<40; i=i+1)
+ begin
+
+ // Wait for Managment core to boot up
+ wait(checkbits == 16'h AB60);
+ $display("Monitor: Test User Risc Boot Started");
+
+ // Wait for user risc core to boot up
+ repeat (25000) @(posedge clock);
+ tb_uart.uart_init;
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+
+ for (i=0; i<40; i=i+1)
+ uart_write_data[i] = $random;
+
+
+
+ fork
begin
- $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
- tb_uart.write_char (uart_write_data[i]);
+ for (i=0; i<40; i=i+1)
+ begin
+ $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
+ tb_uart.write_char (uart_write_data[i]);
+ end
end
- end
-
- begin
- for (j=0; j<40; j=j+1)
+
begin
- tb_uart.read_char_chk(uart_write_data[j]);
+ for (j=0; j<40; j=j+1)
+ begin
+ tb_uart.read_char_chk(uart_write_data[j]);
+ end
end
+ join
+
+ #100
+ tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+
+ test_fail = 0;
+
+ // Check
+ // if all the 40 byte transmitted
+ // if all the 40 byte received
+ // if no error
+ if(uart_tx_nu != 40) test_fail = 1;
+ if(uart_rx_nu != 40) test_fail = 1;
+ if(tb_uart.err_cnt != 0) test_fail = 1;
+
+ end
+ begin
+ // Loop for TimeOut
+ repeat (60000) @(posedge clock);
+ // $display("+1000 cycles");
+ test_fail = 1;
end
- join
-
- #100
- tb_uart.report_status(uart_rx_nu, uart_tx_nu);
-
- test_fail = 0;
-
- // Check
- // if all the 40 byte transmitted
- // if all the 40 byte received
- // if no error
- if(uart_tx_nu != 40) test_fail = 1;
- if(uart_rx_nu != 40) test_fail = 1;
- if(tb_uart.err_cnt != 0) test_fail = 1;
-
+ join_any
+ disable fork; //disable pending fork activity
+
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index 1958002..645b9cd 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -137,6 +137,7 @@
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
sv_list = ../../user_risc_regress_tb.v
top_module = user_risc_regress_tb
@@ -157,7 +158,8 @@
export RISCV_GCC ?= $(CROSS_PREFIX)gcc
export RISCV_OBJDUMP ?= $(CROSS_PREFIX)objdump -D
export RISCV_ROM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -j .text.init -j .text -j .rodata -j .rodata.str1.4 -O verilog
-export RISCV_RAM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -R .text.init -R .text -R .rodata -R .rodata.str1.4 -O verilog
+#Seperate the RAM content and write out in 32bit Little endian format to load it to TCM Memory
+export RISCV_RAM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -R .text.init -R .text -R .rodata -R .rodata.str1.4 -R .riscv.attributes -O verilog --verilog-data-width=4 --reverse-bytes=4
export RISCV_READELF ?= $(CROSS_PREFIX)readelf -s
ifneq (,$(findstring e,$(ARCH_lowercase)))
@@ -172,27 +174,27 @@
ifeq (,$(findstring e,$(ARCH_lowercase)))
# These tests cannot be compiled for RVE
# Comment this target if you don't want to run the riscv_isa
- #TARGETS += riscv_isa
+ TARGETS += riscv_isa
# Comment this target if you don't want to run the riscv_compliance
- #TARGETS += riscv_compliance
+ TARGETS += riscv_compliance
endif
# Comment this target if you don't want to run the isr_sample
#TARGETS += isr_sample
# Comment this target if you don't want to run the coremark
-TARGETS += coremark
+#TARGETS += coremark
# Comment this target if you don't want to run the dhrystone
#TARGETS += dhrystone21
# Comment this target if you don't want to run the hello test
-#TARGETS += hello
+TARGETS += hello
# Targets
-.PHONY: tests run_iverilog run_modelsim run_modelsim_wlf run_vcs run_ncsim run_verilator run_verilator_wf
+.PHONY: tests run_iverilog run_modelsim run_modelsim_wlf run_vcs run_ncsim run_verilator run_verilator_wf run_iverilog_wf
default: clean_test_list run_iverilog
@@ -270,7 +272,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_TESTS_PATH) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) -I $(UPRJ_TESTS_PATH) \
$(sv_list) \
-o $(top_module).vvp; \
printf "" > $(test_results); \
@@ -290,7 +292,7 @@
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_BEHAVIOURAL_AGENTS) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
- -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_TESTS_PATH) \
+ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) -I $(UPRJ_TESTS_PATH) \
$(sv_list) \
-o $(top_module).vvp; \
printf "" > $(test_results); \
diff --git a/verilog/dv/riscv_regress/riscv_runtests.sv b/verilog/dv/riscv_regress/riscv_runtests.sv
index 8f12e4e..bfbb3bb 100644
--- a/verilog/dv/riscv_regress/riscv_runtests.sv
+++ b/verilog/dv/riscv_regress/riscv_runtests.sv
@@ -55,8 +55,8 @@
**/
/**
logic [31:0] test_count;
- `define RISC_CORE i_top.i_core_top
- `define RISC_EXU i_top.i_core_top.i_pipe_top.i_pipe_exu
+ `define RISC_CORE u_top.u_riscv_top.i_core_top
+ `define RISC_EXU u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu
initial begin
test_count = 0;
@@ -70,7 +70,6 @@
end
end
**/
-
always_ff @(posedge clk) begin
bit test_pass;
int unsigned f_test;
@@ -140,10 +139,10 @@
`endif
fd = $fopen(tmpstr, "w");
while ((start != stop)) begin
- test_data[31:24] = u_sdram8.Bank0[(start & 32'h1FFF)+3];
- test_data[23:16] = u_sdram8.Bank0[(start & 32'h1FFF)+2];
- test_data[15:8] = u_sdram8.Bank0[(start & 32'h1FFF)+1];
- test_data[7:0] = u_sdram8.Bank0[(start & 32'h1FFF)+0];
+ test_data[31:24] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+3];
+ test_data[23:16] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+2];
+ test_data[15:8] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+1];
+ test_data[7:0] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+0];
$fwrite(fd, "%x", test_data);
$fwrite(fd, "%s", "\n");
start += 4;
@@ -167,10 +166,10 @@
// Assumed all signaure are with-in first 512 location of memory,
// other-wise need to switch bank
// --------------------------------------------------
- test_data[31:24] = u_sdram8.Bank0[(start & 32'h1FFF)+3];
- test_data[23:16] = u_sdram8.Bank0[(start & 32'h1FFF)+2];
- test_data[15:8] = u_sdram8.Bank0[(start & 32'h1FFF)+1];
- test_data[7:0] = u_sdram8.Bank0[(start & 32'h1FFF)+0];
+ test_data[31:24] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+3];
+ test_data[23:16] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+2];
+ test_data[15:8] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+1];
+ test_data[7:0] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+0];
//$display("Compare Addr: %x ref_data : %x, test_data: %x",start,ref_data,test_data);
test_pass &= (ref_data == test_data);
if(ref_data != test_data)
@@ -186,8 +185,11 @@
$write("\033[0;31mTest failed-2\033[0m\n");
end
`endif // SIGNATURE_OUT
- end else begin
+ end else begin // Non compliance mode
test_running <= 1'b0;
+ if(u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10] != 0)
+ $display("ERROR: mprf_int[10]: %x not zero",u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10]);
+
test_pass = (u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10] == 0);
tests_total += 1;
tests_passed += test_pass;
diff --git a/verilog/dv/riscv_regress/run_iverilog b/verilog/dv/riscv_regress/run_iverilog
new file mode 100755
index 0000000..7e1401b
--- /dev/null
+++ b/verilog/dv/riscv_regress/run_iverilog
@@ -0,0 +1,26 @@
+cd /home/dinesha/workarea/opencore/git/riscduino/verilog/rtl/syntacore/scr1/sim/tests/hello
+
+riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I/home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/syntacore/scr1/sim/tests/common /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c -o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/sc_print.o
+
+riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I/home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/syntacore/scr1/sim/tests/common hello.c -o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/hello.o
+
+riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I/home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/syntacore/scr1/sim/tests/common /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/crt_tcm.o
+
+riscv64-unknown-elf-gcc -o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/hello.elf -T /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/sc_print.o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/hello.o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32
+rm /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/sc_print.o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/crt_tcm.o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/hello.o
+
+cd /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0
+iverilog -g2005-sv -DFUNCTIONAL -DWFDUMP -DSIM -I /opt/pdk/sky130A \
+-I /home/dinesha/workarea/efabless/MPW-4/caravel/verilog/dv/caravel -I /home/dinesha/workarea/efabless/MPW-4/caravel/verilog/rtl \
+-I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../model -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog \
+-I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../agents \
+-I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/syntacore/scr1/src/includes -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/sdram_ctrl/src/defs -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/i2cm/src/includes \
+-I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/usb1_host/src/includes -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/mbist/include -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress \
+../../user_risc_regress_tb.v \
+-o user_risc_regress_tb.vvp
+
+iverilog-vpi ../../../vpi/system/system.c
+vvp -M. -msystem user_risc_regress_tb.vvp \
++test_info=/home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/test_info \
++test_results=/home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/test_results.txt \
+| tee /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/sim_results.txt
diff --git a/verilog/dv/riscv_regress/uprj_netlists.v b/verilog/dv/riscv_regress/uprj_netlists.v
deleted file mode 100644
index e53865f..0000000
--- a/verilog/dv/riscv_regress/uprj_netlists.v
+++ /dev/null
@@ -1,138 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-// Include caravel global defines for the number of the user project IO pads
-`include "defines.v"
- `define USE_POWER_PINS
- `define UNIT_DELAY #0.1
-
-`ifdef GL
- `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
- `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
- `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
- `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
- `include "libs.ref//sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
-
- `include "glbl_cfg.v"
- `include "sdram.v"
- `include "spi_master.v"
- `include "uart_i2cm_usb.v"
- `include "wb_interconnect.v"
- `include "user_project_wrapper.v"
- `include "syntacore.v"
- `include "wb_host.v"
- `include "clk_skew_adjust.v"
-
-`else
- `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
- `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
- `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
- `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-
-
- `include "spi_master/src/spim_top.sv"
- `include "spi_master/src/spim_if.sv"
- `include "spi_master/src/spim_fifo.sv"
- `include "spi_master/src/spim_regs.sv"
- `include "spi_master/src/spim_clkgen.sv"
- `include "spi_master/src/spim_ctrl.sv"
- `include "spi_master/src/spim_rx.sv"
- `include "spi_master/src/spim_tx.sv"
-
- `include "uart/src/uart_core.sv"
- `include "uart/src/uart_cfg.sv"
- `include "uart/src/uart_rxfsm.sv"
- `include "uart/src/uart_txfsm.sv"
- `include "lib/async_fifo_th.sv"
- `include "lib/reset_sync.sv"
- `include "lib/double_sync_low.v"
- `include "lib/clk_buf.v"
-
- `include "i2cm/src/core/i2cm_bit_ctrl.v"
- `include "i2cm/src/core/i2cm_byte_ctrl.v"
- `include "i2cm/src/core/i2cm_top.v"
-
- `include "usb1_host/src/core/usbh_core.sv"
- `include "usb1_host/src/core/usbh_crc16.sv"
- `include "usb1_host/src/core/usbh_crc5.sv"
- `include "usb1_host/src/core/usbh_fifo.sv"
- `include "usb1_host/src/core/usbh_sie.sv"
- `include "usb1_host/src/phy/usb_fs_phy.v"
- `include "usb1_host/src/phy/usb_transceiver.v"
- `include "usb1_host/src/top/usb1_host.sv"
-
- `include "uart_i2c_usb/src/uart_i2c_usb.sv"
-
- `include "sdram_ctrl/src/top/sdrc_top.v"
- `include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v"
- `include "lib/async_fifo.sv"
- `include "sdram_ctrl/src/core/sdrc_core.v"
- `include "sdram_ctrl/src/core/sdrc_bank_ctl.v"
- `include "sdram_ctrl/src/core/sdrc_bank_fsm.v"
- `include "sdram_ctrl/src/core/sdrc_bs_convert.v"
- `include "sdram_ctrl/src/core/sdrc_req_gen.v"
- `include "sdram_ctrl/src/core/sdrc_xfr_ctl.v"
-
- `include "lib/registers.v"
- `include "lib/clk_ctl.v"
- `include "digital_core/src/glbl_cfg.sv"
-
- `include "wb_host/src/wb_host.sv"
- `include "lib/async_wb.sv"
-
- `include "lib/wb_stagging.sv"
- `include "wb_interconnect/src/wb_arb.sv"
- `include "wb_interconnect/src/wb_interconnect.sv"
-
-
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv"
- `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
- `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
- `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
- `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
- `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
- `include "syntacore/scr1/src/core/scr1_tapc.sv"
- `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
- `include "syntacore/scr1/src/core/scr1_core_top.sv"
- `include "syntacore/scr1/src/core/scr1_dm.sv"
- `include "syntacore/scr1/src/core/scr1_dmi.sv"
- `include "syntacore/scr1/src/core/scr1_scu.sv"
-
- `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
- `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
- `include "syntacore/scr1/src/top/scr1_tcm.sv"
- `include "syntacore/scr1/src/top/scr1_timer.sv"
- `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
- `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
- `include "syntacore/scr1/src/top/scr1_intf.sv"
- `include "syntacore/scr1/src/top/scr1_top_wb.sv"
- `include "lib/sync_fifo.sv"
-
- `include "user_project_wrapper.v"
- // we are using netlist file for clk_skew_adjust as it has
- // standard cell + power pin
- `include "gl/clk_skew_adjust.v"
-`endif
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index 4dd6abf..894ffb3 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -178,9 +178,8 @@
initial begin
$dumpfile("simx.vcd");
$dumpvars(1, user_risc_regress_tb);
- $dumpvars(0, user_risc_regress_tb.u_top.u_sdram_ctrl);
- $dumpvars(0, user_risc_regress_tb.u_sdram8);
- //$dumpvars(1, user_risc_regress_tb.u_top.u_riscv_top);
+ $dumpvars(1, user_risc_regress_tb.u_top);
+ $dumpvars(0, user_risc_regress_tb.u_top.u_riscv_top);
end
`endif
@@ -192,10 +191,18 @@
// Wait for reset removal
wait (rst_n == 1);
+
// Initialize the SPI memory with hex content
$write("\033[0;34m---Initializing the SPI Memory with Hexfile: %s\033[0m\n", test_file);
$readmemh(test_file,u_spi_flash_256mb.Mem);
+ // some of the RISCV test need SRAM area for specific
+ // instruction execution like fence
+ $sformat(test_ram_file, "%s.ram",test_file);
+ $write("\033[0;34m---Initializing the u_tsram0_2kb Memory with Hexfile: %s\033[0m\n", test_ram_file);
+ $readmemh(test_ram_file,u_top.u_tsram0_2kb.mem);
+ //for(i =32'h00; i < 32'h100; i = i+1)
+ // $display("Location: %x, Data: %x", i, u_top.u_tsram0_2kb.mem[i]);
#200;
@@ -207,7 +214,7 @@
repeat (2) @(posedge clock);
#1;
//------------ fuse_mhartid= 0x00
- wb_user_core_write('h3000_0004,'h0);
+ wb_user_core_write('h3002_0004,'h0);
repeat (2) @(posedge clock);
@@ -252,7 +259,7 @@
// Logic Analyzer Signals
- .la_data_in ('0) ,
+ .la_data_in ('1) ,
.la_data_out (),
.la_oenb ('0),
@@ -284,149 +291,6 @@
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
- force u_top.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio0.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio0.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio0.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio1.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio1.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio1.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio2.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio2.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio2.VNB =VSS;
-
- force u_top.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay1_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay1_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_delay2_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_delay2_sdio3.VNB = VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VPWR =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VPB =USER_VDD1V8;
- force u_top.u_qspi_master.u_buf_sdio3.VGND =VSS;
- force u_top.u_qspi_master.u_buf_sdio3.VNB =VSS;
-
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB =USER_VDD1V8;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
- force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_qspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_qspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_sspim_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_sspim_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
- force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
- force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-
-
- force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
- force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
- force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
- force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
-
- force u_top.u_wb_host.u_delay1_stb0.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay1_stb0.VGND =VSS;
- force u_top.u_wb_host.u_delay1_stb0.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb1.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb1.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb1.VNB = VSS;
-
- force u_top.u_wb_host.u_delay2_stb2.VPWR =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VPB =USER_VDD1V8;
- force u_top.u_wb_host.u_delay2_stb2.VGND =VSS;
- force u_top.u_wb_host.u_delay2_stb2.VNB = VSS;
end
`endif
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index 549a5e5..d84401d 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -61,7 +61,7 @@
%.vvp: %_tb.v
${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o
${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o
- ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(SYNTACORE_FIRMWARE_PATH)/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
${GCC64_PREFIX}-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex
${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
rm crt_tcm.o user_risc_boot.o
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index b568991..e3b9044 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -668,7 +668,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h0101_2022) u_reg_23 (
+gen_32b_reg #(32'h0601_2022) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -681,9 +681,9 @@
);
//-----------------------------------------
-// Software Reg-3: Poject Revison 2.4 = 0002400
+// Software Reg-3: Poject Revison 2.5 = 0002500
// ----------------------------------------
-gen_32b_reg #(32'h0002_3000) u_reg_24 (
+gen_32b_reg #(32'h0002_5000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk b/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk
index 2d35442..6075f73 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk
@@ -58,8 +58,8 @@
$(bld_dir)/%.hex: $(bld_dir)/%.elf
$(RISCV_ROM_OBJCOPY) $^ $@
$(RISCV_RAM_OBJCOPY) $^ $@.ram
- #assign 0x2000_0xxx to 0x0000_0xxx to map to sdram
- sed -i 's/@20000/@00000/g' $@.ram
+ #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory
+ sed -i 's/@00480/@00000/g' $@.ram
$(bld_dir)/%.dump: $(bld_dir)/%.elf
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld
index 31653f1..6df6659 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld
@@ -28,7 +28,7 @@
MEMORY {
ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x00480000, LENGTH = 4K
}
STACK_SIZE = 1024;
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
index c49465e..3840ec3 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
@@ -27,7 +27,7 @@
MEMORY {
ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K
- TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 2K
+ TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 4K
}
STACK_SIZE = 256;
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile b/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile
index d2b210b..0558434 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile
+++ b/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile
@@ -134,8 +134,8 @@
$(dst_dir)/compliance_%.hex: $(dst_dir)/compliance_%.elf
$(RISCV_ROM_OBJCOPY) $^ $@
$(RISCV_RAM_OBJCOPY) $^ $@.ram
- #assign 0x2000_0xxx to 0x0000_0xxx to map to sdram
- sed -i 's/@20000/@00000/g' $@.ram
+ #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory
+ sed -i 's/@00480/@00000/g' $@.ram
$(bld_dir)/compliance_%.dump: $(dst_dir)/compliance_%.elf
$(RISCV_OBJDUMP) -D -w -x -S $^ > $@
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile b/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile
index 945519c..b953642 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile
+++ b/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile
@@ -44,8 +44,8 @@
$(bld_dir)/%.hex: $(bld_dir)/%.elf
$(RISCV_ROM_OBJCOPY) $^ $@
$(RISCV_RAM_OBJCOPY) $^ $@.ram
- #assign 0x2000_0xxx to 0x0000_0xxx to map to sdram
- sed -i 's/@20000/@00000/g' $@.ram
+ #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory
+ sed -i 's/@00480/@00000/g' $@.ram
$(bld_dir)/%.dump: $(bld_dir)/%.elf
$(RISCV_OBJDUMP) $^ > $@
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
index 2524fd3..db8174e 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
@@ -138,7 +138,7 @@
// SRAM-0 Port 0 Control Generation
assign sram0_clk0 = clk;
-assign sram0_csb0 = !(dmem_req & (imem_addr[11] == 1'b0) & ((dmem_cmd == SCR1_MEM_CMD_RD) | (dmem_cmd == SCR1_MEM_CMD_WR)));
+assign sram0_csb0 = !(dmem_req & (dmem_addr[11] == 1'b0) & ((dmem_cmd == SCR1_MEM_CMD_RD) | (dmem_cmd == SCR1_MEM_CMD_WR)));
assign sram0_web0 = !(dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR));
assign sram0_addr0 = dmem_addr[10:2];
assign sram0_wmask0 = dmem_byteen;
@@ -146,7 +146,7 @@
// SRAM-1 Port 0 Control Generation
assign sram1_clk0 = clk;
-assign sram1_csb0 = !(dmem_req & (imem_addr[11] == 1'b1) & ((dmem_cmd == SCR1_MEM_CMD_RD) | (dmem_cmd == SCR1_MEM_CMD_WR)));
+assign sram1_csb0 = !(dmem_req & (dmem_addr[11] == 1'b1) & ((dmem_cmd == SCR1_MEM_CMD_RD) | (dmem_cmd == SCR1_MEM_CMD_WR)));
assign sram1_web0 = !(dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR));
assign sram1_addr0 = dmem_addr[10:2];
assign sram1_wmask0 = dmem_byteen;
@@ -203,12 +203,8 @@
//-------------------------------------------------------------------------------
// Data memory output generation
//-------------------------------------------------------------------------------
-always_ff @(posedge clk) begin
- if (dmem_rd) begin
- dmem_rdata_shift_reg <= dmem_addr[1:0];
- end
-end
+assign dmem_rdata_shift_reg = dmem_addr[1:0];
assign dmem_rdata = dmem_rdata_local >> ( 8 * dmem_rdata_shift_reg );
endmodule : scr1_tcm
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 8ef66fd..2f5d2c1 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -143,6 +143,8 @@
//// UART Master added with message handler at wb_host ////
//// 2.4 Jan 01, 2022, Dinesh A ////
//// LA[0] is added as soft reset option at wb_port ////
+//// 2.5 Jan 06, 2022, Dinesh A ////
+//// TCM RAM Bug fix inside syntacore ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
