bus repeater added
diff --git a/env/spef-mapping.tcl b/env/spef-mapping.tcl
index a5f39fd..671b62a 100644
--- a/env/spef-mapping.tcl
+++ b/env/spef-mapping.tcl
@@ -8,6 +8,9 @@
set spef_mapping(mprj/\u_riscv_top.i_core_top_0) "$::env(PROJECT_ROOT)/signoff/ycr_core_top/openlane-signoff/spef/ycr_core_top.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/\u_riscv_top.u_connect) "$::env(PROJECT_ROOT)/signoff/ycr_iconnect/openlane-signoff/spef/ycr_iconnect.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/\u_riscv_top.u_intf) "$::env(PROJECT_ROOT)/signoff/ycr_intf/openlane-signoff/spef/ycr_intf.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_rp_east) "$::env(PROJECT_ROOT)/signoff/bus_rep_east/openlane-signoff/spef/bus_rep_east.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_rp_north) "$::env(PROJECT_ROOT)/signoff/bus_rep_north/openlane-signoff/spef/bus_rep_north.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_rp_south) "$::env(PROJECT_ROOT)/signoff/bus_rep_south/openlane-signoff/spef/bus_rep_south.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_rp_west) "$::env(PROJECT_ROOT)/signoff/bus_rep_west/openlane-signoff/spef/bus_rep_west.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_uart_i2c_usb_spi) "$::env(PROJECT_ROOT)/signoff/uart_i2c_usb_spi_top/openlane-signoff/spef/uart_i2c_usb_spi_top.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_wb_host) "$::env(PROJECT_ROOT)/signoff/wb_host/openlane-signoff/spef/wb_host.$::env(RCX_CORNER).spef"
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 9afeacf..8722c96 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index f318870..103eb8b 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/openlane/bus_rep_south/config.tcl b/openlane/bus_rep_south/config.tcl
index bcfd99c..eec763c 100755
--- a/openlane/bus_rep_south/config.tcl
+++ b/openlane/bus_rep_south/config.tcl
@@ -49,7 +49,7 @@
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=124 "
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=253 "
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
@@ -65,9 +65,10 @@
# -------------
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2030 50"
+set ::env(DIE_AREA) "0 0 2650 50"
#set ::env(GRT_OBS) "met4 0 0 300 1725"
@@ -81,6 +82,7 @@
set ::env(PL_TIME_DRIVEN) 1
set ::env(PL_TARGET_DENSITY) "0.20"
set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) 0.2
# helps in anteena fix
set ::env(USE_ARC_ANTENNA_CHECK) "0"
@@ -96,7 +98,7 @@
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0"
## Routing
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
@@ -116,6 +118,11 @@
set ::env(MAGIC_GENERATE_LEF) {1}
set ::env(MAGIC_WRITE_FULL_LEF) {0}
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "600"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
set ::env(ECO_ENABLE) {0}
#set ::env(CURRENT_STEP) "synthesis"
diff --git a/openlane/bus_rep_south/interactive.tcl b/openlane/bus_rep_south/interactive.tcl
index a96ddb6..5b5c6c8 100755
--- a/openlane/bus_rep_south/interactive.tcl
+++ b/openlane/bus_rep_south/interactive.tcl
@@ -13,7 +13,6 @@
# See the License for the specific language governing permissions and
# limitations under the License.
package require openlane; # provides the utils as well
-
proc run_placement_step {args} {
if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
@@ -33,6 +32,9 @@
run_cts
run_resizer_timing
+ if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+ remove_buffers_from_nets
+ }
}
proc run_routing_step {args} {
@@ -118,6 +120,12 @@
}
}
+proc run_erc_step {args} {
+ if { $::env(RUN_CVC) } {
+ run_erc
+ }
+}
+
proc run_eco_step {args} {
if { $::env(ECO_ENABLE) == 1 } {
run_eco_flow
@@ -142,88 +150,71 @@
proc run_post_run_hooks {} {
if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
puts_info "Running post run hook"
- set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
puts_info "$result"
} else {
puts_info "hooks/post_run.py not found, skipping"
}
}
-proc run_magic_drc_batch {args} {
- set options {
- {-magicrc optional}
- {-tech optional}
- {-report required}
- {-design required}
- {-gds required}
- }
- set flags {}
- parse_key_args "run_magic_drc_batch" args arg_values $options flags_mag $flags
- if { [info exists arg_values(-magicrc)] } {
- set magicrc [file normalize $arg_values(-magicrc)]
- }
- if { [info exists arg_values(-tech)] } {
- set ::env(TECH) [file normalize $arg_values(-tech)]
- }
- set ::env(GDS_INPUT) [file normalize $arg_values(-gds)]
- set ::env(REPORT_OUTPUT) [file normalize $arg_values(-report)]
- set ::env(DESIGN_NAME) $arg_values(-design)
+proc run_floorplan {args} {
+ # |----------------------------------------------------|
+ # |---------------- 2. FLOORPLAN ------------------|
+ # |----------------------------------------------------|
+ #
+ # intial fp
+ init_floorplan
- if { [info exists magicrc] } {
- exec magic \
- -noconsole \
- -dnull \
- -rcfile $magicrc \
- $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
- </dev/null |& tee /dev/tty
+ # check for deprecated io variables
+ if { [info exists ::env(FP_IO_HMETAL)]} {
+ set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+ puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+ }
+
+ if { [info exists ::env(FP_IO_VMETAL)]} {
+ set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+ puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+ }
+
+
+ # place io
+ if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+ place_io_ol
} else {
- exec magic \
- -noconsole \
- -dnull \
- $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
- </dev/null |& tee /dev/tty
- }
-}
-
-proc run_lvs_batch {args} {
- # runs device level lvs on -gds/CURRENT_GDS and -net/CURRENT_NETLIST
- # extracts gds only if EXT_NETLIST does not exist
- set options {
- {-design required}
- {-gds optional}
- {-net optional}
- }
- set flags {}
- parse_key_args "run_lvs_batch" args arg_values $options flags_lvs $flags -no_consume
-
- prep {*}$args
-
- if { [info exists arg_values(-gds)] } {
- set ::env(CURRENT_GDS) [file normalize $arg_values(-gds)]
- } else {
- set ::env(CURRENT_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).gds
- }
- if { [info exists arg_values(-net)] } {
- set ::env(CURRENT_NETLIST) [file normalize $arg_values(-net)]
+ if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+ place_io
+ global_placement_or
+ place_contextualized_io \
+ -lef $::env(FP_CONTEXT_LEF) \
+ -def $::env(FP_CONTEXT_DEF)
+ } else {
+ place_io
+ }
}
- assert_files_exist "$::env(CURRENT_GDS) $::env(CURRENT_NETLIST)"
+ apply_def_template
- set ::env(MAGIC_EXT_USE_GDS) 1
- set ::env(EXT_NETLIST) $::env(signoff_results)/$::env(DESIGN_NAME).gds.spice
- if { [file exists $::env(EXT_NETLIST)] } {
- puts_warn "The file $::env(EXT_NETLIST) will be used. If you would like the file re-exported, please delete it."
- } else {
- run_magic_spice_export
+ #if { [info exist ::env(EXTRA_LEFS)] } {
+ if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+ file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+ manual_macro_placement -f
+ } else {
+ # global_placement_or
+ # basic_macro_placement
+ }
+ #}
+
+ if { $::env(RUN_TAP_DECAP_INSERTION) } {
+ tap_decap_or
}
- run_lvs
-}
+ scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
-
-proc run_file {args} {
- set ::env(TCLLIBPATH) $::auto_path
- exec tclsh {*}$args >&@stdout
+ run_power_grid_generation
}
@@ -281,18 +272,9 @@
} else {
set ::env(CURRENT_STEP) "synthesis"
}
- #Dinesh-A: Addition for LAST_STEP
- if { [info exists arg_values(-to) ]} {
- puts_info "Last flow Will be at $arg_values(-to)..."
- set ::env(LAST_STEP) $arg_values(-to)
- } elseif { [info exists ::env(LAST_STEP) ] } {
- puts_info "Last flow Will be at $::env(LAST_STEP)..."
- } else {
- set ::env(LAST_STEP) "cvc"
- }
set_if_unset arg_values(-from) $::env(CURRENT_STEP)
- set_if_unset arg_values(-to) $::env(LAST_STEP)
+ set_if_unset arg_values(-to) "cvc"
set exe 0;
dict for {step_name step_exe} $steps {
diff --git a/openlane/bus_rep_south/pin_order.cfg b/openlane/bus_rep_south/pin_order.cfg
index 74cee02..4546535 100644
--- a/openlane/bus_rep_south/pin_order.cfg
+++ b/openlane/bus_rep_south/pin_order.cfg
@@ -3,256 +3,526 @@
#MANUAL_PLACE
#N
-ch_out\[105\] 1730 0 2
-ch_out\[104\]
-ch_in\[103\]
-ch_out\[102\]
-ch_out\[101\]
-ch_out\[100\]
-ch_out\[99\]
-ch_out\[98\]
-ch_in\[97\]
-ch_out\[96\]
-ch_out\[95\]
-ch_out\[94\]
-ch_in\[93\]
-ch_out\[92\]
-ch_out\[91\]
-ch_out\[90\]
-ch_in\[89\]
-ch_out\[88\]
-ch_out\[87\]
-ch_out\[86\]
-ch_in\[85\]
-ch_out\[84\]
-ch_out\[83\]
-ch_out\[82\]
-ch_in\[81\]
-ch_out\[80\]
-ch_out\[79\]
-ch_in\[78\]
-ch_out\[77\]
-ch_out\[76\]
-ch_in\[75\]
-ch_out\[74\]
-ch_out\[73\]
-ch_in\[72\]
-ch_out\[71\]
-ch_out\[70\]
-ch_in\[69\]
-ch_out\[68\]
-ch_out\[67\]
-ch_in\[66\]
-ch_out\[65\]
-ch_out\[64\]
-ch_in\[63\]
-ch_out\[62\]
-ch_out\[61\]
-ch_in\[60\]
-ch_out\[59\]
-ch_out\[58\]
-ch_in\[57\]
-ch_out\[56\]
-ch_out\[55\]
-ch_in\[54\]
-ch_out\[53\]
-ch_out\[52\]
-ch_in\[51\]
-ch_out\[50\]
-ch_out\[49\]
-ch_in\[48\]
-ch_out\[47\]
-ch_out\[46\]
-ch_in\[45\]
-ch_out\[44\]
-ch_out\[43\]
-ch_in\[42\]
-ch_out\[41\]
-ch_out\[40\]
-ch_in\[39\]
-ch_out\[38\]
-ch_out\[37\]
-ch_in\[36\]
-ch_out\[35\]
-ch_out\[34\]
-ch_in\[33\]
-ch_out\[32\]
-ch_out\[31\]
-ch_in\[30\]
-ch_out\[29\]
-ch_out\[28\]
-ch_in\[27\]
-ch_out\[26\]
-ch_out\[25\]
-ch_in\[24\]
-ch_out\[23\]
-ch_out\[22\]
-ch_in\[21\]
-ch_out\[20\]
-ch_out\[19\]
-ch_in\[18\]
-ch_out\[17\]
-ch_out\[16\]
-ch_in\[15\]
-ch_out\[14\]
-ch_out\[13\]
-ch_in\[12\]
-ch_out\[11\]
-ch_out\[10\]
-ch_in\[9\]
-ch_out\[8\]
-ch_out\[7\]
-ch_in\[6\]
-ch_out\[5\]
-ch_out\[4\]
-ch_in\[3\]
-ch_out\[2\]
+ch_out\[0\] 1000 0 8
ch_out\[1\]
-ch_in\[0\]
+ch_in\[2\]
+ch_out\[3\]
+ch_out\[4\]
+ch_out\[5\]
+ch_out\[6\]
+ch_out\[7\]
+ch_in\[8\]
+ch_out\[9\]
+ch_out\[10\]
+ch_out\[11\]
+ch_in\[12\]
+ch_out\[13\]
+ch_out\[14\]
+ch_out\[15\]
+ch_in\[16\]
+ch_out\[17\]
+ch_out\[18\]
+ch_out\[19\]
+ch_in\[20\]
+ch_out\[21\]
+ch_out\[22\]
+ch_out\[23\]
+ch_in\[24\]
-ch_out\[123\] 1980 0 2
-ch_out\[122\]
-ch_out\[121\]
-ch_out\[120\]
-ch_out\[119\]
-ch_out\[118\]
-ch_out\[117\]
-ch_out\[116\]
-ch_out\[115\]
-ch_out\[114\]
-ch_out\[113\]
-ch_out\[112\]
-ch_out\[111\]
-ch_out\[110\]
-ch_out\[109\]
-ch_out\[108\]
-ch_out\[107\]
-ch_out\[106\]
+ch_out\[25\]
+ch_out\[26\]
+ch_in\[27\]
+ch_out\[28\]
+ch_out\[29\]
+ch_in\[30\]
+ch_out\[31\]
+ch_out\[32\]
+ch_in\[33\]
+ch_out\[34\]
+ch_out\[35\]
+ch_in\[36\]
+ch_out\[37\]
+ch_out\[38\]
+ch_in\[39\]
+ch_out\[40\]
+ch_out\[41\]
+ch_in\[42\]
+ch_out\[43\]
+ch_out\[44\]
+ch_in\[45\]
+ch_out\[46\]
+ch_out\[47\]
+ch_in\[48\]
+ch_out\[49\]
+ch_out\[50\]
+ch_in\[51\]
+ch_out\[52\]
+ch_out\[53\]
+ch_in\[54\]
+ch_out\[55\]
+ch_out\[56\]
+ch_in\[57\]
+ch_out\[58\]
+ch_out\[59\]
+ch_in\[60\]
+ch_out\[61\]
+ch_out\[62\]
+ch_in\[63\]
+ch_out\[64\]
+ch_out\[65\]
+ch_in\[66\]
+ch_out\[67\]
+ch_out\[68\]
+ch_in\[69\]
+ch_out\[70\]
+ch_out\[71\]
+ch_in\[72\]
+ch_out\[73\]
+ch_out\[74\]
+ch_in\[75\]
+ch_out\[76\]
+ch_out\[77\]
+ch_in\[78\]
+ch_out\[79\]
+ch_out\[80\]
+ch_in\[81\]
+ch_out\[82\]
+ch_out\[83\]
+ch_in\[84\]
+ch_out\[85\]
+ch_out\[86\]
+ch_in\[87\]
+ch_out\[88\]
+ch_out\[89\]
+ch_in\[90\]
+ch_out\[91\]
+ch_out\[92\]
+ch_in\[93\]
+ch_out\[94\]
+ch_out\[95\]
+ch_in\[96\]
+ch_out\[97\]
+ch_out\[98\]
+ch_in\[99\]
+ch_out\[100\]
+ch_out\[101\]
+ch_in\[102\]
+ch_out\[103\]
+ch_out\[104\]
+ch_in\[105\]
+
+
+
+
+ch_out\[106\] 1800 0 8
+ch_in\[107\]
+ch_out\[108\]
+ch_in\[109\]
+ch_out\[110\]
+ch_in\[111\]
+ch_out\[112\]
+ch_in\[113\]
+ch_out\[114\]
+ch_in\[115\]
+ch_out\[116\]
+ch_in\[117\]
+ch_out\[118\]
+ch_in\[119\]
+ch_out\[120\]
+ch_in\[121\]
+ch_out\[122\]
+ch_in\[123\]
+ch_out\[124\]
+ch_in\[125\]
+ch_out\[126\]
+ch_in\[127\]
+ch_out\[128\]
+ch_in\[129\]
+ch_out\[130\]
+ch_in\[131\]
+ch_out\[132\]
+ch_in\[133\]
+ch_out\[134\]
+ch_in\[135\]
+ch_out\[136\]
+ch_in\[137\]
+ch_out\[138\]
+ch_in\[139\]
+ch_out\[140\]
+ch_in\[141\]
+ch_in\[142\]
+ch_in\[143\]
+ch_in\[144\]
+ch_in\[145\]
+ch_in\[146\]
+ch_in\[147\]
+ch_in\[148\]
+ch_in\[149\]
+ch_in\[150\]
+ch_in\[151\]
+ch_in\[152\]
+ch_in\[153\]
+ch_in\[154\]
+ch_in\[155\]
+ch_in\[156\]
+ch_in\[157\]
+ch_in\[158\]
+ch_in\[159\]
+ch_in\[160\]
+ch_in\[161\]
+ch_in\[162\]
+ch_in\[163\]
+ch_in\[164\]
+ch_in\[165\]
+ch_in\[166\]
+ch_in\[167\]
+ch_in\[168\]
+ch_in\[169\]
+ch_in\[170\]
+ch_in\[171\]
+ch_in\[172\]
+ch_in\[173\]
+ch_in\[174\]
+ch_in\[175\]
+ch_in\[176\]
+ch_in\[177\]
+ch_in\[178\]
+ch_in\[179\]
+ch_in\[180\]
+ch_in\[181\]
+ch_in\[182\]
+ch_in\[183\]
+ch_in\[184\]
+ch_in\[185\]
+ch_in\[186\]
+ch_in\[187\]
+
+ch_in\[188\] 2200 0 4
+ch_in\[189\]
+ch_in\[190\]
+ch_in\[191\]
+ch_in\[192\]
+ch_in\[193\]
+ch_in\[194\]
+ch_in\[195\]
+ch_in\[196\]
+ch_in\[197\]
+ch_in\[198\]
+ch_in\[199\]
+ch_in\[200\]
+ch_in\[201\]
+ch_in\[202\]
+ch_in\[203\]
+ch_in\[204\]
+ch_in\[205\]
+ch_in\[206\]
+ch_in\[207\]
+ch_in\[208\]
+ch_in\[209\]
+ch_in\[210\]
+ch_in\[211\]
+ch_in\[212\]
+ch_in\[213\]
+ch_in\[214\]
+ch_in\[215\]
+ch_in\[216\]
+ch_in\[217\]
+ch_in\[218\]
+ch_in\[219\]
+
+ch_in\[220\] 2400 0 4
+ch_in\[221\]
+ch_in\[222\]
+ch_in\[223\]
+ch_in\[224\]
+ch_in\[225\]
+ch_in\[226\]
+ch_in\[227\]
+ch_in\[228\]
+ch_in\[229\]
+ch_in\[230\]
+ch_in\[231\]
+ch_in\[232\]
+ch_in\[233\]
+ch_in\[234\]
+ch_in\[235\]
+ch_in\[236\]
+ch_in\[237\]
+ch_in\[238\]
+ch_in\[239\]
+ch_in\[240\]
+ch_in\[241\]
+ch_in\[242\]
+ch_in\[243\]
+ch_in\[244\]
+ch_in\[245\]
+ch_in\[246\]
+ch_in\[247\]
+ch_in\[248\]
+ch_in\[249\]
+ch_in\[250\]
+ch_in\[251\]
+ch_out\[252\]
#S
-ch_in\[105\] 0 0 16
-ch_in\[104\]
-ch_out\[103\]
-ch_in\[102\]
-ch_in\[101\]
-ch_in\[100\]
-ch_in\[99\]
-ch_in\[98\]
-ch_out\[97\]
-ch_in\[96\]
-ch_in\[95\]
-ch_in\[94\]
-ch_out\[93\]
-ch_in\[92\]
-ch_in\[91\]
-ch_in\[90\]
-ch_out\[89\]
-ch_in\[88\]
-ch_in\[87\]
-ch_in\[86\]
-ch_out\[85\]
-ch_in\[84\]
-ch_in\[83\]
-ch_in\[82\]
-ch_out\[81\]
-ch_in\[80\]
-ch_in\[79\]
-ch_out\[78\]
-ch_in\[77\]
-ch_in\[76\]
-ch_out\[75\]
-ch_in\[74\]
-ch_in\[73\]
-ch_out\[72\]
-ch_in\[71\]
-ch_in\[70\]
-ch_out\[69\]
-ch_in\[68\]
-ch_in\[67\]
-ch_out\[66\]
-ch_in\[65\]
-ch_in\[64\]
-ch_out\[63\]
-ch_in\[62\]
-ch_in\[61\]
-ch_out\[60\]
-ch_in\[59\]
-ch_in\[58\]
-ch_out\[57\]
-ch_in\[56\]
-ch_in\[55\]
-ch_out\[54\]
-ch_in\[53\]
-ch_in\[52\]
-ch_out\[51\]
-ch_in\[50\]
-ch_in\[49\]
-ch_out\[48\]
-ch_in\[47\]
-ch_in\[46\]
-ch_out\[45\]
-ch_in\[44\]
-ch_in\[43\]
-ch_out\[42\]
-ch_in\[41\]
-ch_in\[40\]
-ch_out\[39\]
-ch_in\[38\]
-ch_in\[37\]
-ch_out\[36\]
-ch_in\[35\]
-ch_in\[34\]
-ch_out\[33\]
-ch_in\[32\]
-ch_in\[31\]
-ch_out\[30\]
-ch_in\[29\]
-ch_in\[28\]
-ch_out\[27\]
-ch_in\[26\]
-ch_in\[25\]
-ch_out\[24\]
-ch_in\[23\]
-ch_in\[22\]
-ch_out\[21\]
-ch_in\[20\]
-ch_in\[19\]
-ch_out\[18\]
-ch_in\[17\]
-ch_in\[16\]
-ch_out\[15\]
-ch_in\[14\]
-ch_in\[13\]
-ch_out\[12\]
-ch_in\[11\]
+ch_in\[0\] 0 0 16
+ch_in\[1\]
+ch_out\[2\]
+ch_in\[3\]
+ch_in\[4\]
+ch_in\[5\]
+ch_in\[6\]
+ch_in\[7\]
+ch_out\[8\]
+ch_in\[9\]
ch_in\[10\]
-ch_out\[9\]
-ch_in\[8\]
-ch_in\[7\]
-ch_out\[6\]
-ch_in\[5\]
-ch_in\[4\]
-ch_out\[3\]
-ch_in\[2\]
-ch_in\[1\]
-ch_out\[0\]
+ch_in\[11\]
+ch_out\[12\]
+ch_in\[13\]
+ch_in\[14\]
+ch_in\[15\]
+ch_out\[16\]
+ch_in\[17\]
+ch_in\[18\]
+ch_in\[19\]
+ch_out\[20\]
+ch_in\[21\]
+ch_in\[22\]
+ch_in\[23\]
+ch_out\[24\]
+ch_in\[25\]
+ch_in\[26\]
+ch_out\[27\]
+ch_in\[28\]
+ch_in\[29\]
+ch_out\[30\]
+ch_in\[31\]
+ch_in\[32\]
+ch_out\[33\]
+ch_in\[34\]
+ch_in\[35\]
+ch_out\[36\]
+ch_in\[37\]
+ch_in\[38\]
+ch_out\[39\]
+ch_in\[40\]
+ch_in\[41\]
+ch_out\[42\]
+ch_in\[43\]
+ch_in\[44\]
+ch_out\[45\]
+ch_in\[46\]
+ch_in\[47\]
+ch_out\[48\]
+ch_in\[49\]
+ch_in\[50\]
+ch_out\[51\]
+ch_in\[52\]
+ch_in\[53\]
+ch_out\[54\]
+ch_in\[55\]
+ch_in\[56\]
+ch_out\[57\]
+ch_in\[58\]
+ch_in\[59\]
+ch_out\[60\]
+ch_in\[61\]
+ch_in\[62\]
+ch_out\[63\]
+ch_in\[64\]
+ch_in\[65\]
+ch_out\[66\]
+ch_in\[67\]
+ch_in\[68\]
+ch_out\[69\]
+ch_in\[70\]
+ch_in\[71\]
+ch_out\[72\]
+ch_in\[73\]
+ch_in\[74\]
+ch_out\[75\]
+ch_in\[76\]
+ch_in\[77\]
+ch_out\[78\]
+ch_in\[79\]
+ch_in\[80\]
+ch_out\[81\]
+ch_in\[82\]
+ch_in\[83\]
+ch_out\[84\]
+ch_in\[85\]
+ch_in\[86\]
+ch_out\[87\]
+ch_in\[88\]
+ch_in\[89\]
+ch_out\[90\]
+ch_in\[91\]
+ch_in\[92\]
+ch_out\[93\]
+ch_in\[94\]
+ch_in\[95\]
+ch_out\[96\]
+ch_in\[97\]
+ch_in\[98\]
+ch_out\[99\]
+ch_in\[100\]
+ch_in\[101\]
+ch_out\[102\]
+ch_in\[103\]
+ch_in\[104\]
+ch_out\[105\]
-ch_in\[123\] 700 0 16
-ch_in\[122\]
-ch_in\[121\]
-ch_in\[120\]
-ch_in\[119\]
-ch_in\[118\]
-ch_in\[117\]
-ch_in\[116\]
-ch_in\[115\]
-ch_in\[114\]
-ch_in\[113\]
-ch_in\[112\]
-ch_in\[111\]
-ch_in\[110\]
-ch_in\[109\]
+
+ch_in\[106\] 600 0 32
+ch_out\[107\]
ch_in\[108\]
-ch_in\[107\]
-ch_in\[106\]
+ch_out\[109\]
+ch_in\[110\]
+ch_out\[111\]
+ch_in\[112\]
+ch_out\[113\]
+ch_in\[114\]
+ch_out\[115\]
+ch_in\[116\]
+ch_out\[117\]
+ch_in\[118\]
+ch_out\[119\]
+ch_in\[120\]
+ch_out\[121\]
+ch_in\[122\]
+ch_out\[123\]
+ch_in\[124\]
+ch_out\[125\]
+
+ch_in\[126\] 810 0 32
+ch_out\[127\]
+ch_in\[128\]
+ch_out\[129\]
+ch_in\[130\]
+ch_out\[131\]
+ch_in\[132\]
+ch_out\[133\]
+ch_in\[134\]
+ch_out\[135\]
+ch_in\[136\]
+ch_out\[137\]
+ch_in\[138\]
+ch_out\[139\]
+ch_in\[140\]
+ch_out\[141\]
+
+
+ch_out\[142\] 1100 0 32
+ch_out\[143\]
+ch_out\[144\]
+ch_out\[145\]
+ch_out\[146\]
+ch_out\[147\]
+ch_out\[148\]
+ch_out\[149\]
+ch_out\[150\]
+ch_out\[151\]
+ch_out\[152\]
+ch_out\[153\]
+ch_out\[154\]
+ch_out\[155\]
+ch_out\[156\]
+ch_out\[157\]
+ch_out\[158\]
+ch_out\[159\]
+ch_out\[160\]
+ch_out\[161\]
+ch_out\[162\]
+ch_out\[163\]
+ch_out\[164\]
+ch_out\[165\]
+ch_out\[166\]
+ch_out\[167\]
+ch_out\[168\]
+ch_out\[169\]
+ch_out\[170\]
+ch_out\[171\]
+ch_out\[172\]
+ch_out\[173\]
+ch_out\[174\]
+ch_out\[175\]
+ch_out\[176\]
+ch_out\[177\]
+ch_out\[178\]
+ch_out\[179\]
+ch_out\[180\]
+ch_out\[181\]
+ch_out\[182\]
+ch_out\[183\]
+ch_out\[184\]
+ch_out\[185\]
+ch_out\[186\]
+ch_out\[187\]
+
+ch_out\[188\] 1800 0 32
+ch_out\[189\]
+ch_out\[190\]
+ch_out\[191\]
+ch_out\[192\]
+ch_out\[193\]
+ch_out\[194\]
+ch_out\[195\]
+ch_out\[196\]
+ch_out\[197\]
+ch_out\[198\]
+ch_out\[199\]
+ch_out\[200\]
+ch_out\[201\]
+ch_out\[202\]
+ch_out\[203\]
+ch_out\[204\]
+ch_out\[205\]
+ch_out\[206\]
+ch_out\[207\]
+ch_out\[208\]
+ch_out\[209\]
+ch_out\[210\]
+ch_out\[211\]
+ch_out\[212\]
+ch_out\[213\]
+ch_out\[214\]
+ch_out\[215\]
+ch_out\[216\]
+ch_out\[217\]
+ch_out\[218\]
+ch_out\[219\]
+ch_out\[220\]
+ch_out\[221\]
+ch_out\[222\]
+ch_out\[223\]
+ch_out\[224\]
+ch_out\[225\]
+ch_out\[226\]
+ch_out\[227\]
+ch_out\[228\]
+ch_out\[229\]
+ch_out\[230\]
+ch_out\[231\]
+ch_out\[232\]
+ch_out\[233\]
+ch_out\[234\]
+ch_out\[235\]
+ch_out\[236\]
+ch_out\[237\]
+ch_out\[238\]
+ch_out\[239\]
+ch_out\[240\]
+ch_out\[241\]
+ch_out\[242\]
+ch_out\[243\]
+ch_out\[244\]
+ch_out\[245\]
+ch_out\[246\]
+ch_out\[247\]
+ch_out\[248\]
+ch_out\[249\]
+ch_out\[250\]
+ch_out\[251\]
+ch_in\[252\]
+
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 3900d26..b52bc4e 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -30,6 +30,7 @@
set ::env(CLOCK_PORT) "mclk"
set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
## CTS BUFFER
set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index a8e15ef..fff23e7 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -425,23 +425,6 @@
digital_io_out\[24\]
digital_io_in\[24\]
-sflash_oen\[0\] 350 0 2
-sflash_oen\[1\]
-sflash_oen\[2\]
-sflash_oen\[3\]
-sflash_ss\[0\]
-sflash_ss\[1\]
-sflash_ss\[2\]
-sflash_ss\[3\]
-sflash_sck
-sflash_do\[0\]
-sflash_do\[1\]
-sflash_do\[2\]
-sflash_do\[3\]
-sflash_di\[0\]
-sflash_di\[1\]
-sflash_di\[2\]
-sflash_di\[3\]
digital_io_in\[23\] 400 0
digital_io_out\[23\]
@@ -473,6 +456,23 @@
#E
+sflash_oen\[0\]
+sflash_oen\[1\]
+sflash_oen\[2\]
+sflash_oen\[3\]
+sflash_ss\[0\]
+sflash_ss\[1\]
+sflash_ss\[2\]
+sflash_ss\[3\]
+sflash_sck
+sflash_do\[0\]
+sflash_do\[1\]
+sflash_do\[2\]
+sflash_do\[3\]
+sflash_di\[0\]
+sflash_di\[1\]
+sflash_di\[2\]
+sflash_di\[3\]
digital_io_in\[0\] 0200 0 4
digital_io_out\[0\]
diff --git a/openlane/qspim_top/pin_order.cfg b/openlane/qspim_top/pin_order.cfg
index c078759..8c81d46 100644
--- a/openlane/qspim_top/pin_order.cfg
+++ b/openlane/qspim_top/pin_order.cfg
@@ -2,40 +2,8 @@
#MANUAL_PLACE
#E
-spi_debug\[0\] 0000 0 2
-spi_debug\[1\]
-spi_debug\[2\]
-spi_debug\[3\]
-spi_debug\[4\]
-spi_debug\[5\]
-spi_debug\[6\]
-spi_debug\[7\]
-spi_debug\[8\]
-spi_debug\[9\]
-spi_debug\[10\]
-spi_debug\[11\]
-spi_debug\[12\]
-spi_debug\[13\]
-spi_debug\[14\]
-spi_debug\[15\]
-spi_debug\[16\]
-spi_debug\[17\]
-spi_debug\[18\]
-spi_debug\[19\]
-spi_debug\[20\]
-spi_debug\[21\]
-spi_debug\[22\]
-spi_debug\[23\]
-spi_debug\[24\]
-spi_debug\[25\]
-spi_debug\[26\]
-spi_debug\[27\]
-spi_debug\[28\]
-spi_debug\[29\]
-spi_debug\[30\]
-spi_debug\[31\]
-spi_sdi\[3\] 0200 0 2
+spi_sdi\[3\] 0500 0 2
spi_sdi\[2\]
spi_sdi\[1\]
spi_sdi\[0\]
@@ -192,3 +160,36 @@
strap_pre_sram
strap_flash\[1\]
strap_flash\[0\]
+
+spi_debug\[0\] 0200 0 2
+spi_debug\[1\]
+spi_debug\[2\]
+spi_debug\[3\]
+spi_debug\[4\]
+spi_debug\[5\]
+spi_debug\[6\]
+spi_debug\[7\]
+spi_debug\[8\]
+spi_debug\[9\]
+spi_debug\[10\]
+spi_debug\[11\]
+spi_debug\[12\]
+spi_debug\[13\]
+spi_debug\[14\]
+spi_debug\[15\]
+spi_debug\[16\]
+spi_debug\[17\]
+spi_debug\[18\]
+spi_debug\[19\]
+spi_debug\[20\]
+spi_debug\[21\]
+spi_debug\[22\]
+spi_debug\[23\]
+spi_debug\[24\]
+spi_debug\[25\]
+spi_debug\[26\]
+spi_debug\[27\]
+spi_debug\[28\]
+spi_debug\[29\]
+spi_debug\[30\]
+spi_debug\[31\]
diff --git a/openlane/uart_i2c_usb_spi_top/pin_order.cfg b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
index 2801070..b518404 100644
--- a/openlane/uart_i2c_usb_spi_top/pin_order.cfg
+++ b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
@@ -101,7 +101,7 @@
usb_rstn
-#E
+#N
scl_pad_i
scl_pad_o
scl_pad_oen_o
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 25eab79..dd20a7b 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -79,6 +79,9 @@
$::env(DESIGN_DIR)/../../verilog/gl/aes_top.v \
$::env(DESIGN_DIR)/../../verilog/gl/fpu_wrapper.v \
$::env(DESIGN_DIR)/../../verilog/gl/bus_rep_south.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_north.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_east.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_west.v \
"
set ::env(EXTRA_LEFS) "\
@@ -96,6 +99,9 @@
$lef_root/aes_top.lef \
$lef_root/fpu_wrapper.lef \
$lef_root/bus_rep_south.lef \
+ $lef_root/bus_rep_north.lef \
+ $lef_root/bus_rep_east.lef \
+ $lef_root/bus_rep_west.lef \
"
set ::env(EXTRA_GDS_FILES) "\
@@ -113,6 +119,9 @@
$gds_root/aes_top.gds \
$gds_root/fpu_wrapper.gds \
$gds_root/bus_rep_south.gds \
+ $gds_root/bus_rep_north.gds \
+ $gds_root/bus_rep_east.gds \
+ $gds_root/bus_rep_west.gds \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -124,10 +133,6 @@
## Internal Macros
### Macro PDN Connections
-### Follow checks are temp masked due to PDNGEN issue in
-### handling SRAM Power Strip in MET3, This issue occured due
-### Enabling MET3 to MET4 connectivity to handle power hook up
-### for bus repeater macro
set ::env(FP_PDN_CHECK_NODES) 1
set ::env(FP_PDN_IRDROP) "1"
set ::env(RUN_IRDROP_REPORT) "1"
@@ -143,8 +148,8 @@
set ::env(FP_PDN_VPITCH) "80"
set ::env(FP_PDN_HOFFSET) "5"
set ::env(FP_PDN_HPITCH) "80"
-set ::env(FP_PDN_HWIDTH) {6.2}
-set ::env(FP_PDN_VWIDTH) {6.2}
+set ::env(FP_PDN_HWIDTH) {5.2}
+set ::env(FP_PDN_VWIDTH) {5.2}
set ::env(FP_PDN_HSPACING) {13.8}
set ::env(FP_PDN_VSPACING) {13.8}
@@ -171,6 +176,7 @@
met1 150 750 833.1 1166.54,\
met2 150 750 833.1 1166.54,\
met3 150 750 833.1 1166.54,\
+ met3 50 100 100 3350,\
met5 0 0 2920 3520"
#set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 1, vdda2 vssa2 1"
@@ -191,7 +197,10 @@
u_4x8bit_dac vdda1 vssa1 vccd1 vssd1,\
u_aes vccd1 vssd1 vccd1 vssd1,\
u_fpu vccd1 vssd1 vccd1 vssd1,\
- u_rp_south vccd1 vssd1 vccd1 vssd1
+ u_rp_south vccd1 vssd1 vccd1 vssd1,\
+ u_rp_north vccd1 vssd1 vccd1 vssd1,\
+ u_rp_east vccd1 vssd1 vccd1 vssd1,\
+ u_rp_west vccd1 vssd1 vccd1 vssd1
"
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 1f6639d..c464041 100755
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -258,7 +258,7 @@
set steps [dict create \
"synthesis" "run_synthesis" \
"floorplan" "run_floorplan" \
- "placement" "run_placement_step" \
+ "placement" "run_placement_step"\
"cts" "run_cts_step" \
"routing" "run_routing_step" \
"parasitics_sta" "run_parasitics_sta_step" \
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 9169bcd..c1e83c0 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -4,9 +4,9 @@
u_pinmux 2250 2000 N
u_pll 2500 3028 N
-u_fpu 1000 2600 N
-u_aes 50 2600 N
-u_riscv_top.i_core_top_0 50 1400 N
+u_fpu 1100 2600 N
+u_aes 150 2600 N
+u_riscv_top.i_core_top_0 150 1400 N
u_riscv_top.u_connect 740 1400 N
u_riscv_top.u_intf 950 650 N
u_dcache_2kb 150 130 N
@@ -16,4 +16,7 @@
u_intercon 1850 650 N
u_wb_host 1750 100 N
-u_rp_south 20 20 N
+u_rp_south 100 20 N
+u_rp_north 100 3400 N
+u_rp_east 2820 50 E
+u_rp_west 50 100 E
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index ace04ab..8d53f9c 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -167,15 +167,29 @@
-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
##################################
-# u_rp_south Power Hook Up
+# u_rp_North & u_rp_south Power Hook Up
# Power connect met-3 to met-4
##################################
define_pdn_grid \
-macro \
-name macro_2 \
- -instances "u_rp_south" \
+ -instances "u_rp_south u_rp_north" \
-starts_with POWER \
-halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
add_pdn_connect -grid macro_2 -layers "met3 met4"
+
+##################################
+# u_rp_east Power Hook Up
+# Power connect met-3 to met-5
+##################################
+
+define_pdn_grid \
+ -macro \
+ -name macro_3 \
+ -instances "u_rp_east u_rp_west" \
+ -starts_with POWER \
+ -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+
+add_pdn_connect -grid macro_3 -layers "met3 met5"
diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc
index cc73165..2542338 100644
--- a/openlane/ycr_intf/base.sdc
+++ b/openlane/ycr_intf/base.sdc
@@ -2,6 +2,7 @@
# Timing Constraints
###############################################################################
create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
+create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock0} [get_ports dcache_mem_clk0]
@@ -20,6 +21,7 @@
set_clock_groups -name async_clock -asynchronous \
-group [get_clocks {core_clk dcache_mem_clk0 dcache_mem_clk1 icache_mem_clk0 icache_mem_clk1}]\
+ -group [get_clocks {rtc_clk}]\
-group [get_clocks {wb_clk}] -comment {Async Clock group}
# Set case analysis
diff --git a/sdc/bus_rep_south.sdc b/sdc/bus_rep_south.sdc
index 4b6e7be..76a6861 100644
--- a/sdc/bus_rep_south.sdc
+++ b/sdc/bus_rep_south.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Thu Nov 24 03:05:17 2022
+# Sat Dec 3 12:30:12 2022
###############################################################################
current_design bus_rep_south
###############################################################################
@@ -35,20 +35,149 @@
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[121]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[122]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[123]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[124]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[125]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[126]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[127]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[128]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[129]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[130]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[131]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[132]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[133]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[134]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[135]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[136]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[137]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[138]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[139]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[140]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[141]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[142]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[143]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[144]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[145]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[146]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[147]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[148]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[149]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[150]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[151]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[152]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[153]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[154]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[155]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[156]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[157]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[158]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[159]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[160]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[161]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[162]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[163]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[164]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[165]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[166]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[167]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[168]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[169]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[170]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[171]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[172]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[173]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[174]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[175]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[176]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[177]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[178]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[179]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[180]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[181]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[182]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[183]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[184]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[185]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[186]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[187]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[188]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[189]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[190]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[191]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[192]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[193]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[194]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[195]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[196]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[197]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[198]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[199]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[200]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[201]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[202]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[203]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[204]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[205]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[206]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[207]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[208]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[209]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[210]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[211]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[212]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[213]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[214]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[215]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[216]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[217]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[218]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[219]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[220]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[221]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[222]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[223]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[224]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[225]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[226]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[227]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[228]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[229]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[230]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[231]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[232]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[233]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[234]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[235]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[236]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[237]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[238]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[239]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[240]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[241]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[242]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[243]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[244]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[245]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[246]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[247]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[248]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[249]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[250]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[251]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[252]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[27]}]
@@ -159,20 +288,149 @@
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[121]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[122]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[123]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[124]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[125]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[126]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[127]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[128]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[129]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[130]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[131]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[132]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[133]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[134]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[135]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[136]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[137]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[138]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[139]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[140]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[141]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[142]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[143]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[144]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[145]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[146]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[147]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[148]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[149]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[150]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[151]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[152]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[153]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[154]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[155]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[156]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[157]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[158]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[159]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[160]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[161]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[162]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[163]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[164]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[165]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[166]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[167]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[168]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[169]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[170]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[171]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[172]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[173]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[174]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[175]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[176]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[177]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[178]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[179]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[180]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[181]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[182]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[183]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[184]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[185]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[186]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[187]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[188]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[189]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[190]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[191]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[192]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[193]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[194]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[195]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[196]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[197]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[198]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[199]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[200]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[201]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[202]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[203]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[204]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[205]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[206]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[207]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[208]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[209]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[210]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[211]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[212]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[213]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[214]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[215]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[216]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[217]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[218]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[219]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[220]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[221]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[222]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[223]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[224]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[225]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[226]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[227]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[228]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[229]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[230]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[231]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[232]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[233]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[234]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[235]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[236]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[237]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[238]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[239]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[240]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[241]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[242]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[243]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[244]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[245]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[246]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[247]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[248]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[249]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[250]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[251]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[252]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[27]}]
@@ -259,6 +517,135 @@
###############################################################################
# Environment
###############################################################################
+set_load -pin_load 0.0334 [get_ports {ch_out[252]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[251]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[250]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[249]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[248]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[247]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[246]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[245]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[244]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[243]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[242]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[241]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[240]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[239]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[238]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[237]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[236]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[235]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[234]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[233]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[232]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[231]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[230]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[229]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[228]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[227]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[226]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[225]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[224]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[223]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[222]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[221]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[220]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[219]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[218]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[217]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[216]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[215]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[214]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[213]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[212]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[211]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[210]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[209]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[208]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[207]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[206]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[205]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[204]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[203]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[202]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[201]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[200]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[199]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[198]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[197]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[196]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[195]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[194]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[193]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[192]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[191]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[190]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[189]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[188]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[187]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[186]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[185]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[184]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[183]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[182]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[181]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[180]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[179]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[178]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[177]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[176]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[175]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[174]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[173]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[172]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[171]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[170]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[169]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[168]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[167]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[166]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[165]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[164]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[163]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[162]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[161]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[160]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[159]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[158]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[157]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[156]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[155]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[154]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[153]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[152]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[151]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[150]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[149]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[148]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[147]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[146]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[145]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[144]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[143]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[142]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[141]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[140]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[139]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[138]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[137]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[136]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[135]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[134]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[133]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[132]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[131]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[130]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[129]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[128]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[127]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[126]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[125]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[124]}]
set_load -pin_load 0.0334 [get_ports {ch_out[123]}]
set_load -pin_load 0.0334 [get_ports {ch_out[122]}]
set_load -pin_load 0.0334 [get_ports {ch_out[121]}]
@@ -383,6 +770,135 @@
set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[252]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[251]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[250]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[249]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[248]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[247]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[246]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[245]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[244]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[243]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[242]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[241]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[240]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[239]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[238]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[237]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[236]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[235]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[234]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[233]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[232]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[231]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[230]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[229]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[228]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[227]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[226]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[225]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[224]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[223]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[222]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[221]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[220]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[219]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[218]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[217]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[216]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[215]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[214]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[213]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[212]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[211]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[210]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[209]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[208]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[207]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[206]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[205]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[204]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[203]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[202]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[201]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[200]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[199]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[198]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[197]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[196]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[195]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[194]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[193]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[192]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[191]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[190]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[189]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[188]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[187]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[186]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[185]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[184]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[183]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[182]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[181]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[180]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[179]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[178]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[177]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[176]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[175]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[174]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[173]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[172]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[171]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[170]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[169]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[168]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[167]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[166]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[165]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[164]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[163]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[162]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[161]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[160]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[159]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[158]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[157]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[156]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[155]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[154]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[153]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[152]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[151]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[150]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[149]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[148]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[147]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[146]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[145]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[144]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[143]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[142]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[141]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[140]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[139]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[138]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[137]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[136]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[135]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[134]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[133]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[132]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[131]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[130]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[129]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[128]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[124]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[123]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[122]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[121]}]
diff --git a/sdc/pinmux_top.sdc b/sdc/pinmux_top.sdc
index f5391f4..1e3d2e0 100644
--- a/sdc/pinmux_top.sdc
+++ b/sdc/pinmux_top.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sat Nov 26 13:16:41 2022
+# Sun Dec 4 03:05:47 2022
###############################################################################
current_design pinmux_top
###############################################################################
diff --git a/sdc/qspim_top.sdc b/sdc/qspim_top.sdc
index 8bab75d..e7836ed 100644
--- a/sdc/qspim_top.sdc
+++ b/sdc/qspim_top.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sat Nov 26 13:14:11 2022
+# Thu Dec 1 11:16:57 2022
###############################################################################
current_design qspim_top
###############################################################################
diff --git a/sdc/uart_i2c_usb_spi_top.sdc b/sdc/uart_i2c_usb_spi_top.sdc
index 10e9be3..e2ff4b3 100644
--- a/sdc/uart_i2c_usb_spi_top.sdc
+++ b/sdc/uart_i2c_usb_spi_top.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sat Nov 26 13:16:55 2022
+# Thu Dec 1 09:40:58 2022
###############################################################################
current_design uart_i2c_usb_spi_top
###############################################################################
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
index fddc749..ccc31a1 100644
--- a/sdc/user_project_wrapper.sdc
+++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Mon Nov 28 11:11:31 2022
+# Sun Dec 4 11:28:31 2022
###############################################################################
current_design user_project_wrapper
###############################################################################
diff --git a/sdc/wb_host.sdc b/sdc/wb_host.sdc
index 9c35c74..8143a0e 100644
--- a/sdc/wb_host.sdc
+++ b/sdc/wb_host.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Mon Nov 28 06:54:23 2022
+# Thu Dec 1 09:39:39 2022
###############################################################################
current_design wb_host
###############################################################################
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 3531d3e..c553c4b 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_basic user_aes user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_aes_core user_fpu_core
+PATTERNS = user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_basic user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_aes_core user_fpu_core user_aes
all: ${PATTERNS}
echo "################# RTL Test case Summary #####################" > regression.rpt
@@ -27,7 +27,7 @@
#for i in ${PATTERNS}; do \
# ( cd $$i && make | tee run.rtl.log && grep Monitor run.rtl.log | grep $$i >> ../regression.rpt) ; \
#done
- echo "################# GL Test case Summary #####################" >> regression.rpt
+ #echo "################# GL Test case Summary #####################" >> regression.rpt
\rm -rf */*.vvp
for i in ${PATTERNS}; do \
( cd $$i && make SIM=GL | tee run.gl.log && grep Monitor run.gl.log | grep $$i >> ../regression.rpt) ; \
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index ef56ee4..2ea05db 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -143,6 +143,14 @@
initial begin
+ $display("################# NOTE:#####################################");
+ $display("This test assumes Caravel GPIO are pre-programmed with user_define.v value");
+ $display("If you see RTL simulation fails, cross check mgmt_core_wrapper/verilog/includes/includes.rtl.caravel ");
+ $display(" From: -v $(CARAVEL_PATH)/rtl/user_defines.v ");
+ $display(" To: -v $(USER_PROJECT_VERILOG)/rtl/user_defines.v ");
+ $display(" Gate Sim expect to fail as caravel gate netlist have not generated based on user_define.v in user project");
+ $display("#####################################################################################");
+
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (80) begin
repeat (2000) @(posedge clock);
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 401dc92..fc0b5eb 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -219,6 +219,23 @@
test_fail=0;
fork
begin
+ $display("##########################################################");
+ $display("Step-0,Monitor: Checking the chip signature :");
+ $display("###################################################");
+ test_id = 0;
+ test_step = 0;
+ // Remove Wb/PinMux Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,CHIP_SIGNATURE);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,CHIP_RELEASE_DATE);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,CHIP_REVISION);
+ if(test_fail == 1) begin
+ $display("ERROR: Step-0,Monitor: Checking the chip signature - FAILED");
+ end else begin
+ $display("STATUS: Step-0,Monitor: Checking the chip signature - PASSED");
+ $display("##########################################################");
+ end
$display("##########################################################");
$display("Step-1, Checking the Strap Loading");
@@ -512,25 +529,6 @@
$display("##########################################################");
end
- $display("##########################################################");
- $display("Step-11,Monitor: Checking the chip signature :");
- $display("###################################################");
- test_id = 11;
- test_step = 14;
- // Remove Wb/PinMux Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
-
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,CHIP_SIGNATURE);
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,CHIP_RELEASE_DATE);
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,CHIP_REVISION);
- if(test_fail == 1) begin
- $display("ERROR: Step-11,Monitor: Checking the chip signature - FAILED");
- end else begin
- $display("STATUS: Step-11,Monitor: Checking the chip signature - PASSED");
-
- $display("##########################################################");
-
- end
end
begin
repeat (500000) @(posedge clock);
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 9eae583..a769a58 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index f46170f..f8a9197 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -221,6 +221,9 @@
$(USER_PROJECT_VERILOG)/gl/aes_top.v
$(USER_PROJECT_VERILOG)/gl/fpu_wrapper.v
$(USER_PROJECT_VERILOG)/gl/bus_rep_south.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_north.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_east.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_west.v
-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 22e2bc7..e7d042f 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -168,3 +168,6 @@
-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_south.sv
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_north.sv
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_east.sv
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_west.sv
diff --git a/verilog/rtl/bus_rep/bus_rep_south.sv b/verilog/rtl/bus_rep/bus_rep_south.sv
index 32c1521..ea877be 100644
--- a/verilog/rtl/bus_rep/bus_rep_south.sv
+++ b/verilog/rtl/bus_rep/bus_rep_south.sv
@@ -31,8 +31,22 @@
);
// channel repeater
+
+`ifndef SYNTHESIS
+
assign ch_out = ch_in;
+`else
+
+ genvar i;
+ generate
+ for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp
+ sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i]));
+ end
+ endgenerate
+
+`endif
+
endmodule
diff --git a/verilog/rtl/bus_repeater.sv b/verilog/rtl/bus_repeater.sv
index d50fa9f..8312ed8 100644
--- a/verilog/rtl/bus_repeater.sv
+++ b/verilog/rtl/bus_repeater.sv
@@ -1,276 +1,538 @@
/*********************************************
Bus Repeater SOUTH
**********************************************/
-wire wb_clk_int_i;
-wire wb_rst_int_i ;
+wire wb_clk_i_rp;
+wire wb_rst_i_rp ;
+wire wbs_cyc_i_rp ;
+wire wbs_stb_i_rp ;
+wire wbs_we_i_rp ;
+wire [3:0] wbs_sel_i_rp;
+wire [31:0] wbs_adr_i_rp;
+wire [31:0] wbs_dat_i_rp;
+
wire wbs_ack_int_o ;
-wire wbs_cyc_int_i ;
-wire wbs_stb_int_i ;
-wire wbs_we_int_i ;
-wire [3:0] wbs_sel_int_i;
-wire [31:0] wbs_adr_int_i;
-wire [31:0] wbs_dat_int_i;
wire [31:0] wbs_dat_int_o;
wire [17:0] la_data_in_rp;
-wire [123:0] ch_in_south = {
- la_data_in[0],
- la_data_in[1],
- la_data_in[2],
- la_data_in[3],
- la_data_in[4],
- la_data_in[5],
- la_data_in[6],
- la_data_in[7],
- la_data_in[8],
- la_data_in[9],
- la_data_in[10],
- la_data_in[11],
- la_data_in[12],
- la_data_in[13],
- la_data_in[14],
- la_data_in[15],
- la_data_in[16],
+wire [252:0] ch_in_south = {
+ user_clock2,
+ la_data_out_int[127],
+ la_data_out_int[126],
+ la_data_out_int[125],
+ la_data_out_int[124],
+ la_data_out_int[123],
+ la_data_out_int[122],
+ la_data_out_int[121],
+ la_data_out_int[120],
+ la_data_out_int[119],
+ la_data_out_int[118],
+ la_data_out_int[117],
+ la_data_out_int[116],
+ la_data_out_int[115],
+ la_data_out_int[114],
+ la_data_out_int[113],
+ la_data_out_int[112],
+ la_data_out_int[111],
+ la_data_out_int[110],
+ la_data_out_int[109],
+ la_data_out_int[108],
+ la_data_out_int[107],
+ la_data_out_int[106],
+ la_data_out_int[105],
+ la_data_out_int[104],
+ la_data_out_int[103],
+ la_data_out_int[102],
+ la_data_out_int[101],
+ la_data_out_int[100],
+ la_data_out_int[99],
+ la_data_out_int[98],
+ la_data_out_int[97],
+ la_data_out_int[96],
+ la_data_out_int[95],
+ la_data_out_int[94],
+ la_data_out_int[93],
+ la_data_out_int[92],
+ la_data_out_int[91],
+ la_data_out_int[90],
+ la_data_out_int[89],
+ la_data_out_int[88],
+ la_data_out_int[87],
+ la_data_out_int[86],
+ la_data_out_int[85],
+ la_data_out_int[84],
+ la_data_out_int[83],
+ la_data_out_int[82],
+ la_data_out_int[81],
+ la_data_out_int[80],
+ la_data_out_int[79],
+ la_data_out_int[78],
+ la_data_out_int[77],
+ la_data_out_int[76],
+ la_data_out_int[75],
+ la_data_out_int[74],
+ la_data_out_int[73],
+ la_data_out_int[72],
+ la_data_out_int[71],
+ la_data_out_int[70],
+ la_data_out_int[69],
+ la_data_out_int[68],
+ la_data_out_int[67],
+ la_data_out_int[66],
+ la_data_out_int[65],
+ la_data_out_int[64],
+ la_data_out_int[63],
+ la_data_out_int[62],
+ la_data_out_int[61],
+ la_data_out_int[60],
+ la_data_out_int[59],
+ la_data_out_int[58],
+ la_data_out_int[57],
+ la_data_out_int[56],
+ la_data_out_int[55],
+ la_data_out_int[54],
+ la_data_out_int[53],
+ la_data_out_int[52],
+ la_data_out_int[51],
+ la_data_out_int[50],
+ la_data_out_int[49],
+ la_data_out_int[48],
+ la_data_out_int[47],
+ la_data_out_int[46],
+ la_data_out_int[45],
+ la_data_out_int[44],
+ la_data_out_int[43],
+ la_data_out_int[42],
+ la_data_out_int[41],
+ la_data_out_int[40],
+ la_data_out_int[39],
+ la_data_out_int[38],
+ la_data_out_int[37],
+ la_data_out_int[36],
+ la_data_out_int[35],
+ la_data_out_int[34],
+ la_data_out_int[33],
+ la_data_out_int[32],
+ la_data_out_int[31],
+ la_data_out_int[30],
+ la_data_out_int[29],
+ la_data_out_int[28],
+ la_data_out_int[27],
+ la_data_out_int[26],
+ la_data_out_int[25],
+ la_data_out_int[24],
+ la_data_out_int[23],
+ la_data_out_int[22],
+ la_data_out_int[21],
+ la_data_out_int[20],
+ la_data_out_int[19],
+ la_data_out_int[18],
+ la_data_out_int[17],
la_data_in[17],
- wb_clk_i , // 105
- wb_rst_i , //
- wbs_ack_int_o , // 103
- wbs_cyc_i ,
- wbs_stb_i ,
- wbs_we_i ,
- wbs_adr_i[0] ,
- wbs_dat_i[0] ,
- wbs_dat_int_o[0] , // 97
- wbs_sel_i[0] ,
- wbs_adr_i[1] ,
- wbs_dat_i[1] ,
- wbs_dat_int_o[1] , // 93
- wbs_sel_i[1] ,
- wbs_adr_i[2] ,
- wbs_dat_i[2] ,
- wbs_dat_int_o[2] , // 89
- wbs_sel_i[2] ,
- wbs_adr_i[3] ,
- wbs_dat_i[3] ,
- wbs_dat_int_o[3] , // 85
- wbs_sel_i[3] ,
- wbs_adr_i[4] ,
- wbs_dat_i[4] ,
- wbs_dat_int_o[4] , // 81
- wbs_adr_i[5] ,
- wbs_dat_i[5] ,
- wbs_dat_int_o[5] , // 78
- wbs_adr_i[6] ,
- wbs_dat_i[6] ,
- wbs_dat_int_o[6] , // 75
- wbs_adr_i[7] ,
- wbs_dat_i[7] ,
- wbs_dat_int_o[7] , // 72
- wbs_adr_i[8] ,
- wbs_dat_i[8] ,
- wbs_dat_int_o[8] , // 69
- wbs_adr_i[9] ,
- wbs_dat_i[9] ,
- wbs_dat_int_o[9] , // 66
- wbs_adr_i[10] ,
- wbs_dat_i[10] ,
- wbs_dat_int_o[10] , // 63
- wbs_adr_i[11] ,
- wbs_dat_i[11] ,
- wbs_dat_int_o[11] , // 60
- wbs_adr_i[12] ,
- wbs_dat_i[12] ,
- wbs_dat_int_o[12] , // 57
- wbs_adr_i[13] ,
- wbs_dat_i[13] ,
- wbs_dat_int_o[13] , // 54
- wbs_adr_i[14] ,
- wbs_dat_i[14] ,
- wbs_dat_int_o[14] , // 51
- wbs_adr_i[15] ,
- wbs_dat_i[15] ,
- wbs_dat_int_o[15] , // 48
- wbs_adr_i[16] ,
- wbs_dat_i[16] ,
- wbs_dat_int_o[16] , // 45
- wbs_adr_i[17] ,
- wbs_dat_i[17] ,
- wbs_dat_int_o[17] , // 42
- wbs_adr_i[18] ,
- wbs_dat_i[18] ,
- wbs_dat_int_o[18] , // 39
- wbs_adr_i[19] ,
- wbs_dat_i[19] ,
- wbs_dat_int_o[19] , // 36
- wbs_adr_i[20] ,
- wbs_dat_i[20] ,
- wbs_dat_int_o[20] , // 33
- wbs_adr_i[21] ,
- wbs_dat_i[21] ,
- wbs_dat_int_o[21] , // 30
- wbs_adr_i[22] ,
- wbs_dat_i[22] ,
- wbs_dat_int_o[22] , // 27
- wbs_adr_i[23] ,
- wbs_dat_i[23] ,
- wbs_dat_int_o[23] , // 24
- wbs_adr_i[24] ,
- wbs_dat_i[24] ,
- wbs_dat_int_o[24] , // 21
- wbs_adr_i[25] ,
- wbs_dat_i[25] ,
- wbs_dat_int_o[25] , // 18
- wbs_adr_i[26] ,
- wbs_dat_i[26] ,
- wbs_dat_int_o[26] , // 15
- wbs_adr_i[27] ,
- wbs_dat_i[27] ,
- wbs_dat_int_o[27] , // 12
- wbs_adr_i[28] ,
- wbs_dat_i[28] ,
- wbs_dat_int_o[28] , // 9
- wbs_adr_i[29] ,
- wbs_dat_i[29] ,
- wbs_dat_int_o[29] , // 6
- wbs_adr_i[30] ,
- wbs_dat_i[30] ,
- wbs_dat_int_o[30] , // 3
- wbs_adr_i[31] ,
+ la_data_out_int[16],
+ la_data_in[16],
+ la_data_out_int[15],
+ la_data_in[15],
+ la_data_out_int[14],
+ la_data_in[14],
+ la_data_out_int[13],
+ la_data_in[13],
+ la_data_out_int[12],
+ la_data_in[12],
+ la_data_out_int[11],
+ la_data_in[11],
+ la_data_out_int[10],
+ la_data_in[10],
+ la_data_out_int[9],
+ la_data_in[9],
+ la_data_out_int[8],
+ la_data_in[8],
+ la_data_out_int[7],
+ la_data_in[7],
+ la_data_out_int[6],
+ la_data_in[6],
+ la_data_out_int[5],
+ la_data_in[5],
+ la_data_out_int[4],
+ la_data_in[4],
+ la_data_out_int[3],
+ la_data_in[3],
+ la_data_out_int[2],
+ la_data_in[2],
+ la_data_out_int[1],
+ la_data_in[1],
+ la_data_out_int[0],
+ la_data_in[0],
+
+ wbs_dat_int_o[31] , // 105
wbs_dat_i[31] ,
- wbs_dat_int_o[31]
+ wbs_adr_i[31] ,
+ wbs_dat_int_o[30] ,
+ wbs_dat_i[30] ,
+ wbs_adr_i[30] ,
+ wbs_dat_int_o[29] ,
+ wbs_dat_i[29] ,
+ wbs_adr_i[29] ,
+ wbs_dat_int_o[28] ,
+ wbs_dat_i[28] ,
+ wbs_adr_i[28] ,
+ wbs_dat_int_o[27] ,
+ wbs_dat_i[27] ,
+ wbs_adr_i[27] ,
+ wbs_dat_int_o[26] ,
+ wbs_dat_i[26] ,
+ wbs_adr_i[26] ,
+ wbs_dat_int_o[25] ,
+ wbs_dat_i[25] ,
+ wbs_adr_i[25] ,
+ wbs_dat_int_o[24] ,
+ wbs_dat_i[24] ,
+ wbs_adr_i[24] ,
+ wbs_dat_int_o[23] ,
+ wbs_dat_i[23] ,
+ wbs_adr_i[23] ,
+ wbs_dat_int_o[22] ,
+ wbs_dat_i[22] ,
+ wbs_adr_i[22] ,
+ wbs_dat_int_o[21] ,
+ wbs_dat_i[21] ,
+ wbs_adr_i[21] ,
+ wbs_dat_int_o[20] ,
+ wbs_dat_i[20] ,
+ wbs_adr_i[20] ,
+ wbs_dat_int_o[19] ,
+ wbs_dat_i[19] ,
+ wbs_adr_i[19] ,
+ wbs_dat_int_o[18] ,
+ wbs_dat_i[18] ,
+ wbs_adr_i[18] ,
+ wbs_dat_int_o[17] ,
+ wbs_dat_i[17] ,
+ wbs_adr_i[17] ,
+ wbs_dat_int_o[16] ,
+ wbs_dat_i[16] ,
+ wbs_adr_i[16] ,
+ wbs_dat_int_o[15] ,
+ wbs_dat_i[15] ,
+ wbs_adr_i[15] ,
+ wbs_dat_int_o[14] ,
+ wbs_dat_i[14] ,
+ wbs_adr_i[14] ,
+ wbs_dat_int_o[13] ,
+ wbs_dat_i[13] ,
+ wbs_adr_i[13] ,
+ wbs_dat_int_o[12] ,
+ wbs_dat_i[12] ,
+ wbs_adr_i[12] ,
+ wbs_dat_int_o[11] ,
+ wbs_dat_i[11] ,
+ wbs_adr_i[11] ,
+ wbs_dat_int_o[10] ,
+ wbs_dat_i[10] ,
+ wbs_adr_i[10] ,
+ wbs_dat_int_o[9] ,
+ wbs_dat_i[9] ,
+ wbs_adr_i[9] ,
+ wbs_dat_int_o[8] , // 36
+ wbs_dat_i[8] ,
+ wbs_adr_i[8] ,
+ wbs_dat_int_o[7] , // 33
+ wbs_dat_i[7] ,
+ wbs_adr_i[7] ,
+ wbs_dat_int_o[6] , // 30
+ wbs_dat_i[6] ,
+ wbs_adr_i[6] ,
+ wbs_dat_int_o[5] , // 27
+ wbs_dat_i[5] ,
+ wbs_adr_i[5] ,
+ wbs_dat_int_o[4] , // 24
+ wbs_dat_i[4] ,
+ wbs_adr_i[4] ,
+ wbs_sel_i[3] ,
+ wbs_dat_int_o[3] , // 20
+ wbs_dat_i[3] ,
+ wbs_adr_i[3] ,
+ wbs_sel_i[2] ,
+ wbs_dat_int_o[2] , // 16
+ wbs_dat_i[2] ,
+ wbs_adr_i[2] ,
+ wbs_sel_i[1] ,
+ wbs_dat_int_o[1] , // 12
+ wbs_dat_i[1] ,
+ wbs_adr_i[1] ,
+ wbs_sel_i[0] ,
+ wbs_dat_int_o[0] , // 8
+ wbs_dat_i[0] ,
+ wbs_adr_i[0] ,
+ wbs_we_i ,
+ wbs_stb_i ,
+ wbs_cyc_i ,
+ wbs_ack_int_o ,
+ wb_rst_i ,
+ wb_clk_i
};
-wire [123:0] ch_out_south ;
+wire [252:0] ch_out_south ;
assign {
- la_data_in_rp[0] ,
- la_data_in_rp[1] ,
- la_data_in_rp[2] ,
- la_data_in_rp[3] ,
- la_data_in_rp[4] ,
- la_data_in_rp[5] ,
- la_data_in_rp[6] ,
- la_data_in_rp[7] ,
- la_data_in_rp[8] ,
- la_data_in_rp[9] ,
- la_data_in_rp[10] ,
- la_data_in_rp[11] ,
- la_data_in_rp[12] ,
- la_data_in_rp[13] ,
- la_data_in_rp[14] ,
- la_data_in_rp[15] ,
- la_data_in_rp[16] ,
- la_data_in_rp[17] ,
- wb_clk_int_i ,
- wb_rst_int_i ,
- wbs_ack_o ,
- wbs_cyc_int_i ,
- wbs_stb_int_i ,
- wbs_we_int_i ,
- wbs_adr_int_i[0] ,
- wbs_dat_int_i[0] ,
- wbs_dat_o[0] ,
- wbs_sel_int_i[0] ,
- wbs_adr_int_i[1] ,
- wbs_dat_int_i[1] ,
- wbs_dat_o[1] ,
- wbs_sel_int_i[1] ,
- wbs_adr_int_i[2] ,
- wbs_dat_int_i[2] ,
- wbs_dat_o[2] ,
- wbs_sel_int_i[2] ,
- wbs_adr_int_i[3] ,
- wbs_dat_int_i[3] ,
- wbs_dat_o[3] ,
- wbs_sel_int_i[3] ,
- wbs_adr_int_i[4] ,
- wbs_dat_int_i[4] ,
- wbs_dat_o[4] ,
- wbs_adr_int_i[5] ,
- wbs_dat_int_i[5] ,
- wbs_dat_o[5] ,
- wbs_adr_int_i[6] ,
- wbs_dat_int_i[6] ,
- wbs_dat_o[6] ,
- wbs_adr_int_i[7] ,
- wbs_dat_int_i[7] ,
- wbs_dat_o[7] ,
- wbs_adr_int_i[8] ,
- wbs_dat_int_i[8] ,
- wbs_dat_o[8] ,
- wbs_adr_int_i[9] ,
- wbs_dat_int_i[9] ,
- wbs_dat_o[9] ,
- wbs_adr_int_i[10] ,
- wbs_dat_int_i[10] ,
- wbs_dat_o[10] ,
- wbs_adr_int_i[11] ,
- wbs_dat_int_i[11] ,
- wbs_dat_o[11] ,
- wbs_adr_int_i[12] ,
- wbs_dat_int_i[12] ,
- wbs_dat_o[12] ,
- wbs_adr_int_i[13] ,
- wbs_dat_int_i[13] ,
- wbs_dat_o[13] ,
- wbs_adr_int_i[14] ,
- wbs_dat_int_i[14] ,
- wbs_dat_o[14] ,
- wbs_adr_int_i[15] ,
- wbs_dat_int_i[15] ,
- wbs_dat_o[15] ,
- wbs_adr_int_i[16] ,
- wbs_dat_int_i[16] ,
- wbs_dat_o[16] ,
- wbs_adr_int_i[17] ,
- wbs_dat_int_i[17] ,
- wbs_dat_o[17] ,
- wbs_adr_int_i[18] ,
- wbs_dat_int_i[18] ,
- wbs_dat_o[18] ,
- wbs_adr_int_i[19] ,
- wbs_dat_int_i[19] ,
- wbs_dat_o[19] ,
- wbs_adr_int_i[20] ,
- wbs_dat_int_i[20] ,
- wbs_dat_o[20] ,
- wbs_adr_int_i[21] ,
- wbs_dat_int_i[21] ,
- wbs_dat_o[21] ,
- wbs_adr_int_i[22] ,
- wbs_dat_int_i[22] ,
- wbs_dat_o[22] ,
- wbs_adr_int_i[23] ,
- wbs_dat_int_i[23] ,
- wbs_dat_o[23] ,
- wbs_adr_int_i[24] ,
- wbs_dat_int_i[24] ,
- wbs_dat_o[24] ,
- wbs_adr_int_i[25] ,
- wbs_dat_int_i[25] ,
- wbs_dat_o[25] ,
- wbs_adr_int_i[26] ,
- wbs_dat_int_i[26] ,
- wbs_dat_o[26] ,
- wbs_adr_int_i[27] ,
- wbs_dat_int_i[27] ,
- wbs_dat_o[27] ,
- wbs_adr_int_i[28] ,
- wbs_dat_int_i[28] ,
- wbs_dat_o[28] ,
- wbs_adr_int_i[29] ,
- wbs_dat_int_i[29] ,
- wbs_dat_o[29] ,
- wbs_adr_int_i[30] ,
- wbs_dat_int_i[30] ,
- wbs_dat_o[30] ,
- wbs_adr_int_i[31] ,
- wbs_dat_int_i[31] ,
- wbs_dat_o[31]
+ user_clock2_rp ,
+ la_data_out[127],
+ la_data_out[126],
+ la_data_out[125],
+ la_data_out[124],
+ la_data_out[123],
+ la_data_out[122],
+ la_data_out[121],
+ la_data_out[120],
+ la_data_out[119],
+ la_data_out[118],
+ la_data_out[117],
+ la_data_out[116],
+ la_data_out[115],
+ la_data_out[114],
+ la_data_out[113],
+ la_data_out[112],
+ la_data_out[111],
+ la_data_out[110],
+ la_data_out[109],
+ la_data_out[108],
+ la_data_out[107],
+ la_data_out[106],
+ la_data_out[105],
+ la_data_out[104],
+ la_data_out[103],
+ la_data_out[102],
+ la_data_out[101],
+ la_data_out[100],
+ la_data_out[99],
+ la_data_out[98],
+ la_data_out[97],
+ la_data_out[96],
+ la_data_out[95],
+ la_data_out[94],
+ la_data_out[93],
+ la_data_out[92],
+ la_data_out[91],
+ la_data_out[90],
+ la_data_out[89],
+ la_data_out[88],
+ la_data_out[87],
+ la_data_out[86],
+ la_data_out[85],
+ la_data_out[84],
+ la_data_out[83],
+ la_data_out[82],
+ la_data_out[81],
+ la_data_out[80],
+ la_data_out[79],
+ la_data_out[78],
+ la_data_out[77],
+ la_data_out[76],
+ la_data_out[75],
+ la_data_out[74],
+ la_data_out[73],
+ la_data_out[72],
+ la_data_out[71],
+ la_data_out[70],
+ la_data_out[69],
+ la_data_out[68],
+ la_data_out[67],
+ la_data_out[66],
+ la_data_out[65],
+ la_data_out[64],
+ la_data_out[63],
+ la_data_out[62],
+ la_data_out[61],
+ la_data_out[60],
+ la_data_out[59],
+ la_data_out[58],
+ la_data_out[57],
+ la_data_out[56],
+ la_data_out[55],
+ la_data_out[54],
+ la_data_out[53],
+ la_data_out[52],
+ la_data_out[51],
+ la_data_out[50],
+ la_data_out[49],
+ la_data_out[48],
+ la_data_out[47],
+ la_data_out[46],
+ la_data_out[45],
+ la_data_out[44],
+ la_data_out[43],
+ la_data_out[42],
+ la_data_out[41],
+ la_data_out[40],
+ la_data_out[39],
+ la_data_out[38],
+ la_data_out[37],
+ la_data_out[36],
+ la_data_out[35],
+ la_data_out[34],
+ la_data_out[33],
+ la_data_out[32],
+ la_data_out[31],
+ la_data_out[30],
+ la_data_out[29],
+ la_data_out[28],
+ la_data_out[27],
+ la_data_out[26],
+ la_data_out[25],
+ la_data_out[24],
+ la_data_out[23],
+ la_data_out[22],
+ la_data_out[21],
+ la_data_out[20],
+ la_data_out[19],
+ la_data_out[18],
+ la_data_out[17],
+ la_data_in_rp[17],
+ la_data_out[16],
+ la_data_in_rp[16],
+ la_data_out[15],
+ la_data_in_rp[15],
+ la_data_out[14],
+ la_data_in_rp[14],
+ la_data_out[13],
+ la_data_in_rp[13],
+ la_data_out[12],
+ la_data_in_rp[12],
+ la_data_out[11],
+ la_data_in_rp[11],
+ la_data_out[10],
+ la_data_in_rp[10],
+ la_data_out[9],
+ la_data_in_rp[9],
+ la_data_out[8],
+ la_data_in_rp[8],
+ la_data_out[7],
+ la_data_in_rp[7],
+ la_data_out[6],
+ la_data_in_rp[6],
+ la_data_out[5],
+ la_data_in_rp[5],
+ la_data_out[4],
+ la_data_in_rp[4],
+ la_data_out[3],
+ la_data_in_rp[3],
+ la_data_out[2],
+ la_data_in_rp[2],
+ la_data_out[1],
+ la_data_in_rp[1],
+ la_data_out[0],
+ la_data_in_rp[0],
+
+ wbs_dat_o[31] ,
+ wbs_dat_i_rp[31],
+ wbs_adr_i_rp[31],
+ wbs_dat_o[30] ,
+ wbs_dat_i_rp[30],
+ wbs_adr_i_rp[30],
+ wbs_dat_o[29] ,
+ wbs_dat_i_rp[29],
+ wbs_adr_i_rp[29],
+ wbs_dat_o[28] ,
+ wbs_dat_i_rp[28],
+ wbs_adr_i_rp[28],
+ wbs_dat_o[27] ,
+ wbs_dat_i_rp[27],
+ wbs_adr_i_rp[27],
+ wbs_dat_o[26] ,
+ wbs_dat_i_rp[26],
+ wbs_adr_i_rp[26],
+ wbs_dat_o[25] ,
+ wbs_dat_i_rp[25],
+ wbs_adr_i_rp[25],
+ wbs_dat_o[24] ,
+ wbs_dat_i_rp[24],
+ wbs_adr_i_rp[24],
+ wbs_dat_o[23] ,
+ wbs_dat_i_rp[23],
+ wbs_adr_i_rp[23],
+ wbs_dat_o[22] ,
+ wbs_dat_i_rp[22],
+ wbs_adr_i_rp[22],
+ wbs_dat_o[21] ,
+ wbs_dat_i_rp[21],
+ wbs_adr_i_rp[21],
+ wbs_dat_o[20] ,
+ wbs_dat_i_rp[20],
+ wbs_adr_i_rp[20],
+ wbs_dat_o[19] ,
+ wbs_dat_i_rp[19],
+ wbs_adr_i_rp[19],
+ wbs_dat_o[18] ,
+ wbs_dat_i_rp[18],
+ wbs_adr_i_rp[18],
+ wbs_dat_o[17] ,
+ wbs_dat_i_rp[17],
+ wbs_adr_i_rp[17],
+ wbs_dat_o[16] ,
+ wbs_dat_i_rp[16],
+ wbs_adr_i_rp[16],
+ wbs_dat_o[15] ,
+ wbs_dat_i_rp[15],
+ wbs_adr_i_rp[15],
+ wbs_dat_o[14] ,
+ wbs_dat_i_rp[14],
+ wbs_adr_i_rp[14],
+ wbs_dat_o[13] ,
+ wbs_dat_i_rp[13],
+ wbs_adr_i_rp[13],
+ wbs_dat_o[12] ,
+ wbs_dat_i_rp[12],
+ wbs_adr_i_rp[12],
+ wbs_dat_o[11] ,
+ wbs_dat_i_rp[11],
+ wbs_adr_i_rp[11],
+ wbs_dat_o[10] ,
+ wbs_dat_i_rp[10],
+ wbs_adr_i_rp[10],
+ wbs_dat_o[9] ,
+ wbs_dat_i_rp[9],
+ wbs_adr_i_rp[9],
+ wbs_dat_o[8] ,
+ wbs_dat_i_rp[8],
+ wbs_adr_i_rp[8],
+ wbs_dat_o[7] ,
+ wbs_dat_i_rp[7],
+ wbs_adr_i_rp[7],
+ wbs_dat_o[6] ,
+ wbs_dat_i_rp[6],
+ wbs_adr_i_rp[6],
+ wbs_dat_o[5] ,
+ wbs_dat_i_rp[5],
+ wbs_adr_i_rp[5],
+ wbs_dat_o[4] ,
+ wbs_dat_i_rp[4],
+ wbs_adr_i_rp[4],
+
+ wbs_sel_i_rp[3] ,
+ wbs_dat_o[3] ,
+ wbs_dat_i_rp[3] ,
+ wbs_adr_i_rp[3] ,
+ wbs_sel_i_rp[2] ,
+ wbs_dat_o[2] ,
+ wbs_dat_i_rp[2] ,
+ wbs_adr_i_rp[2] ,
+ wbs_sel_i_rp[1] ,
+ wbs_dat_o[1] ,
+ wbs_dat_i_rp[1] ,
+ wbs_adr_i_rp[1] ,
+ wbs_sel_i_rp[0] ,
+ wbs_dat_o[0] ,
+ wbs_dat_i_rp[0] ,
+ wbs_adr_i_rp[0] ,
+ wbs_we_i_rp ,
+ wbs_stb_i_rp ,
+ wbs_cyc_i_rp ,
+ wbs_ack_o ,
+ wb_rst_i_rp ,
+ wb_clk_i_rp
} = ch_out_south;
bus_rep_south #(
`ifndef SYNTHESIS
-.BUS_REP_WD(124)
+.BUS_REP_WD(253)
`endif
) u_rp_south(
`ifdef USE_POWER_PINS
@@ -280,3 +542,318 @@
.ch_in (ch_in_south),
.ch_out (ch_out_south)
);
+
+
+/*********************************************
+ Bus Repeater WEST
+**********************************************/
+
+wire [41:0] ch_in_west = {
+ io_oeb_int[37],
+ io_out_int[37],
+ io_in[37],
+ io_oeb_int[36],
+ io_out_int[36],
+ io_in[36],
+ io_oeb_int[35],
+ io_out_int[35],
+ io_in[35],
+ io_oeb_int[34],
+ io_out_int[34],
+ io_in[34],
+ io_oeb_int[33],
+ io_out_int[33],
+ io_in[33],
+ io_oeb_int[32],
+ io_out_int[32],
+ io_in[32],
+ io_oeb_int[31],
+ io_out_int[31],
+ io_in[31],
+ io_oeb_int[30],
+ io_out_int[30],
+ io_in[30],
+ io_oeb_int[29],
+ io_out_int[29],
+ io_in[29],
+ io_oeb_int[28],
+ io_out_int[28],
+ io_in[28],
+ io_oeb_int[27],
+ io_out_int[27],
+ io_in[27],
+ io_oeb_int[26],
+ io_out_int[26],
+ io_in[26],
+ io_oeb_int[25],
+ io_out_int[25],
+ io_in[25],
+ io_oeb_int[24],
+ io_out_int[24],
+ io_in[24]
+ };
+
+wire [41:0] ch_out_west ;
+assign {
+ io_oeb[37],
+ io_out[37],
+ io_in_rp[37],
+ io_oeb[36],
+ io_out[36],
+ io_in_rp[36],
+ io_oeb[35],
+ io_out[35],
+ io_in_rp[35],
+ io_oeb[34],
+ io_out[34],
+ io_in_rp[34],
+ io_oeb[33],
+ io_out[33],
+ io_in_rp[33],
+ io_oeb[32],
+ io_out[32],
+ io_in_rp[32],
+ io_oeb[31],
+ io_out[31],
+ io_in_rp[31],
+ io_oeb[30],
+ io_out[30],
+ io_in_rp[30],
+ io_oeb[29],
+ io_out[29],
+ io_in_rp[29],
+ io_oeb[28],
+ io_out[28],
+ io_in_rp[28],
+ io_oeb[27],
+ io_out[27],
+ io_in_rp[27],
+ io_oeb[26],
+ io_out[26],
+ io_in_rp[26],
+ io_oeb[25],
+ io_out[25],
+ io_in_rp[25],
+ io_oeb[24],
+ io_out[24],
+ io_in_rp[24]
+
+ } = ch_out_west;
+
+bus_rep_west #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(42)
+`endif
+ ) u_rp_west(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
+`endif
+ .ch_in (ch_in_west),
+ .ch_out (ch_out_west)
+ );
+
+/*********************************************
+ Bus Repeater NORTH
+**********************************************/
+
+wire [26:0] ch_in_north = {
+ io_in[15],
+ io_out_int[15],
+ io_oeb_int[15],
+ io_in[16],
+ io_out_int[16],
+ io_oeb_int[16],
+ io_in[17],
+ io_out_int[17],
+ io_oeb_int[17],
+ io_in[18],
+ io_out_int[18],
+ io_oeb_int[18],
+ io_in[19],
+ io_out_int[19],
+ io_oeb_int[19],
+ io_in[20],
+ io_out_int[20],
+ io_oeb_int[20],
+ io_in[21],
+ io_out_int[21],
+ io_oeb_int[21],
+ io_in[22],
+ io_out_int[22],
+ io_oeb_int[22],
+ io_in[23],
+ io_out_int[23],
+ io_oeb_int[23]
+ };
+
+
+wire [26:0] ch_out_north ;
+assign {
+ io_in_rp[15],
+ io_out[15],
+ io_oeb[15],
+ io_in_rp[16],
+ io_out[16],
+ io_oeb[16],
+ io_in_rp[17],
+ io_out[17],
+ io_oeb[17],
+ io_in_rp[18],
+ io_out[18],
+ io_oeb[18],
+ io_in_rp[19],
+ io_out[19],
+ io_oeb[19],
+ io_in_rp[20],
+ io_out[20],
+ io_oeb[20],
+ io_in_rp[21],
+ io_out[21],
+ io_oeb[21],
+ io_in_rp[22],
+ io_out[22],
+ io_oeb[22],
+ io_in_rp[23],
+ io_out[23],
+ io_oeb[23]
+ } = ch_out_north;
+
+bus_rep_north #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(27)
+`endif
+ ) u_rp_north(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
+`endif
+ .ch_in (ch_in_north),
+ .ch_out (ch_out_north)
+ );
+
+/*********************************************
+ Bus Repeater EAST
+**********************************************/
+
+wire [44:0] ch_in_east = {
+ io_in[0],
+ io_out_int[0],
+ io_oeb_int[0],
+ io_in[1],
+ io_out_int[1],
+ io_oeb_int[1],
+ io_in[2],
+ io_out_int[2],
+ io_oeb_int[2],
+ io_in[3],
+ io_out_int[3],
+ io_oeb_int[3],
+ io_in[4],
+ io_out_int[4],
+ io_oeb_int[4],
+ io_in[5],
+ io_out_int[5],
+ io_oeb_int[5],
+ io_in[6],
+ io_out_int[6],
+ io_oeb_int[6],
+ io_in[7],
+ io_out_int[7],
+ io_oeb_int[7],
+ io_in[8],
+ io_out_int[8],
+ io_oeb_int[8],
+ io_in[9],
+ io_out_int[9],
+ io_oeb_int[9],
+ io_in[10],
+ io_out_int[10],
+ io_oeb_int[10],
+ io_in[11],
+ io_out_int[11],
+ io_oeb_int[11],
+ io_in[12],
+ io_out_int[12],
+ io_oeb_int[12],
+ io_in[13],
+ io_out_int[13],
+ io_oeb_int[13],
+ io_in[14],
+ io_out_int[14],
+ io_oeb_int[14]
+ };
+
+
+wire [44:0] ch_out_east ;
+assign {
+ io_in_rp[0],
+ io_out[0],
+ io_oeb[0],
+ io_in_rp[1],
+ io_out[1],
+ io_oeb[1],
+ io_in_rp[2],
+ io_out[2],
+ io_oeb[2],
+ io_in_rp[3],
+ io_out[3],
+ io_oeb[3],
+ io_in_rp[4],
+ io_out[4],
+ io_oeb[4],
+ io_in_rp[5],
+ io_out[5],
+ io_oeb[5],
+ io_in_rp[6],
+ io_out[6],
+ io_oeb[6],
+ io_in_rp[7],
+ io_out[7],
+ io_oeb[7],
+ io_in_rp[8],
+ io_out[8],
+ io_oeb[8],
+ io_in_rp[9],
+ io_out[9],
+ io_oeb[9],
+ io_in_rp[10],
+ io_out[10],
+ io_oeb[10],
+ io_in_rp[11],
+ io_out[11],
+ io_oeb[11],
+ io_in_rp[12],
+ io_out[12],
+ io_oeb[12],
+ io_in_rp[13],
+ io_out[13],
+ io_oeb[13],
+ io_in_rp[14],
+ io_out[14],
+ io_oeb[14]
+ } = ch_out_east;
+
+bus_rep_east #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(45)
+`endif
+ ) u_rp_east(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
+`endif
+ .ch_in (ch_in_east),
+ .ch_out (ch_out_east)
+ );
+
+//---------------------------------------------------------
+// No Repeated added for these ports yet
+//---------------------------------------------------------
+//assign io_oeb[14:0] = io_oeb_int[14:0];
+//assign io_out[14:0] = io_out_int[14:0];
+//assign io_in_rp[14:0] = io_in[14:0];
+
+//assign io_oeb[37:24] = io_oeb_int[37:24];
+//assign io_out[37:24] = io_out_int[37:24];
+//assign io_in_rp[37:24] = io_in[37:24];
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index 58da5bf..99bbf33 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,9 +4,9 @@
// ASCI Representation of RISC = 32'h8273_8343
parameter CHIP_SIGNATURE = 32'h8273_8343;
// Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h2811_2022;
+parameter CHIP_RELEASE_DATE = 32'h0412_2022;
// Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION = 32'h0006_1000;
+parameter CHIP_REVISION = 32'h0006_2000;
parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_0100_1000_1000_1110_1000_0100;
parameter CLK_SKEW2_RESET_VAL = 32'b1000_1000_1000_1000_1000_0100_0111_1110;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 54a4b24..6a818d1 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -298,6 +298,9 @@
//// 6.1 Nov 28, 2022, Dinesh A ////
//// Power Hook up connectivity issue for ////
//// aes,fpu,bus repeater is fixed ////
+//// 6.2 Dec 4, 2022, Dinesh A ////
+//// Bus repeater north/south/east/west added for better ////
+//// global buffering ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -880,7 +883,7 @@
assign cfg_ccska_aes = cfg_clk_skew_ctrl2[27:24];
assign cfg_ccska_fpu = cfg_clk_skew_ctrl2[31:28];
-assign la_data_out[127:0] = {pinmux_debug,spi_debug,riscv_debug};
+wire [127:0] la_data_out_int = {pinmux_debug,spi_debug,riscv_debug};
wire int_pll_clock = pll_clk_out[0];
@@ -894,6 +897,13 @@
wire cpu_clk_rp_fpu = cpu_clk_rp[7];
wire cpu_clk_rp_pinmux = cpu_clk_rp[8];
+//----------------------------------------------------------
+// Bus Repeater Initiatiation
+//----------------------------------------------------------
+wire [37:0] io_in_rp ;
+wire [37:0] io_out_int ;
+wire [37:0] io_oeb_int ;
+wire user_clock2_rp ;
`include "bus_repeater.sv"
@@ -906,8 +916,8 @@
.vccd1 (vccd1 ),// User area 1 1.8V supply
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .user_clock1 (wb_clk_int_i ),
- .user_clock2 (user_clock2 ),
+ .user_clock1 (wb_clk_i_rp ),
+ .user_clock2 (user_clock2_rp ),
.int_pll_clock (int_pll_clock ),
.cpu_clk (cpu_clk ),
@@ -926,14 +936,14 @@
.wbd_pll_rst_n (wbd_pll_rst_n ),
// Master Port
- .wbm_rst_i (wb_rst_int_i ),
- .wbm_clk_i (wb_clk_int_i ),
- .wbm_cyc_i (wbs_cyc_int_i ),
- .wbm_stb_i (wbs_stb_int_i ),
- .wbm_adr_i (wbs_adr_int_i ),
- .wbm_we_i (wbs_we_int_i ),
- .wbm_dat_i (wbs_dat_int_i ),
- .wbm_sel_i (wbs_sel_int_i ),
+ .wbm_rst_i (wb_rst_i_rp ),
+ .wbm_clk_i (wb_clk_i_rp ),
+ .wbm_cyc_i (wbs_cyc_i_rp ),
+ .wbm_stb_i (wbs_stb_i_rp ),
+ .wbm_adr_i (wbs_adr_i_rp ),
+ .wbm_we_i (wbs_we_i_rp ),
+ .wbm_dat_i (wbs_dat_i_rp ),
+ .wbm_sel_i (wbs_sel_i_rp ),
.wbm_dat_o (wbs_dat_int_o ),
.wbm_ack_o (wbs_ack_int_o ),
.wbm_err_o ( ),
@@ -1614,8 +1624,8 @@
.strap_sticky (strap_sticky ),
.strap_uartm (strap_uartm ),
- .user_clock1 (wb_clk_int_i ),
- .user_clock2 (user_clock2 ),
+ .user_clock1 (wb_clk_i_rp ),
+ .user_clock2 (user_clock2_rp ),
.int_pll_clock (int_pll_clock ),
.xtal_clk (xtal_clk ),
.cpu_clk (cpu_clk_rp_pinmux ),
@@ -1654,9 +1664,9 @@
.i2cm_intr (i2cm_intr_o ),
// Digital IO
- .digital_io_out (io_out ),
- .digital_io_oen (io_oeb ),
- .digital_io_in (io_in ),
+ .digital_io_out (io_out_int ),
+ .digital_io_oen (io_oeb_int ),
+ .digital_io_in (io_in_rp ),
// SFLASH I/F
.sflash_sck (sflash_sck ),
