tb update
diff --git a/sta/scripts/riscdunio.tcl b/sta/scripts/riscdunio.tcl
index 486242c..7f63af6 100644
--- a/sta/scripts/riscdunio.tcl
+++ b/sta/scripts/riscdunio.tcl
@@ -1,11 +1,9 @@
- set ::env(USER_ROOT) "/home/dinesha/workarea/opencore/git/riscduino"
- #set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
- #set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4"
- set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
- set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4"
+ set ::env(USER_ROOT) ".."
+ set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-6/caravel"
+ set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw6"
- read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib
@@ -24,63 +22,107 @@
read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib
read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib
- puts "IP :: Total Cell :: Total register"
- read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
- link_design qspim_top
- set tcell [llength [get_cell -hier *]]
- set tregs [llength [all_registers]]
- puts "qspim :: $tcell :: $tregs "
+ source scripts/statistic.tcl
+ set c_seq_cnt 0
+ set c_comb_cnt 0
+ set c_total_cnt 0
- read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v
- link_design ycr1_top_wb
- set tcell [llength [get_cell -hier *]]
- set tregs [llength [all_registers]]
- puts "yifive :: $tcell :: $tregs "
+ read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v
+ link_design qspim_top
+ puts "IP :: Total Cell :: Total Combo :: Total Sequential"
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "qspim_top :: $tcell :: $tregs "
+ lassign [get_statistic qspim_top] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
- read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_iconnect.v
+ link_design ycr_iconnect
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_iconnect :: $tcell :: $tregs "
+ lassign [get_statistic ycr_iconnect] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
+ link_design ycr_intf
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic ycr_intf] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v
+ link_design ycr_core_top
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic ycr_core_top] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v
link_design uart_i2c_usb_spi_top
- set tcell [llength [get_cell -hier *]]
- set tregs [llength [all_registers]]
- puts "uart_i2cm_usb_spi :: $tcell :: $tregs "
-
- read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic uart_i2c_usb_spi_top] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
link_design wb_host
- set tcell [llength [get_cell -hier *]]
- set tregs [llength [all_registers]]
- puts "wb_host :: $tcell :: $tregs "
-
- read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic wb_host] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
link_design wb_interconnect
- set tcell [llength [get_cell -hier *]]
- set tregs [llength [all_registers]]
- puts "wb_interconnect :: $tcell :: $tregs "
-
- read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic wb_interconnect] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
link_design pinmux
- set tcell [llength [get_cell -hier *]]
- set tregs [llength [all_registers]]
- puts "pinmux :: $tcell :: $tregs "
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic pinmux] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
- read_verilog $::env(USER_ROOT)/verilog/gl/DFFRAM.v
- link_design DFFRAM
- set tcell [llength [get_cell -hier *]]
- set tregs [llength [all_registers]]
- puts "DFFRAM :: $tcell :: $tregs "
+ puts "digital_top :: $c_total_cnt :: $c_comb_cnt :: $c_seq_cnt"
+ # read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/DFFRAM.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v
- read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v
- read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
- read_verilog $::env(USER_ROOT)/verilog/gl/DFFRAM.v
- read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
- read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
- read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
- read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v
- read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
- read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v
-
- link_design user_project_wrapper
- set tcell [llength [get_cell -hier *]]
- set tregs [llength [all_registers]]
- puts "user_project_wrapper :: $tcell :: $tregs "
+ #link_design user_project_wrapper
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "user_project_wrapper :: $tcell :: $tregs "
diff --git a/verilog/dv/arduino_arrays/arduino_arrays_tb.v b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
index b195e2e..5e96037 100644
--- a/verilog/dv/arduino_arrays/arduino_arrays_tb.v
+++ b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
@@ -18,22 +18,23 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
//// Digital core. ////
+//// This test bench to valid Arduino example: ////
+//// <example><05.control><Arrays> ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -193,7 +194,7 @@
repeat (2) @(posedge clock);
#1;
- // Remove WB and SPI Reset, Keep SDARM and CORE under Reset
+ // Remove WB and SPI Reset and CORE under Reset
wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
// QSPI SRAM:CS#2 Switch to QSPI Mode
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp b/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp
index 07a49d4..a2d7001 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp
@@ -1,5 +1,4 @@
#include <Arduino.h>
-#line 1 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
/*
ASCII table
@@ -21,11 +20,8 @@
https://www.arduino.cc/en/Tutorial/BuiltInExamples/ASCIITable
*/
-#line 22 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
void setup();
-#line 39 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
void loop();
-#line 22 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
// first visible ASCIIcharacter '!' is number 33:
int thisByte = 33;
void setup() {
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
index af4e082..9f2be69 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -18,30 +18,23 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
//// Digital core. ////
-//// 1. User Risc core is booted using compiled code of ////
-//// user_risc_boot.c ////
-//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
-//// 3. After successful boot, Risc core will write signature ////
-//// in to user register from 0x1003_0058 to 0x1003_006C ////
-//// 4. Through the External Wishbone Interface we read back ////
-//// from 0x3003_0058 to 0x3003_006C ////
-//// and validate the user register to declared pass fail ////
+//// This test bench to valid Arduino example: ////
+//// <example><04.Communication><ASCIITable> ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
index 051b224..f440419 100644
--- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
+++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -18,30 +18,23 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
//// Digital core. ////
-//// 1. User Risc core is booted using compiled code of ////
-//// user_risc_boot.c ////
-//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
-//// 3. After successful boot, Risc core will write signature ////
-//// in to user register from 0x1003_0058 to 0x1003_006C ////
-//// 4. Through the External Wishbone Interface we read back ////
-//// from 0x3003_0058 to 0x3003_006C ////
-//// and validate the user register to declared pass fail ////
+//// This test bench to valid Arduino example: ////
+//// ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
index f0cf862..eda8c5a 100644
--- a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
+++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
@@ -18,30 +18,24 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
//// Digital core. ////
-//// 1. User Risc core is booted using compiled code of ////
-//// user_risc_boot.c ////
-//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
-//// 3. After successful boot, Risc core will write signature ////
-//// in to user register from 0x1003_0058 to 0x1003_006C ////
-//// 4. Through the External Wishbone Interface we read back ////
-//// from 0x3003_0058 to 0x3003_006C ////
-//// and validate the user register to declared pass fail ////
+//// This test bench to valid Arduino example: ////
+//// <example><04.Communication><MultiSerial> ////
+//// ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
index c435c40..fb25cf0 100644
--- a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
+++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
@@ -18,30 +18,22 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
//// Digital core. ////
-//// 1. User Risc core is booted using compiled code of ////
-//// user_risc_boot.c ////
-//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
-//// 3. After successful boot, Risc core will write signature ////
-//// in to user register from 0x1003_0058 to 0x1003_006C ////
-//// 4. Through the External Wishbone Interface we read back ////
-//// from 0x3003_0058 to 0x3003_006C ////
-//// and validate the user register to declared pass fail ////
+//// This test bench to valid Arduino example: ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile
index 3a63981..7bcd2b7 100644
--- a/verilog/dv/uart_master/Makefile
+++ b/verilog/dv/uart_master/Makefile
@@ -23,7 +23,7 @@
DESIGNS?=../../..
CONFIG = caravel_user_project
-TOOLS?=/opt/riscv64i/
+TOOLS?=/opt/riscv32i/
########################################################
#include $(MCW_ROOT)/verilog/dv/make/env.makefile
@@ -52,7 +52,7 @@
#######################################################################
export GCC_PATH?= $(TOOLS)/bin
-export GCC_PREFIX?= riscv64-unknown-linux-gnu
+export GCC_PREFIX?= riscv32-unknown-linux-gnu
############## USER SPECIFIC DEFINE ##################
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index e0f8219..e41e0d2 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -146,7 +146,7 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h01);
// Enable I2C Multi Functional Ports
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h4000);
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h8000);
// Remove i2m reset
wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h010);
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
index c8e3f5c..7a50429 100644
--- a/verilog/dv/user_sspi/user_sspi_tb.v
+++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -456,7 +456,7 @@
`endif
//------------------------------------------------------
-// Integrate the Serial flash with qurd support to
+// Integrate the Serial flash with quad support to
// user core using the gpio pads
// ----------------------------------------------------
wire flash_io1;
