bus repeater south addition
diff --git a/Makefile b/Makefile
index 2d433bf..a54eedb 100644
--- a/Makefile
+++ b/Makefile
@@ -324,6 +324,6 @@
.PHONY: caravel-sta
caravel-sta: ./env/spef-mapping.tcl
@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ
-# @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
-# @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow
+ @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
+ @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow
@echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
diff --git a/env/spef-mapping.tcl b/env/spef-mapping.tcl
new file mode 100644
index 0000000..ce5a1ec
--- /dev/null
+++ b/env/spef-mapping.tcl
@@ -0,0 +1,12 @@
+set spef_mapping(mprj/u_4x8bit_dac) "$::env(PROJECT_ROOT)/signoff/not-found/dac_top.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_aes) "$::env(PROJECT_ROOT)/signoff/aes_top/openlane-signoff/spef/aes_top.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_fpu) "$::env(PROJECT_ROOT)/signoff/fpu_wrapper/openlane-signoff/spef/fpu_wrapper.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_intercon) "$::env(PROJECT_ROOT)/signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_pinmux) "$::env(PROJECT_ROOT)/signoff/pinmux_top/openlane-signoff/spef/pinmux_top.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_pll) "$::env(PROJECT_ROOT)/signoff/dg_pll/openlane-signoff/spef/dg_pll.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_qspi_master) "$::env(PROJECT_ROOT)/signoff/qspim_top/openlane-signoff/spef/qspim_top.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/\u_riscv_top.i_core_top_0) "$::env(PROJECT_ROOT)/signoff/ycr_core_top/openlane-signoff/spef/ycr_core_top.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/\u_riscv_top.u_connect) "$::env(PROJECT_ROOT)/signoff/ycr_iconnect/openlane-signoff/spef/ycr_iconnect.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/\u_riscv_top.u_intf) "$::env(PROJECT_ROOT)/signoff/ycr_intf/openlane-signoff/spef/ycr_intf.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_uart_i2c_usb_spi) "$::env(PROJECT_ROOT)/signoff/uart_i2c_usb_spi_top/openlane-signoff/spef/uart_i2c_usb_spi_top.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_wb_host) "$::env(PROJECT_ROOT)/signoff/wb_host/openlane-signoff/spef/wb_host.$::env(RCX_CORNER).spef"
diff --git a/gds/aes_top.gds.gz b/gds/aes_top.gds.gz
deleted file mode 100644
index cbd7222..0000000
--- a/gds/aes_top.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/dac_top.gds.gz b/gds/dac_top.gds.gz
deleted file mode 100644
index 2dbfa41..0000000
--- a/gds/dac_top.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/dg_pll.gds.gz b/gds/dg_pll.gds.gz
deleted file mode 100644
index d290c13..0000000
--- a/gds/dg_pll.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/fpu_wrapper.gds.gz b/gds/fpu_wrapper.gds.gz
deleted file mode 100644
index eae5ad0..0000000
--- a/gds/fpu_wrapper.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/pinmux_top.gds.gz b/gds/pinmux_top.gds.gz
deleted file mode 100644
index 8770f2c..0000000
--- a/gds/pinmux_top.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/qspim_top.gds.gz b/gds/qspim_top.gds.gz
deleted file mode 100644
index 97eda45..0000000
--- a/gds/qspim_top.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/uart_i2c_usb_spi_top.gds.gz b/gds/uart_i2c_usb_spi_top.gds.gz
deleted file mode 100644
index 127d77d..0000000
--- a/gds/uart_i2c_usb_spi_top.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 8ee6bed..3a26931 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/gds/wb_host.gds.gz b/gds/wb_host.gds.gz
deleted file mode 100644
index 545827a..0000000
--- a/gds/wb_host.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/wb_interconnect.gds.gz b/gds/wb_interconnect.gds.gz
deleted file mode 100644
index 4215a7d..0000000
--- a/gds/wb_interconnect.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/ycr_core_top.gds.gz b/gds/ycr_core_top.gds.gz
deleted file mode 100644
index cc2e1d3..0000000
--- a/gds/ycr_core_top.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/ycr_iconnect.gds.gz b/gds/ycr_iconnect.gds.gz
deleted file mode 100644
index bf35859..0000000
--- a/gds/ycr_iconnect.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/ycr_intf.gds.gz b/gds/ycr_intf.gds.gz
deleted file mode 100644
index 5d1e7e0..0000000
--- a/gds/ycr_intf.gds.gz
+++ /dev/null
Binary files differ
diff --git a/lef/aes_top.lef.gz b/lef/aes_top.lef.gz
deleted file mode 100644
index 31232e1..0000000
--- a/lef/aes_top.lef.gz
+++ /dev/null
Binary files differ
diff --git a/lef/dac_top.lef.gz b/lef/dac_top.lef.gz
deleted file mode 100644
index 90d033e..0000000
--- a/lef/dac_top.lef.gz
+++ /dev/null
Binary files differ
diff --git a/lef/dg_pll.lef.gz b/lef/dg_pll.lef.gz
deleted file mode 100644
index fcbd319..0000000
--- a/lef/dg_pll.lef.gz
+++ /dev/null
Binary files differ
diff --git a/lef/fpu_wrapper.lef.gz b/lef/fpu_wrapper.lef.gz
deleted file mode 100644
index f0dbe37..0000000
--- a/lef/fpu_wrapper.lef.gz
+++ /dev/null
Binary files differ
diff --git a/lef/pinmux_top.lef.gz b/lef/pinmux_top.lef.gz
deleted file mode 100644
index bc5b0ce..0000000
--- a/lef/pinmux_top.lef.gz
+++ /dev/null
Binary files differ
diff --git a/lef/qspim_top.lef.gz b/lef/qspim_top.lef.gz
deleted file mode 100644
index 5e80b24..0000000
--- a/lef/qspim_top.lef.gz
+++ /dev/null
Binary files differ
diff --git a/lef/uart_i2c_usb_spi_top.lef.gz b/lef/uart_i2c_usb_spi_top.lef.gz
deleted file mode 100644
index b1d98bd..0000000
--- a/lef/uart_i2c_usb_spi_top.lef.gz
+++ /dev/null
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 76e768e..56b6bca 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/lef/wb_host.lef.gz b/lef/wb_host.lef.gz
deleted file mode 100644
index c319c4f..0000000
--- a/lef/wb_host.lef.gz
+++ /dev/null
Binary files differ
diff --git a/lef/wb_interconnect.lef.gz b/lef/wb_interconnect.lef.gz
deleted file mode 100644
index 9d38f02..0000000
--- a/lef/wb_interconnect.lef.gz
+++ /dev/null
Binary files differ
diff --git a/lef/ycr_core_top.lef.gz b/lef/ycr_core_top.lef.gz
deleted file mode 100644
index ca37a90..0000000
--- a/lef/ycr_core_top.lef.gz
+++ /dev/null
Binary files differ
diff --git a/lef/ycr_iconnect.lef.gz b/lef/ycr_iconnect.lef.gz
deleted file mode 100644
index 8160c33..0000000
--- a/lef/ycr_iconnect.lef.gz
+++ /dev/null
Binary files differ
diff --git a/lef/ycr_intf.lef.gz b/lef/ycr_intf.lef.gz
deleted file mode 100644
index a9e1e1d..0000000
--- a/lef/ycr_intf.lef.gz
+++ /dev/null
Binary files differ
diff --git a/openlane/aes_top/pin_order.cfg b/openlane/aes_top/pin_order.cfg
index 1d8dedd..847e469 100644
--- a/openlane/aes_top/pin_order.cfg
+++ b/openlane/aes_top/pin_order.cfg
@@ -3,7 +3,7 @@
#MANUAL_PLACE
-#W
+#E
mclk 0100 0 2
rst_n
diff --git a/openlane/bus_rep_south/config.tcl b/openlane/bus_rep_south/config.tcl
new file mode 100755
index 0000000..bcfd99c
--- /dev/null
+++ b/openlane/bus_rep_south/config.tcl
@@ -0,0 +1,127 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) bus_rep_south
+
+
+set ::env(DESIGN_IS_CORE) "1"
+set ::env(FP_PDN_CORE_RING) {1}
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_NET) ""
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_south.sv \
+ "
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=124 "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2030 50"
+
+#set ::env(GRT_OBS) "met4 0 0 300 1725"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.20"
+set ::env(CELL_PAD) "8"
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+## CTS
+set ::env(CLOCK_TREE_SYNTH) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"
+
+## Routing
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+#set ::env(GLB_RT_MAXLAYER) 3
+set ::env(RT_MAX_LAYER) {met3}
+set ::env(FP_PDN_LOWER_LAYER) {met2}
+set ::env(FP_PDN_UPPER_LAYER) {met3}
+
+set ::env(FP_IO_HLAYER) {met2}
+set ::env(FP_IO_VLAYER) {met1}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+
+set ::env(ECO_ENABLE) {0}
+#set ::env(CURRENT_STEP) "synthesis"
+#set ::env(LAST_STEP) "parasitics_sta"
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_south/interactive.tcl b/openlane/bus_rep_south/interactive.tcl
new file mode 100755
index 0000000..a96ddb6
--- /dev/null
+++ b/openlane/bus_rep_south/interactive.tcl
@@ -0,0 +1,355 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+
+proc run_placement_step {args} {
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+}
+
+proc run_routing_step {args} {
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ if { $::env(ECO_ENABLE) == 0 } {
+ run_routing
+ }
+}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+ run_parasitics_sta
+ }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_irdrop_report_step {args} {
+ if { $::env(RUN_IRDROP_REPORT) } {
+ run_irdrop_report
+ }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
+}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
+proc run_post_run_hooks {} {
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
+}
+
+proc run_magic_drc_batch {args} {
+ set options {
+ {-magicrc optional}
+ {-tech optional}
+ {-report required}
+ {-design required}
+ {-gds required}
+ }
+ set flags {}
+ parse_key_args "run_magic_drc_batch" args arg_values $options flags_mag $flags
+ if { [info exists arg_values(-magicrc)] } {
+ set magicrc [file normalize $arg_values(-magicrc)]
+ }
+ if { [info exists arg_values(-tech)] } {
+ set ::env(TECH) [file normalize $arg_values(-tech)]
+ }
+ set ::env(GDS_INPUT) [file normalize $arg_values(-gds)]
+ set ::env(REPORT_OUTPUT) [file normalize $arg_values(-report)]
+ set ::env(DESIGN_NAME) $arg_values(-design)
+
+ if { [info exists magicrc] } {
+ exec magic \
+ -noconsole \
+ -dnull \
+ -rcfile $magicrc \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ } else {
+ exec magic \
+ -noconsole \
+ -dnull \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ }
+}
+
+proc run_lvs_batch {args} {
+ # runs device level lvs on -gds/CURRENT_GDS and -net/CURRENT_NETLIST
+ # extracts gds only if EXT_NETLIST does not exist
+ set options {
+ {-design required}
+ {-gds optional}
+ {-net optional}
+ }
+ set flags {}
+ parse_key_args "run_lvs_batch" args arg_values $options flags_lvs $flags -no_consume
+
+ prep {*}$args
+
+ if { [info exists arg_values(-gds)] } {
+ set ::env(CURRENT_GDS) [file normalize $arg_values(-gds)]
+ } else {
+ set ::env(CURRENT_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).gds
+ }
+ if { [info exists arg_values(-net)] } {
+ set ::env(CURRENT_NETLIST) [file normalize $arg_values(-net)]
+ }
+
+ assert_files_exist "$::env(CURRENT_GDS) $::env(CURRENT_NETLIST)"
+
+ set ::env(MAGIC_EXT_USE_GDS) 1
+ set ::env(EXT_NETLIST) $::env(signoff_results)/$::env(DESIGN_NAME).gds.spice
+ if { [file exists $::env(EXT_NETLIST)] } {
+ puts_warn "The file $::env(EXT_NETLIST) will be used. If you would like the file re-exported, please delete it."
+ } else {
+ run_magic_spice_export
+ }
+
+ run_lvs
+}
+
+
+proc run_file {args} {
+ set ::env(TCLLIBPATH) $::auto_path
+ exec tclsh {*}$args >&@stdout
+}
+
+
+
+proc run_flow {args} {
+ set options {
+ {-design optional}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+ # signal trap SIGINT save_state;
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ load_overrides $arg_values(-override_env)
+ }
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 1
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+ set steps [dict create \
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "irdrop" "run_irdrop_report_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
+ ]
+
+ if { [info exists arg_values(-from) ]} {
+ puts_info "Starting flow at $arg_values(-from)..."
+ set ::env(CURRENT_STEP) $arg_values(-from)
+ } elseif { [info exists ::env(CURRENT_STEP) ] } {
+ puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+ } else {
+ set ::env(CURRENT_STEP) "synthesis"
+ }
+ #Dinesh-A: Addition for LAST_STEP
+ if { [info exists arg_values(-to) ]} {
+ puts_info "Last flow Will be at $arg_values(-to)..."
+ set ::env(LAST_STEP) $arg_values(-to)
+ } elseif { [info exists ::env(LAST_STEP) ] } {
+ puts_info "Last flow Will be at $::env(LAST_STEP)..."
+ } else {
+ set ::env(LAST_STEP) "cvc"
+ }
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+ set_if_unset arg_values(-to) $::env(LAST_STEP)
+
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ # Saves to <RUN_DIR>/results/final
+ save_final_views
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/bus_rep_south/pdn.tcl b/openlane/bus_rep_south/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/bus_rep_south/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+ name grid
+ rails {
+ met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+ }
+ straps {
+ met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+ met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+ }
+ connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+ power_pins "VPWR"
+ ground_pins "VGND"
+ blockages "li1 met1 met2 met3 met4"
+ straps {
+ }
+ connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/bus_rep_south/pin_order.cfg b/openlane/bus_rep_south/pin_order.cfg
new file mode 100644
index 0000000..74cee02
--- /dev/null
+++ b/openlane/bus_rep_south/pin_order.cfg
@@ -0,0 +1,258 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#N
+ch_out\[105\] 1730 0 2
+ch_out\[104\]
+ch_in\[103\]
+ch_out\[102\]
+ch_out\[101\]
+ch_out\[100\]
+ch_out\[99\]
+ch_out\[98\]
+ch_in\[97\]
+ch_out\[96\]
+ch_out\[95\]
+ch_out\[94\]
+ch_in\[93\]
+ch_out\[92\]
+ch_out\[91\]
+ch_out\[90\]
+ch_in\[89\]
+ch_out\[88\]
+ch_out\[87\]
+ch_out\[86\]
+ch_in\[85\]
+ch_out\[84\]
+ch_out\[83\]
+ch_out\[82\]
+ch_in\[81\]
+ch_out\[80\]
+ch_out\[79\]
+ch_in\[78\]
+ch_out\[77\]
+ch_out\[76\]
+ch_in\[75\]
+ch_out\[74\]
+ch_out\[73\]
+ch_in\[72\]
+ch_out\[71\]
+ch_out\[70\]
+ch_in\[69\]
+ch_out\[68\]
+ch_out\[67\]
+ch_in\[66\]
+ch_out\[65\]
+ch_out\[64\]
+ch_in\[63\]
+ch_out\[62\]
+ch_out\[61\]
+ch_in\[60\]
+ch_out\[59\]
+ch_out\[58\]
+ch_in\[57\]
+ch_out\[56\]
+ch_out\[55\]
+ch_in\[54\]
+ch_out\[53\]
+ch_out\[52\]
+ch_in\[51\]
+ch_out\[50\]
+ch_out\[49\]
+ch_in\[48\]
+ch_out\[47\]
+ch_out\[46\]
+ch_in\[45\]
+ch_out\[44\]
+ch_out\[43\]
+ch_in\[42\]
+ch_out\[41\]
+ch_out\[40\]
+ch_in\[39\]
+ch_out\[38\]
+ch_out\[37\]
+ch_in\[36\]
+ch_out\[35\]
+ch_out\[34\]
+ch_in\[33\]
+ch_out\[32\]
+ch_out\[31\]
+ch_in\[30\]
+ch_out\[29\]
+ch_out\[28\]
+ch_in\[27\]
+ch_out\[26\]
+ch_out\[25\]
+ch_in\[24\]
+ch_out\[23\]
+ch_out\[22\]
+ch_in\[21\]
+ch_out\[20\]
+ch_out\[19\]
+ch_in\[18\]
+ch_out\[17\]
+ch_out\[16\]
+ch_in\[15\]
+ch_out\[14\]
+ch_out\[13\]
+ch_in\[12\]
+ch_out\[11\]
+ch_out\[10\]
+ch_in\[9\]
+ch_out\[8\]
+ch_out\[7\]
+ch_in\[6\]
+ch_out\[5\]
+ch_out\[4\]
+ch_in\[3\]
+ch_out\[2\]
+ch_out\[1\]
+ch_in\[0\]
+
+ch_out\[123\] 1980 0 2
+ch_out\[122\]
+ch_out\[121\]
+ch_out\[120\]
+ch_out\[119\]
+ch_out\[118\]
+ch_out\[117\]
+ch_out\[116\]
+ch_out\[115\]
+ch_out\[114\]
+ch_out\[113\]
+ch_out\[112\]
+ch_out\[111\]
+ch_out\[110\]
+ch_out\[109\]
+ch_out\[108\]
+ch_out\[107\]
+ch_out\[106\]
+
+
+#S
+ch_in\[105\] 0 0 16
+ch_in\[104\]
+ch_out\[103\]
+ch_in\[102\]
+ch_in\[101\]
+ch_in\[100\]
+ch_in\[99\]
+ch_in\[98\]
+ch_out\[97\]
+ch_in\[96\]
+ch_in\[95\]
+ch_in\[94\]
+ch_out\[93\]
+ch_in\[92\]
+ch_in\[91\]
+ch_in\[90\]
+ch_out\[89\]
+ch_in\[88\]
+ch_in\[87\]
+ch_in\[86\]
+ch_out\[85\]
+ch_in\[84\]
+ch_in\[83\]
+ch_in\[82\]
+ch_out\[81\]
+ch_in\[80\]
+ch_in\[79\]
+ch_out\[78\]
+ch_in\[77\]
+ch_in\[76\]
+ch_out\[75\]
+ch_in\[74\]
+ch_in\[73\]
+ch_out\[72\]
+ch_in\[71\]
+ch_in\[70\]
+ch_out\[69\]
+ch_in\[68\]
+ch_in\[67\]
+ch_out\[66\]
+ch_in\[65\]
+ch_in\[64\]
+ch_out\[63\]
+ch_in\[62\]
+ch_in\[61\]
+ch_out\[60\]
+ch_in\[59\]
+ch_in\[58\]
+ch_out\[57\]
+ch_in\[56\]
+ch_in\[55\]
+ch_out\[54\]
+ch_in\[53\]
+ch_in\[52\]
+ch_out\[51\]
+ch_in\[50\]
+ch_in\[49\]
+ch_out\[48\]
+ch_in\[47\]
+ch_in\[46\]
+ch_out\[45\]
+ch_in\[44\]
+ch_in\[43\]
+ch_out\[42\]
+ch_in\[41\]
+ch_in\[40\]
+ch_out\[39\]
+ch_in\[38\]
+ch_in\[37\]
+ch_out\[36\]
+ch_in\[35\]
+ch_in\[34\]
+ch_out\[33\]
+ch_in\[32\]
+ch_in\[31\]
+ch_out\[30\]
+ch_in\[29\]
+ch_in\[28\]
+ch_out\[27\]
+ch_in\[26\]
+ch_in\[25\]
+ch_out\[24\]
+ch_in\[23\]
+ch_in\[22\]
+ch_out\[21\]
+ch_in\[20\]
+ch_in\[19\]
+ch_out\[18\]
+ch_in\[17\]
+ch_in\[16\]
+ch_out\[15\]
+ch_in\[14\]
+ch_in\[13\]
+ch_out\[12\]
+ch_in\[11\]
+ch_in\[10\]
+ch_out\[9\]
+ch_in\[8\]
+ch_in\[7\]
+ch_out\[6\]
+ch_in\[5\]
+ch_in\[4\]
+ch_out\[3\]
+ch_in\[2\]
+ch_in\[1\]
+ch_out\[0\]
+
+ch_in\[123\] 700 0 16
+ch_in\[122\]
+ch_in\[121\]
+ch_in\[120\]
+ch_in\[119\]
+ch_in\[118\]
+ch_in\[117\]
+ch_in\[116\]
+ch_in\[115\]
+ch_in\[114\]
+ch_in\[113\]
+ch_in\[112\]
+ch_in\[111\]
+ch_in\[110\]
+ch_in\[109\]
+ch_in\[108\]
+ch_in\[107\]
+ch_in\[106\]
diff --git a/openlane/fpu_wrapper/pin_order.cfg b/openlane/fpu_wrapper/pin_order.cfg
index 3cf0a29..edb7b03 100644
--- a/openlane/fpu_wrapper/pin_order.cfg
+++ b/openlane/fpu_wrapper/pin_order.cfg
@@ -3,7 +3,7 @@
#MANUAL_PLACE
-#W
+#E
mclk 0100 0 2
rst_n
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index d0e0a8f..3900d26 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -41,7 +41,7 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_top.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_reg.sv \
@@ -141,7 +141,7 @@
#LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {0}
+set ::env(MAGIC_EXT_USE_GDS) {1}
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/openlane/uart_i2c_usb_spi_top/config.tcl b/openlane/uart_i2c_usb_spi_top/config.tcl
index 7576c81..358a009 100644
--- a/openlane/uart_i2c_usb_spi_top/config.tcl
+++ b/openlane/uart_i2c_usb_spi_top/config.tcl
@@ -41,7 +41,7 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
$::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_core.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_cfg.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_rxfsm.sv \
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 756c6da..26d4cc6 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -74,10 +74,11 @@
$::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \
$::env(DESIGN_DIR)/../../verilog/gl/ycr_iconnect.v \
$::env(DESIGN_DIR)/../../verilog/gl/dg_pll.v \
- $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
$::env(DESIGN_DIR)/../../verilog/gl/dac_top.v \
$::env(DESIGN_DIR)/../../verilog/gl/aes_top.v \
$::env(DESIGN_DIR)/../../verilog/gl/fpu_wrapper.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_south.v \
"
set ::env(EXTRA_LEFS) "\
@@ -94,6 +95,7 @@
$lef_root/dac_top.lef \
$lef_root/aes_top.lef \
$lef_root/fpu_wrapper.lef \
+ $lef_root/bus_rep_south.lef \
"
set ::env(EXTRA_GDS_FILES) "\
@@ -107,8 +109,10 @@
$gds_root/ycr_iconnect.gds \
$gds_root/dg_pll.gds \
$gds_root/dac_top.gds \
+ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
$gds_root/aes_top.gds \
$gds_root/fpu_wrapper.gds \
+ $gds_root/bus_rep_south.gds \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -120,12 +124,19 @@
## Internal Macros
### Macro PDN Connections
+### Follow checks are temp masked due to PDNGEN issue in
+### handling SRAM Power Strip in MET3, This issue occured due
+### Enabling MET3 to MET4 connectivity to handle power hook up
+### for bus repeater macro
+set ::env(FP_PDN_CHECK_NODES) 1
+set ::env(FP_PDN_IRDROP) "1"
+set ::env(RUN_IRDROP_REPORT) "1"
+####################
set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "0"
-set ::env(FP_PDN_CHECK_NODES) 1
set ::env(FP_PDN_ENABLE_RAILS) 0
-set ::env(FP_PDN_IRDROP) "1"
+set ::env(FP_PDN_IRDROP) "0"
set ::env(FP_PDN_HORIZONTAL_HALO) "10"
set ::env(FP_PDN_VERTICAL_HALO) "10"
set ::env(FP_PDN_VOFFSET) "5"
@@ -179,7 +190,8 @@
u_riscv_top.u_intf vccd1 vssd1 vccd1 vssd1,\
u_4x8bit_dac vdda1 vssa1 vccd1 vssd1,\
u_aes vdda1 vssa1 vccd1 vssd1,\
- u_fpu vdda1 vssa1 vccd1 vssd1
+ u_fpu vdda1 vssa1 vccd1 vssd1,\
+ u_rp_south vdda1 vssa1 vccd1 vssd1
"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index e7437d8..9169bcd 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,18 +1,19 @@
-u_4x8bit_dac 1850 2500 N
-u_qspi_master 2250 450 N
-u_uart_i2c_usb_spi 2250 1100 N
-u_pinmux 2250 2000 N
-u_pll 2500 3028 N
+u_4x8bit_dac 1850 2500 N
+u_qspi_master 2250 450 N
+u_uart_i2c_usb_spi 2250 1100 N
+u_pinmux 2250 2000 N
+u_pll 2500 3028 N
-u_fpu 1000 2600 N
-u_aes 50 2600 N
-u_riscv_top.i_core_top_0 50 1400 N
-u_riscv_top.u_connect 740 1400 N
-u_riscv_top.u_intf 950 650 N
-u_dcache_2kb 150 130 N
-u_icache_2kb 950 130 N
-u_tsram0_2kb 150 750 N
+u_fpu 1000 2600 N
+u_aes 50 2600 N
+u_riscv_top.i_core_top_0 50 1400 N
+u_riscv_top.u_connect 740 1400 N
+u_riscv_top.u_intf 950 650 N
+u_dcache_2kb 150 130 N
+u_icache_2kb 950 130 N
+u_tsram0_2kb 150 750 N
-u_intercon 1850 650 N
-u_wb_host 1750 100 N
+u_intercon 1850 650 N
+u_wb_host 1750 100 N
+u_rp_south 20 20 N
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index b2a2b42..ace04ab 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -150,14 +150,32 @@
-spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
-core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
}
+##################################
+# Common Macro Power Hook Up
+# Power Connect met-4 to met-5
+##################################
define_pdn_grid \
-macro \
- -default \
- -name macro \
+ -name macro_1 \
+ -instances "u_pll u_intercon u_pinmux u_qspi_master u_tsram0_2kb u_icache_2kb u_dcache_2kb u_uart_i2c_usb_spi u_wb_host u_riscv_top.i_core_top_0 u_riscv_top.u_connect u_riscv_top.u_intf u_4x8bit_dac u_aes u_fpu" \
-starts_with POWER \
-halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
add_pdn_connect \
- -grid macro \
+ -grid macro_1 \
-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+
+##################################
+# u_rp_south Power Hook Up
+# Power connect met-3 to met-4
+##################################
+
+define_pdn_grid \
+ -macro \
+ -name macro_2 \
+ -instances "u_rp_south" \
+ -starts_with POWER \
+ -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+
+add_pdn_connect -grid macro_2 -layers "met3 met4"
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 407a338..48a791b 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -42,7 +42,7 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
$::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wb_host.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wbh_reset_fsm.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wbh_reg.sv \
@@ -85,7 +85,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 425"
+set ::env(DIE_AREA) "0 0 425 425"
set ::env(GRT_OBS) " \
met4 0 0 400 425"
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 8c93e59..8ac589d 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -3,12 +3,6 @@
#MANUAL_PLACE
-#W
-
-cpu_clk 0100 0 2
-
-
-
#S
user_clock2 0000 0 2
user_clock1
@@ -158,16 +152,8 @@
#N
-cfg_clk_skew_ctrl2\[31\] 0000 0 2
-cfg_clk_skew_ctrl2\[30\]
-cfg_clk_skew_ctrl2\[29\]
-cfg_clk_skew_ctrl2\[28\]
-cfg_clk_skew_ctrl2\[27\]
-cfg_clk_skew_ctrl2\[26\]
-cfg_clk_skew_ctrl2\[25\]
-cfg_clk_skew_ctrl2\[24\]
-cfg_clk_skew_ctrl1\[31\]
+cfg_clk_skew_ctrl1\[31\] 0000 0 2
cfg_clk_skew_ctrl1\[30\]
cfg_clk_skew_ctrl1\[29\]
cfg_clk_skew_ctrl1\[28\]
@@ -181,7 +167,9 @@
cfg_clk_skew_ctrl1\[4\]
cfg_cska_wh\[0\]
-wbd_int_rst_n 0100 0 2
+cpu_clk 0100 0 2
+
+wbd_int_rst_n 0120 0 2
cfg_clk_skew_ctrl2\[23\]
cfg_clk_skew_ctrl2\[22\]
cfg_clk_skew_ctrl2\[21\]
@@ -347,7 +335,16 @@
wbs_cyc_o
-strap_sticky\[31\] 325 0 2
+cfg_clk_skew_ctrl2\[31\] 325 0 2
+cfg_clk_skew_ctrl2\[30\]
+cfg_clk_skew_ctrl2\[29\]
+cfg_clk_skew_ctrl2\[28\]
+cfg_clk_skew_ctrl2\[27\]
+cfg_clk_skew_ctrl2\[26\]
+cfg_clk_skew_ctrl2\[25\]
+cfg_clk_skew_ctrl2\[24\]
+
+strap_sticky\[31\]
strap_sticky\[30\]
strap_sticky\[29\]
strap_sticky\[28\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index e83bae6..a87255c 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -30,6 +30,8 @@
set ::env(CLOCK_NET) "clk_i"
set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
## CTS BUFFER
set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
@@ -41,7 +43,8 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_wbb.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_fifo2.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \
@@ -51,7 +54,7 @@
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=4\
+set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=14\
CH_DATA_WD=154 \
"
@@ -102,7 +105,7 @@
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
-set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "2000"
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500"
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"
@@ -117,7 +120,7 @@
set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
#LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {0}
+set ::env(MAGIC_EXT_USE_GDS) {1}
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 7038097..51bfa57 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -3,7 +3,19 @@
#MANUAL_PLACE
#S
-rst_n 000 0 2
+ch_clk_in\[13\] 000 0 2
+ch_clk_in\[12\]
+ch_clk_in\[11\]
+ch_clk_in\[10\]
+ch_clk_in\[9\]
+ch_clk_in\[8\]
+ch_clk_in\[7\]
+ch_clk_in\[6\]
+ch_clk_in\[5\]
+ch_clk_in\[4\]
+
+
+rst_n 020 0 2
ch_data_in\[43\]
ch_data_in\[42\]
ch_data_in\[41\]
@@ -260,6 +272,7 @@
ch_data_out\[22\]
ch_data_out\[21\]
ch_data_out\[20\]
+ch_clk_out\[4\]
ch_data_out\[3\] 050 0 2
ch_data_out\[2\]
@@ -587,19 +600,34 @@
ch_data_out\[42\]
ch_data_out\[41\]
ch_data_out\[40\]
+ch_clk_out\[9\]
+
ch_data_out\[39\]
ch_data_out\[38\]
ch_data_out\[37\]
ch_data_out\[36\]
+ch_clk_out\[8\]
+
ch_data_out\[35\]
ch_data_out\[34\]
ch_data_out\[33\]
ch_data_out\[32\]
+
+ch_clk_out\[7\]
+
ch_data_out\[31\]
ch_data_out\[30\]
ch_data_out\[29\]
ch_data_out\[28\]
+ch_clk_out\[6\]
+
+ch_data_out\[27\] 750 0 2
+ch_data_out\[26\]
+ch_data_out\[25\]
+ch_data_out\[24\]
+ch_clk_out\[5\]
+
ch_data_out\[76\] 1600 0 2
ch_data_out\[75\]
ch_data_out\[74\]
@@ -634,20 +662,17 @@
ch_data_out\[45\]
ch_data_out\[44\]
-ch_data_out\[27\]
-ch_data_out\[26\]
-ch_data_out\[25\]
-ch_data_out\[24\]
-
-ch_data_out\[153\] 1700 0 2
-ch_data_out\[152\]
-ch_data_out\[151\]
-ch_data_out\[150\]
-
-ch_data_out\[149\]
+ch_data_out\[149\] 1700 0 2
ch_data_out\[148\]
ch_data_out\[147\]
ch_data_out\[146\]
+ch_clk_out\[10\]
+
+ch_data_out\[153\] 1750 0 2
+ch_data_out\[152\]
+ch_data_out\[151\]
+ch_data_out\[150\]
+ch_clk_out\[11\]
#E
ch_data_out\[19\] 0000 0 2
@@ -1064,4 +1089,6 @@
s2_wbd_ack_i
s2_wbd_cyc_o
+ch_clk_out\[12\]
+ch_clk_out\[13\]
diff --git a/openlane/ycr_core_top/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg
index 222f71f..f3daaa8 100644
--- a/openlane/ycr_core_top/pin_order.cfg
+++ b/openlane/ycr_core_top/pin_order.cfg
@@ -1,6 +1,21 @@
#BUS_SORT
#MANUAL_PLACE
#E
+pwrup_rst_n
+rst_n
+
+cfg_ccska\[3\]
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_int
+core_clk_skew
+
+clk
+clk_o
+core_rst_n_o
+core_rdc_qlfy_o
+
core_uid\[1\] 0200 00 2
core_uid\[0\]
imem2core_req_ack_i
@@ -331,19 +346,3 @@
core_irq_soft_i
cpu_rst_n
-#S
-pwrup_rst_n
-rst_n
-
-
-cfg_ccska\[3\]
-cfg_ccska\[2\]
-cfg_ccska\[1\]
-cfg_ccska\[0\]
-core_clk_int
-core_clk_skew
-
-clk
-clk_o
-core_rst_n_o
-core_rdc_qlfy_o
diff --git a/openlane/ycr_iconnect/config.tcl b/openlane/ycr_iconnect/config.tcl
index 0d3f9e8..5aeb2f3 100644
--- a/openlane/ycr_iconnect/config.tcl
+++ b/openlane/ycr_iconnect/config.tcl
@@ -23,7 +23,7 @@
# Timing configuration
set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "core_clk rtc_clk"
+set ::env(CLOCK_PORT) "u_cclk_cts.genblk1.u_mux/X rtc_clk"
set ::env(SYNTH_MAX_FANOUT) 4
diff --git a/openlane/ycr_iconnect/pin_order.cfg b/openlane/ycr_iconnect/pin_order.cfg
index 254fda4..981fcbd 100644
--- a/openlane/ycr_iconnect/pin_order.cfg
+++ b/openlane/ycr_iconnect/pin_order.cfg
@@ -817,6 +817,14 @@
riscv_debug\[0\]
#E
+cfg_ccska\[3\]
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_int
+core_clk_skew
+core_clk
+
core_irq_lines_i\[31\] 850 0 2
core_irq_lines_i\[30\]
core_irq_lines_i\[29\]
@@ -851,13 +859,6 @@
core_irq_lines_i\[0\]
core_irq_soft_i
-cfg_ccska\[3\]
-cfg_ccska\[2\]
-cfg_ccska\[1\]
-cfg_ccska\[0\]
-core_clk_int
-core_clk_skew
-core_clk
rtc_clk
pwrup_rst_n
cpu_intf_rst_n
diff --git a/sdc/caravel.sdc b/sdc/caravel.sdc
new file mode 100644
index 0000000..b548e92
--- /dev/null
+++ b/sdc/caravel.sdc
@@ -0,0 +1,330 @@
+### Caravel Signoff SDC
+### Rev 3
+### Date: 28/10/2022
+### Reference SDC: $CARAVEL_ROOT/signoff/caravel/caravel.sdc
+
+## MASTER CLOCKS
+## Reduce the clock speed from 25ns 40ns
+create_clock -name clk -period 40 [get_ports {clock}]
+
+create_clock -name hkspi_clk -period 100 [get_pins {housekeeping/mgmt_gpio_in[4]} ]
+create_clock -name hk_serial_clk -period 50 [get_pins {housekeeping/serial_clock}]
+create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}]
+# hk_serial_clk period is x2 core clock
+
+### User Project Clocks
+create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clk] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
+create_clock -name int_pll_clock -period 5.0000 [get_pins {mprj/u_pinmux/int_pll_clock}]
+
+create_clock -name wbs_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_reg.u_wbs_ref_clkbuf.u_buf/X}]
+create_clock -name wbs_clk_i -period 12.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
+
+create_clock -name cpu_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_reg.u_cpu_ref_clkbuf.u_buf/X}]
+create_clock -name cpu_clk -period 13.0000 [get_pins {mprj/u_wb_host/cpu_clk}]
+
+create_clock -name rtc_ref_clk -period 50.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}]
+create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_rtc.u_buf/X}]
+
+create_clock -name pll_ref_clk -period 20.0000 [get_pins {mprj/u_pinmux/pll_ref_clk}]
+create_clock -name pll_clk_0 -period 6.0000 [get_pins {mprj/u_pll/ringosc.ibufp01/Y}]
+
+create_clock -name usb_ref_clk -period 5.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
+create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_usb.u_buf/X}]
+create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+create_clock -name dbg_ref_clk -period 12.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}]
+
+set_clock_uncertainty 0.1000 [all_clocks]
+
+set_clock_groups \
+ -name clock_group \
+ -logically_exclusive \
+ -group [get_clocks {wb_clk clk}]\
+ -group [get_clocks {hk_serial_clk}]\
+ -group [get_clocks {hk_serial_load}]\
+ -group [get_clocks {hkspi_clk}]\
+ -group [get_clocks {int_pll_clock}]\
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbs_ref_clk}]\
+ -group [get_clocks {cpu_clk}]\
+ -group [get_clocks {cpu_ref_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {pll_ref_clk}]\
+ -group [get_clocks {pll_clk_0}]\
+ -group [get_clocks {usb_clk}]\
+ -group [get_clocks {uarts0_clk}]\
+ -group [get_clocks {uarts1_clk}]\
+ -group [get_clocks {uartm_clk}]\
+ -group [get_clocks {dbg_ref_clk}]\
+ -group [get_clocks {rtc_ref_clk}]\
+ -comment {Async Clock group}
+
+# clock <-> hk_serial_clk/load no paths
+# future note: CDC stuff
+# clock <-> hkspi_clk no paths with careful methods (clock is off)
+
+set_propagated_clock [all_clocks]
+
+## INPUT/OUTPUT DELAYS
+set input_delay_value 4
+set output_delay_value 4
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {gpio}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[0]}]
+
+#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[1]}]
+
+set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[2]}]
+set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[3]}]
+
+#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[4]}]
+
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[5]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[6]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[7]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[8]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[9]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[10]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[11]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[12]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[13]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[20]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[21]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[22]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[23]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[24]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[25]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[26]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[27]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[28]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[29]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[30]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[31]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[32]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[33]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[34]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[35]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[36]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[37]}]
+
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_csb}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_clk}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1}]
+
+# set_output_delay $output_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[1]}]
+
+set_max_fanout 12 [current_design]
+# synthesis max fanout should be less than 12 (7 maybe)
+
+## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
+set_case_analysis 0 [get_pins housekeeping/_3936_/S]
+set_case_analysis 0 [get_pins housekeeping/_3937_/S]
+
+# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 to be outputs
+
+set_case_analysis 1 [get_pins padframe/*_pad*/DM[2]]
+set_case_analysis 1 [get_pins padframe/*_pad*/DM[1]]
+set_case_analysis 0 [get_pins padframe/*_pad*/DM[0]]
+set_case_analysis 0 [get_pins padframe/*_pad*/SLOW]
+set_case_analysis 0 [get_pins padframe/*_pad*/ANALOG_EN]
+
+# the following pads are set as inputs
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[4]/DM[0]]
+
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[2]/DM[0]]
+
+
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[2]]
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[1]]
+set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]]
+
+#################################################################
+## User Case analysis
+#################################################################
+
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}]
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}]
+
+# clock skew cntrl-2
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}]
+
+#Keept the SRAM clock driving edge at pos edge
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}]
+
+set_case_analysis 1 [get_pins {mprj/u_aes/cfg_cska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_fpu/cfg_cska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[0]}]
+
+## FALSE PATHS (ASYNCHRONOUS INPUTS)
+set_false_path -from [get_ports {resetb}]
+
+## Async USB/I2C Interrupt, Double Sync added inside glbl block
+set_false_path -through [get_pins {mprj/u_pinmux/usb_intr}]
+set_false_path -through [get_pins {mprj/u_pinmux/i2cm_intr}]
+
+## UART RXD is async signal
+set_false_path -through [get_pins {mprj/u_wb_host/uartm_rxd}]
+
+##SPI Slave Interface Signal (SCLK/SSN) are double sync with wb_clk
+set_false_path -through [get_pins {mprj/u_wb_host/sclk}]
+set_false_path -through [get_pins {mprj/u_wb_host/ssn}]
+## SDIN sampled on negedge SCLK
+set_false_path -through [get_pins {mprj/u_wb_host/sdin}]
+
+
+# set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_in[*]]
+# reset_path -from [get_ports mprj_io[4]]
+# reset_path -from [get_ports mprj_io[2]]
+#reset_path is not supported in PT read_sdc ^
+
+set_false_path -from [get_ports mprj_io[0]] -through [get_pins housekeeping/mgmt_gpio_in[0]]
+set_false_path -from [get_ports mprj_io[1]] -through [get_pins housekeeping/mgmt_gpio_in[1]]
+set_false_path -from [get_ports mprj_io[3]] -through [get_pins housekeeping/mgmt_gpio_in[3]]
+set_false_path -from [get_ports mprj_io[5]] -through [get_pins housekeeping/mgmt_gpio_in[5]]
+set_false_path -from [get_ports mprj_io[6]] -through [get_pins housekeeping/mgmt_gpio_in[6]]
+set_false_path -from [get_ports mprj_io[7]] -through [get_pins housekeeping/mgmt_gpio_in[7]]
+set_false_path -from [get_ports mprj_io[8]] -through [get_pins housekeeping/mgmt_gpio_in[8]]
+set_false_path -from [get_ports mprj_io[9]] -through [get_pins housekeeping/mgmt_gpio_in[9]]
+set_false_path -from [get_ports mprj_io[10]] -through [get_pins housekeeping/mgmt_gpio_in[10]]
+set_false_path -from [get_ports mprj_io[11]] -through [get_pins housekeeping/mgmt_gpio_in[11]]
+set_false_path -from [get_ports mprj_io[12]] -through [get_pins housekeeping/mgmt_gpio_in[12]]
+set_false_path -from [get_ports mprj_io[13]] -through [get_pins housekeeping/mgmt_gpio_in[13]]
+set_false_path -from [get_ports mprj_io[14]] -through [get_pins housekeeping/mgmt_gpio_in[14]]
+set_false_path -from [get_ports mprj_io[15]] -through [get_pins housekeeping/mgmt_gpio_in[15]]
+set_false_path -from [get_ports mprj_io[16]] -through [get_pins housekeeping/mgmt_gpio_in[16]]
+set_false_path -from [get_ports mprj_io[17]] -through [get_pins housekeeping/mgmt_gpio_in[17]]
+set_false_path -from [get_ports mprj_io[18]] -through [get_pins housekeeping/mgmt_gpio_in[18]]
+set_false_path -from [get_ports mprj_io[19]] -through [get_pins housekeeping/mgmt_gpio_in[19]]
+set_false_path -from [get_ports mprj_io[20]] -through [get_pins housekeeping/mgmt_gpio_in[20]]
+set_false_path -from [get_ports mprj_io[21]] -through [get_pins housekeeping/mgmt_gpio_in[21]]
+set_false_path -from [get_ports mprj_io[22]] -through [get_pins housekeeping/mgmt_gpio_in[22]]
+set_false_path -from [get_ports mprj_io[23]] -through [get_pins housekeeping/mgmt_gpio_in[23]]
+set_false_path -from [get_ports mprj_io[24]] -through [get_pins housekeeping/mgmt_gpio_in[24]]
+set_false_path -from [get_ports mprj_io[25]] -through [get_pins housekeeping/mgmt_gpio_in[25]]
+set_false_path -from [get_ports mprj_io[26]] -through [get_pins housekeeping/mgmt_gpio_in[26]]
+set_false_path -from [get_ports mprj_io[27]] -through [get_pins housekeeping/mgmt_gpio_in[27]]
+set_false_path -from [get_ports mprj_io[28]] -through [get_pins housekeeping/mgmt_gpio_in[28]]
+set_false_path -from [get_ports mprj_io[29]] -through [get_pins housekeeping/mgmt_gpio_in[29]]
+set_false_path -from [get_ports mprj_io[30]] -through [get_pins housekeeping/mgmt_gpio_in[30]]
+set_false_path -from [get_ports mprj_io[31]] -through [get_pins housekeeping/mgmt_gpio_in[31]]
+set_false_path -from [get_ports mprj_io[32]] -through [get_pins housekeeping/mgmt_gpio_in[32]]
+set_false_path -from [get_ports mprj_io[33]] -through [get_pins housekeeping/mgmt_gpio_in[33]]
+set_false_path -from [get_ports mprj_io[34]] -through [get_pins housekeeping/mgmt_gpio_in[34]]
+set_false_path -from [get_ports mprj_io[35]] -through [get_pins housekeeping/mgmt_gpio_in[35]]
+set_false_path -from [get_ports mprj_io[36]] -through [get_pins housekeeping/mgmt_gpio_in[36]]
+set_false_path -from [get_ports mprj_io[37]] -through [get_pins housekeeping/mgmt_gpio_in[37]]
+
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_out[*]]
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]]
+set_false_path -from [get_ports gpio]
+
+# add loads for output ports (pads)
+set min_cap 5
+set max_cap 10
+puts "\[INFO\]: Cap load range: $min_cap : $max_cap"
+# set_load 10 [all_outputs]
+set_load -min $min_cap [all_outputs]
+set_load -max $max_cap [all_outputs]
+
+#add input transition for the inputs ports (pads)
+# set_input_transition 2 [all_inputs]
+#add exception for power pads as 2ns on them results in max_tran violations (false viol)
+# set_input_transition 2 [remove_from_collection [all_inputs] [get_ports v*]]
+# remove_from_collection is not supported in PT read_sdc ^
+# set_input_transition 2 [all_inputs]
+# set_input_transition 0 [get_ports v*]
+
+set min_in_tran 1
+set max_in_tran 4
+puts "\[INFO\]: Input transition range: $min_in_tran : $max_in_tran"
+set_input_transition -min $min_in_tran [all_inputs]
+set_input_transition -min 0 [get_ports v*]
+set_input_transition -max $max_in_tran [all_inputs]
+set_input_transition -max 0 [get_ports v*]
+
+# check ocv table (not provided) -- maybe try 8%
+set derate 0.0375
+puts "\[INFO\]: Setting derate factor to: [expr $derate * 100] %"
+set_timing_derate -early [expr 1-$derate]
+set_timing_derate -late [expr 1+$derate]
+
+# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
+# apply the constraint to hd cells at the ss corner only
+# if {$::env(PROC_CORNER) == "s"} {
+# set max_tran 1.5
+# set_max_transition $max_tran [get_pins -of_objects [get_cells -filter {ref_name=~sky130_fd_sc_hd*}]]
+# set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
+# set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
+# puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
+# }
+# -filter not supported in PT read_sdc ^
diff --git a/signoff/pinmux_top/OPENLANE_VERSION b/signoff/pinmux_top/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/pinmux_top/OPENLANE_VERSION
+++ b/signoff/pinmux_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/pinmux_top/PDK_SOURCES b/signoff/pinmux_top/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/pinmux_top/PDK_SOURCES
+++ b/signoff/pinmux_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/qspim_top/OPENLANE_VERSION
+++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/qspim_top/PDK_SOURCES
+++ b/signoff/qspim_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/user_project_wrapper/OPENLANE_VERSION
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/user_project_wrapper/PDK_SOURCES
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/ycr_core_top/OPENLANE_VERSION
+++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/ycr_core_top/PDK_SOURCES
+++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/ycr_iconnect/OPENLANE_VERSION b/signoff/ycr_iconnect/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/ycr_iconnect/OPENLANE_VERSION
+++ b/signoff/ycr_iconnect/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/ycr_iconnect/PDK_SOURCES b/signoff/ycr_iconnect/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/ycr_iconnect/PDK_SOURCES
+++ b/signoff/ycr_iconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION
index fabca1a..1234be5 100644
--- a/signoff/ycr_intf/OPENLANE_VERSION
+++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES
index ef91c87..f8d3b3a 100644
--- a/signoff/ycr_intf/PDK_SOURCES
+++ b/signoff/ycr_intf/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
diff --git a/verilog/dv/common/agents/caravel_task.sv b/verilog/dv/common/agents/caravel_task.sv
index 70ff764..3937734 100644
--- a/verilog/dv/common/agents/caravel_task.sv
+++ b/verilog/dv/common/agents/caravel_task.sv
@@ -13,9 +13,9 @@
****/
`ifdef RISC_BOOT // RISCV Based Test case
-parameter bit [15:0] PAD_STRAP = 16'b0000_0001_1011_0000;
+parameter bit [15:0] PAD_STRAP = 16'b0000_0001_1010_0000;
`else
-parameter bit [15:0] PAD_STRAP = 16'b0000_0000_1011_0000;
+parameter bit [15:0] PAD_STRAP = 16'b0000_0000_1010_0000;
`endif
/***********************************************
diff --git a/verilog/dv/common/agents/usb_agents.v b/verilog/dv/common/agents/usb_agents.v
index c266567..4d144d0 100644
--- a/verilog/dv/common/agents/usb_agents.v
+++ b/verilog/dv/common/agents/usb_agents.v
@@ -274,7 +274,7 @@
input [15:0] value;
input [15:0] index;
input [15:0] length;
-output status;
+output[7:0] status;
reg [7:0] status;
integer idx;
begin
diff --git a/verilog/dv/common/bfm/bfm_spim.v b/verilog/dv/common/bfm/bfm_spim.v
index f04f8b9..2bf556f 100644
--- a/verilog/dv/common/bfm/bfm_spim.v
+++ b/verilog/dv/common/bfm/bfm_spim.v
@@ -172,8 +172,7 @@
endtask
// Write 4 Byte
task send_dword;
-input dword;
-reg [31:0] dword;
+input [31:0] dword;
begin
send_word(dword[31:16]);
send_word(dword[15:0]);
@@ -182,8 +181,7 @@
// Write 2 Byte
task send_word;
-input word;
-reg [15:0] word;
+input [15:0] word;
begin
send_byte(word[15:8]);
send_byte(word[7:0]);
@@ -194,8 +192,7 @@
// Write 1 Byte
task send_byte;
-input data;
-reg [7:0] data;
+input [7:0] data;
integer i;
begin
@@ -217,7 +214,7 @@
// READ 4 BYTE
task receive_dword;
-output dword;
+output [31:0] dword;
reg [31:0] dword;
begin
receive_word(dword[31:16]);
@@ -227,7 +224,7 @@
// READ 2 BYTE
task receive_word;
-output word;
+output [15:0] word;
reg [15:0] word;
begin
receive_byte(word[15:8]);
@@ -239,7 +236,7 @@
// READ 1 BYTE
task receive_byte;
-output data;
+output [7:0] data;
reg [7:0] data;
integer i;
begin
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index db9d549..758f0ed 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -165,11 +165,11 @@
## RTL
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DRISC_BOOT -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+ iverilog -g2012 -Ttyp -DFUNCTIONAL -DSIM -DRISC_BOOT -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
else
- iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DRISC_BOOT -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+ iverilog -g2012 -DWFDUMP -Ttyp -DFUNCTIONAL -DRISC_BOOT -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
endif
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 51bde45..ef56ee4 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -18,18 +18,17 @@
//// ////
//// User Risc Core Boot Validation ////
//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscuino.git ////
+//// http://www.opencores.org/cores/riscuino/ ////
//// ////
//// Description ////
-//// 1. User Risc core is booted using compiled code of ////
-//// user_risc_boot.hex ////
-//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
-//// 3. After successful boot, Risc core will write signature////
-//// in to user register from 0x3000_0018 to 0x3000_002C ////
-//// 4. Through the External Wishbone Interface we read back ////
-//// and validate the user register to declared pass fail ////
+//// 1. Strap is set to RISC core auto Boot mode ////
+//// 2. With Reset removal from caravel, User core boot up ////
+//// 3. Risc-V firmware have UART Loop back mode ////
+//// 4. Any UART Data Transmited by testbench will be loop back////
+//// 5. There are 40 Random char are transmited and compared ////
+//// againt received data ////
//// ////
//// To Do: ////
//// nothing ////
@@ -132,9 +131,10 @@
$dumpfile("simx.vcd");
$dumpvars(1,risc_boot_tb);
//$dumpvars(1,risc_boot_tb.u_spi_flash_256mb);
- $dumpvars(2,risc_boot_tb.u_top);
+ //$dumpvars(2,risc_boot_tb.u_top);
$dumpvars(1,risc_boot_tb.u_top.mprj);
$dumpvars(0,risc_boot_tb.u_top.mprj.u_wb_host);
+ $dumpvars(0,risc_boot_tb.u_top.mprj.u_pinmux);
//$dumpvars(0,risc_boot_tb.tb_uart);
//$dumpvars(0,risc_boot_tb.u_user_spiflash);
$display("Waveform Dump started");
@@ -165,7 +165,7 @@
$value$plusargs("risc_core_id=%d", d_risc_id);
- init();
+ init();
uart_data_bit = 2'b11;
uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
@@ -186,7 +186,7 @@
uart_stick_parity, uart_timeout, uart_divisor);
- wait_riscv_boot();
+ wait_riscv_boot();
repeat (50000) @(posedge clock);
for (i=0; i<40; i=i+1)
diff --git a/verilog/dv/uart_master_test2/uart_master_test2_tb.v b/verilog/dv/uart_master_test2/uart_master_test2_tb.v
index 257363e..b757926 100644
--- a/verilog/dv/uart_master_test2/uart_master_test2_tb.v
+++ b/verilog/dv/uart_master_test2/uart_master_test2_tb.v
@@ -19,7 +19,7 @@
`include "uart_agent.v"
`define TB_HEX "uart_master.hex"
-`define TB_TOP uart_master_tb
+`define TB_TOP uart_master_test2
module `TB_TOP;
reg clock;
reg RSTB;
diff --git a/verilog/dv/user_aes_core/user_aes_core_tb.v b/verilog/dv/user_aes_core/user_aes_core_tb.v
index 017a14a..fbb54f7 100644
--- a/verilog/dv/user_aes_core/user_aes_core_tb.v
+++ b/verilog/dv/user_aes_core/user_aes_core_tb.v
@@ -65,7 +65,7 @@
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
`include "uart_agent.v"
-module user_aes_tb;
+module user_aes_core_tb;
parameter real CLK1_PERIOD = 20; // 50Mhz
parameter real CLK2_PERIOD = 2.5;
@@ -128,10 +128,10 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(2, user_aes_tb);
- $dumpvars(0, user_aes_tb.u_top.u_aes);
- $dumpvars(0, user_aes_tb.u_top.u_riscv_top);
- $dumpvars(0, user_aes_tb.u_top.u_pinmux);
+ $dumpvars(2, user_aes_core_tb);
+ $dumpvars(0, user_aes_core_tb.u_top.u_aes);
+ $dumpvars(0, user_aes_core_tb.u_top.u_riscv_top);
+ $dumpvars(0, user_aes_core_tb.u_top.u_pinmux);
end
`endif
diff --git a/verilog/dv/user_fpu_core/user_fpu_core_tb.v b/verilog/dv/user_fpu_core/user_fpu_core_tb.v
index 41b4ffe..e79506e 100644
--- a/verilog/dv/user_fpu_core/user_fpu_core_tb.v
+++ b/verilog/dv/user_fpu_core/user_fpu_core_tb.v
@@ -65,7 +65,10 @@
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
`include "uart_agent.v"
-module user_fpu_tb;
+
+`define TB_HEX "user_fpu_core.hex"
+`define TB_TOP user_fpu_core_tb
+module `TB_TOP;
parameter real CLK1_PERIOD = 20; // 50Mhz
parameter real CLK2_PERIOD = 2.5;
@@ -128,10 +131,10 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(2, user_fpu_tb);
- $dumpvars(0, user_fpu_tb.u_top.u_fpu);
- $dumpvars(0, user_fpu_tb.u_top.u_riscv_top);
- $dumpvars(0, user_fpu_tb.u_top.u_pinmux);
+ $dumpvars(2, `TB_TOP);
+ $dumpvars(0, `TB_TOP.u_top.u_fpu);
+ $dumpvars(0, `TB_TOP.u_top.u_riscv_top);
+ $dumpvars(0, `TB_TOP.u_top.u_pinmux);
end
`endif
@@ -256,7 +259,7 @@
assign io_in[36] = flash_io3;
// Quard flash
- s25fl256s #(.mem_file_name("user_fpu_core.hex"),
+ s25fl256s #(.mem_file_name(`TB_HEX),
.otp_file_name("none"),
.TimingModel("S25FL512SAGMFI010_F_30pF"))
u_spi_flash_256mb (
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index c4b27a9..5b52174 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -68,7 +68,7 @@
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
`include "i2c_slave_model.v"
-module tb_top;
+module user_i2cm_tb;
parameter real CLK1_PERIOD = 20; // 50Mhz
parameter real CLK2_PERIOD = 2.5;
parameter real IPLL_PERIOD = 5.008;
@@ -88,7 +88,7 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(0, tb_top);
+ $dumpvars(0, user_i2cm_tb);
end
`endif
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 25cbfd3..57d6802 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -145,7 +145,7 @@
uart_stick_parity, uart_timeout, uart_divisor);
- tb_master_uart.write_char('\n'); // for uart baud auto detect purpose
+ tb_master_uart.write_char(8'h0A); // for uart baud auto detect purpose - New Line Character \n
//$write ("\n(%t)Response:\n",$time);
flag = 0;
while(flag == 0)
diff --git a/verilog/gl/aes_top.v.gz b/verilog/gl/aes_top.v.gz
deleted file mode 100644
index e7eb9a3..0000000
--- a/verilog/gl/aes_top.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/gl/dac_top.v.gz b/verilog/gl/dac_top.v.gz
deleted file mode 100644
index b1d0048..0000000
--- a/verilog/gl/dac_top.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/gl/dg_pll.v.gz b/verilog/gl/dg_pll.v.gz
deleted file mode 100644
index c14c7b7..0000000
--- a/verilog/gl/dg_pll.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/gl/fpu_wrapper.v.gz b/verilog/gl/fpu_wrapper.v.gz
deleted file mode 100644
index d4c7323..0000000
--- a/verilog/gl/fpu_wrapper.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/gl/pinmux_top.v.gz b/verilog/gl/pinmux_top.v.gz
deleted file mode 100644
index 83ae623..0000000
--- a/verilog/gl/pinmux_top.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/gl/qspim_top.v.gz b/verilog/gl/qspim_top.v.gz
deleted file mode 100644
index f8267cf..0000000
--- a/verilog/gl/qspim_top.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/gl/uart_i2c_usb_spi_top.v.gz b/verilog/gl/uart_i2c_usb_spi_top.v.gz
deleted file mode 100644
index 93b01a5..0000000
--- a/verilog/gl/uart_i2c_usb_spi_top.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 26c4224..d79009f 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
diff --git a/verilog/gl/wb_host.v.gz b/verilog/gl/wb_host.v.gz
deleted file mode 100644
index 5fcfeb0..0000000
--- a/verilog/gl/wb_host.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/gl/wb_interconnect.v.gz b/verilog/gl/wb_interconnect.v.gz
deleted file mode 100644
index c2739a5..0000000
--- a/verilog/gl/wb_interconnect.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/gl/ycr_core_top.v.gz b/verilog/gl/ycr_core_top.v.gz
deleted file mode 100644
index 6f6238d..0000000
--- a/verilog/gl/ycr_core_top.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/gl/ycr_iconnect.v.gz b/verilog/gl/ycr_iconnect.v.gz
deleted file mode 100644
index ec91a6a..0000000
--- a/verilog/gl/ycr_iconnect.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/gl/ycr_intf.v.gz b/verilog/gl/ycr_intf.v.gz
deleted file mode 100644
index 10a3e88..0000000
--- a/verilog/gl/ycr_intf.v.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index c52c530..22e2bc7 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -167,3 +167,4 @@
-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_south.sv
diff --git a/verilog/rtl/bus_rep/bus_rep_south.sv b/verilog/rtl/bus_rep/bus_rep_south.sv
new file mode 100644
index 0000000..32c1521
--- /dev/null
+++ b/verilog/rtl/bus_rep/bus_rep_south.sv
@@ -0,0 +1,38 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+// Bus Repater //
+//////////////////////////////////////////////////////////////////////
+module bus_rep_south #(
+ parameter BUS_REP_WD = 7
+ ) (
+`ifdef USE_POWER_PINS
+ input logic vccd1, // User area 1 1.8V supply
+ input logic vssd1, // User area 1 digital ground
+`endif
+ // Bus repeaters
+ input [BUS_REP_WD-1:0] ch_in,
+ output [BUS_REP_WD-1:0] ch_out
+ );
+
+// channel repeater
+assign ch_out = ch_in;
+
+
+endmodule
+
diff --git a/verilog/rtl/bus_repeater.sv b/verilog/rtl/bus_repeater.sv
new file mode 100644
index 0000000..aa11747
--- /dev/null
+++ b/verilog/rtl/bus_repeater.sv
@@ -0,0 +1,282 @@
+/*********************************************
+ Bus Repeater SOUTH
+**********************************************/
+wire wb_clk_int_i;
+wire wb_rst_int_i ;
+wire wbs_ack_int_o ;
+wire wbs_cyc_int_i ;
+wire wbs_stb_int_i ;
+wire wbs_we_int_i ;
+wire [3:0] wbs_sel_int_i;
+wire [31:0] wbs_adr_int_i;
+wire [31:0] wbs_dat_int_i;
+wire [31:0] wbs_dat_int_o;
+
+wire [17:0] la_data_in_rp;
+
+wire [123:0] ch_in_south = {
+ la_data_in[0],
+ la_data_in[1],
+ la_data_in[2],
+ la_data_in[3],
+ la_data_in[4],
+ la_data_in[5],
+ la_data_in[6],
+ la_data_in[7],
+ la_data_in[8],
+ la_data_in[9],
+ la_data_in[10],
+ la_data_in[11],
+ la_data_in[12],
+ la_data_in[13],
+ la_data_in[14],
+ la_data_in[15],
+ la_data_in[16],
+ la_data_in[17],
+ wb_clk_i , // 105
+ wb_rst_i , //
+ wbs_ack_int_o , // 103
+ wbs_cyc_i ,
+ wbs_stb_i ,
+ wbs_we_i ,
+ wbs_adr_i[0] ,
+ wbs_dat_i[0] ,
+ wbs_dat_int_o[0] , // 97
+ wbs_sel_i[0] ,
+ wbs_adr_i[1] ,
+ wbs_dat_i[1] ,
+ wbs_dat_int_o[1] , // 93
+ wbs_sel_i[1] ,
+ wbs_adr_i[2] ,
+ wbs_dat_i[2] ,
+ wbs_dat_int_o[2] , // 89
+ wbs_sel_i[2] ,
+ wbs_adr_i[3] ,
+ wbs_dat_i[3] ,
+ wbs_dat_int_o[3] , // 85
+ wbs_sel_i[3] ,
+ wbs_adr_i[4] ,
+ wbs_dat_i[4] ,
+ wbs_dat_int_o[4] , // 81
+ wbs_adr_i[5] ,
+ wbs_dat_i[5] ,
+ wbs_dat_int_o[5] , // 78
+ wbs_adr_i[6] ,
+ wbs_dat_i[6] ,
+ wbs_dat_int_o[6] , // 75
+ wbs_adr_i[7] ,
+ wbs_dat_i[7] ,
+ wbs_dat_int_o[7] , // 72
+ wbs_adr_i[8] ,
+ wbs_dat_i[8] ,
+ wbs_dat_int_o[8] , // 69
+ wbs_adr_i[9] ,
+ wbs_dat_i[9] ,
+ wbs_dat_int_o[9] , // 66
+ wbs_adr_i[10] ,
+ wbs_dat_i[10] ,
+ wbs_dat_int_o[10] , // 63
+ wbs_adr_i[11] ,
+ wbs_dat_i[11] ,
+ wbs_dat_int_o[11] , // 60
+ wbs_adr_i[12] ,
+ wbs_dat_i[12] ,
+ wbs_dat_int_o[12] , // 57
+ wbs_adr_i[13] ,
+ wbs_dat_i[13] ,
+ wbs_dat_int_o[13] , // 54
+ wbs_adr_i[14] ,
+ wbs_dat_i[14] ,
+ wbs_dat_int_o[14] , // 51
+ wbs_adr_i[15] ,
+ wbs_dat_i[15] ,
+ wbs_dat_int_o[15] , // 48
+ wbs_adr_i[16] ,
+ wbs_dat_i[16] ,
+ wbs_dat_int_o[16] , // 45
+ wbs_adr_i[17] ,
+ wbs_dat_i[17] ,
+ wbs_dat_int_o[17] , // 42
+ wbs_adr_i[18] ,
+ wbs_dat_i[18] ,
+ wbs_dat_int_o[18] , // 39
+ wbs_adr_i[19] ,
+ wbs_dat_i[19] ,
+ wbs_dat_int_o[19] , // 36
+ wbs_adr_i[20] ,
+ wbs_dat_i[20] ,
+ wbs_dat_int_o[20] , // 33
+ wbs_adr_i[21] ,
+ wbs_dat_i[21] ,
+ wbs_dat_int_o[21] , // 30
+ wbs_adr_i[22] ,
+ wbs_dat_i[22] ,
+ wbs_dat_int_o[22] , // 27
+ wbs_adr_i[23] ,
+ wbs_dat_i[23] ,
+ wbs_dat_int_o[23] , // 24
+ wbs_adr_i[24] ,
+ wbs_dat_i[24] ,
+ wbs_dat_int_o[24] , // 21
+ wbs_adr_i[25] ,
+ wbs_dat_i[25] ,
+ wbs_dat_int_o[25] , // 18
+ wbs_adr_i[26] ,
+ wbs_dat_i[26] ,
+ wbs_dat_int_o[26] , // 15
+ wbs_adr_i[27] ,
+ wbs_dat_i[27] ,
+ wbs_dat_int_o[27] , // 12
+ wbs_adr_i[28] ,
+ wbs_dat_i[28] ,
+ wbs_dat_int_o[28] , // 9
+ wbs_adr_i[29] ,
+ wbs_dat_i[29] ,
+ wbs_dat_int_o[29] , // 6
+ wbs_adr_i[30] ,
+ wbs_dat_i[30] ,
+ wbs_dat_int_o[30] , // 3
+ wbs_adr_i[31] ,
+ wbs_dat_i[31] ,
+ wbs_dat_int_o[31]
+ };
+wire [123:0] ch_out_south ;
+assign {
+ la_data_in_rp[0] ,
+ la_data_in_rp[1] ,
+ la_data_in_rp[2] ,
+ la_data_in_rp[3] ,
+ la_data_in_rp[4] ,
+ la_data_in_rp[5] ,
+ la_data_in_rp[6] ,
+ la_data_in_rp[7] ,
+ la_data_in_rp[8] ,
+ la_data_in_rp[9] ,
+ la_data_in_rp[10] ,
+ la_data_in_rp[11] ,
+ la_data_in_rp[12] ,
+ la_data_in_rp[13] ,
+ la_data_in_rp[14] ,
+ la_data_in_rp[15] ,
+ la_data_in_rp[16] ,
+ la_data_in_rp[17] ,
+ wb_clk_int_i ,
+ wb_rst_int_i ,
+ wbs_ack_o ,
+ wbs_cyc_int_i ,
+ wbs_stb_int_i ,
+ wbs_we_int_i ,
+ wbs_adr_int_i[0] ,
+ wbs_dat_int_i[0] ,
+ wbs_dat_o[0] ,
+ wbs_sel_int_i[0] ,
+ wbs_adr_int_i[1] ,
+ wbs_dat_int_i[1] ,
+ wbs_dat_o[1] ,
+ wbs_sel_int_i[1] ,
+ wbs_adr_int_i[2] ,
+ wbs_dat_int_i[2] ,
+ wbs_dat_o[2] ,
+ wbs_sel_int_i[2] ,
+ wbs_adr_int_i[3] ,
+ wbs_dat_int_i[3] ,
+ wbs_dat_o[3] ,
+ wbs_sel_int_i[3] ,
+ wbs_adr_int_i[4] ,
+ wbs_dat_int_i[4] ,
+ wbs_dat_o[4] ,
+ wbs_adr_int_i[5] ,
+ wbs_dat_int_i[5] ,
+ wbs_dat_o[5] ,
+ wbs_adr_int_i[6] ,
+ wbs_dat_int_i[6] ,
+ wbs_dat_o[6] ,
+ wbs_adr_int_i[7] ,
+ wbs_dat_int_i[7] ,
+ wbs_dat_o[7] ,
+ wbs_adr_int_i[8] ,
+ wbs_dat_int_i[8] ,
+ wbs_dat_o[8] ,
+ wbs_adr_int_i[9] ,
+ wbs_dat_int_i[9] ,
+ wbs_dat_o[9] ,
+ wbs_adr_int_i[10] ,
+ wbs_dat_int_i[10] ,
+ wbs_dat_o[10] ,
+ wbs_adr_int_i[11] ,
+ wbs_dat_int_i[11] ,
+ wbs_dat_o[11] ,
+ wbs_adr_int_i[12] ,
+ wbs_dat_int_i[12] ,
+ wbs_dat_o[12] ,
+ wbs_adr_int_i[13] ,
+ wbs_dat_int_i[13] ,
+ wbs_dat_o[13] ,
+ wbs_adr_int_i[14] ,
+ wbs_dat_int_i[14] ,
+ wbs_dat_o[14] ,
+ wbs_adr_int_i[15] ,
+ wbs_dat_int_i[15] ,
+ wbs_dat_o[15] ,
+ wbs_adr_int_i[16] ,
+ wbs_dat_int_i[16] ,
+ wbs_dat_o[16] ,
+ wbs_adr_int_i[17] ,
+ wbs_dat_int_i[17] ,
+ wbs_dat_o[17] ,
+ wbs_adr_int_i[18] ,
+ wbs_dat_int_i[18] ,
+ wbs_dat_o[18] ,
+ wbs_adr_int_i[19] ,
+ wbs_dat_int_i[19] ,
+ wbs_dat_o[19] ,
+ wbs_adr_int_i[20] ,
+ wbs_dat_int_i[20] ,
+ wbs_dat_o[20] ,
+ wbs_adr_int_i[21] ,
+ wbs_dat_int_i[21] ,
+ wbs_dat_o[21] ,
+ wbs_adr_int_i[22] ,
+ wbs_dat_int_i[22] ,
+ wbs_dat_o[22] ,
+ wbs_adr_int_i[23] ,
+ wbs_dat_int_i[23] ,
+ wbs_dat_o[23] ,
+ wbs_adr_int_i[24] ,
+ wbs_dat_int_i[24] ,
+ wbs_dat_o[24] ,
+ wbs_adr_int_i[25] ,
+ wbs_dat_int_i[25] ,
+ wbs_dat_o[25] ,
+ wbs_adr_int_i[26] ,
+ wbs_dat_int_i[26] ,
+ wbs_dat_o[26] ,
+ wbs_adr_int_i[27] ,
+ wbs_dat_int_i[27] ,
+ wbs_dat_o[27] ,
+ wbs_adr_int_i[28] ,
+ wbs_dat_int_i[28] ,
+ wbs_dat_o[28] ,
+ wbs_adr_int_i[29] ,
+ wbs_dat_int_i[29] ,
+ wbs_dat_o[29] ,
+ wbs_adr_int_i[30] ,
+ wbs_dat_int_i[30] ,
+ wbs_dat_o[30] ,
+ wbs_adr_int_i[31] ,
+ wbs_dat_int_i[31] ,
+ wbs_dat_o[31]
+ } = ch_out_south;
+
+bus_rep_south #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(124)
+`endif
+ ) u_rp_south(
+`ifdef USE_POWER_PINS
+ .vccd1 (vdda1 ),
+ .vssd1 (vssa1 ),
+`endif
+ .ch_in (ch_in_south),
+ .ch_out (ch_out_south)
+ );
diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv
index 26e5cbb..a9c6693 100644
--- a/verilog/rtl/lib/ctech_cells.sv
+++ b/verilog/rtl/lib/ctech_cells.sv
@@ -111,10 +111,12 @@
input logic A,
output logic X);
+wire X1;
`ifndef SYNTHESIS
assign X = A;
`else
- sky130_fd_sc_hd__clkdlybuf4s15_2 u_dly (.X(X),.A(A));
+ sky130_fd_sc_hd__clkbuf_1 u_dly0 (.X(X1),.A(A));
+ sky130_fd_sc_hd__clkbuf_1 u_dly1 (.X(X),.A(X1));
`endif
endmodule
diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim
index ee4d23b..abbea37 160000
--- a/verilog/rtl/qspim
+++ b/verilog/rtl/qspim
@@ -1 +1 @@
-Subproject commit ee4d23bb8a6edf84545f1aa0ba5db083d12440d7
+Subproject commit abbea3730b710e8ee387dad5bcd2242dc10a59e7
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 09fd72f..4104a12 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -290,6 +290,9 @@
//// B. FPU Integration ////
//// 5.8 Nov 20, 2022, Dinesh A ////
//// A. Pinmux - Double Sync added for usb & i2c inter ////
+//// 5.9 Nov 25, 2022, Dinesh A ////
+//// cpu_clk will be feed through wb_interconnect for ////
+//// buffering purpose ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -876,6 +879,19 @@
wire int_pll_clock = pll_clk_out[0];
+//-------------------------------------
+// cpu clock repeater mapping
+//-------------------------------------
+wire [9:0] cpu_clk_rp;
+
+wire [5:0] cpu_clk_rp_risc = cpu_clk_rp[5:0];
+wire cpu_clk_rp_aes = cpu_clk_rp[6];
+wire cpu_clk_rp_fpu = cpu_clk_rp[7];
+wire cpu_clk_rp_pinmux = cpu_clk_rp[8];
+
+
+`include "bus_repeater.sv"
+
/***********************************************
Wishbone HOST
*************************************************/
@@ -885,7 +901,7 @@
.vccd1 (vccd1 ),// User area 1 1.8V supply
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .user_clock1 (wb_clk_i ),
+ .user_clock1 (wb_clk_int_i ),
.user_clock2 (user_clock2 ),
.int_pll_clock (int_pll_clock ),
@@ -905,16 +921,16 @@
.wbd_pll_rst_n (wbd_pll_rst_n ),
// Master Port
- .wbm_rst_i (wb_rst_i ),
- .wbm_clk_i (wb_clk_i ),
- .wbm_cyc_i (wbs_cyc_i ),
- .wbm_stb_i (wbs_stb_i ),
- .wbm_adr_i (wbs_adr_i ),
- .wbm_we_i (wbs_we_i ),
- .wbm_dat_i (wbs_dat_i ),
- .wbm_sel_i (wbs_sel_i ),
- .wbm_dat_o (wbs_dat_o ),
- .wbm_ack_o (wbs_ack_o ),
+ .wbm_rst_i (wb_rst_int_i ),
+ .wbm_clk_i (wb_clk_int_i ),
+ .wbm_cyc_i (wbs_cyc_int_i ),
+ .wbm_stb_i (wbs_stb_int_i ),
+ .wbm_adr_i (wbs_adr_int_i ),
+ .wbm_we_i (wbs_we_int_i ),
+ .wbm_dat_i (wbs_dat_int_i ),
+ .wbm_sel_i (wbs_sel_int_i ),
+ .wbm_dat_o (wbs_dat_int_o ),
+ .wbm_ack_o (wbs_ack_int_o ),
.wbm_err_o ( ),
// Clock Skeq Adjust
@@ -938,7 +954,7 @@
.cfg_clk_skew_ctrl1 (cfg_clk_skew_ctrl1 ),
.cfg_clk_skew_ctrl2 (cfg_clk_skew_ctrl2 ),
- .la_data_in (la_data_in[17:0] ),
+ .la_data_in (la_data_in_rp[17:0] ),
.uartm_rxd (uartm_rxd ),
.uartm_txd (uartm_txd ),
@@ -998,7 +1014,7 @@
.cfg_bypass_dcache (cfg_bypass_dcache ),
// Clock
- .core_clk_int (cpu_clk ),
+ .core_clk_int (cpu_clk_rp_risc ),
.cfg_ccska_riscv_intf (cfg_ccska_riscv_intf_rp ),
.cfg_ccska_riscv_icon (cfg_ccska_riscv_icon_rp ),
.cfg_ccska_riscv_core0 (cfg_ccska_riscv_core0_rp ),
@@ -1225,15 +1241,15 @@
*************************************************/
aes_top u_aes (
`ifdef USE_POWER_PINS
- .vccd1 (vdda1 ),
- .vssd1 (vssa1 ),
+ .vccd1 (vdda1 ),
+ .vssd1 (vssa1 ),
`endif
.mclk (cpu_clk_aes ),
.rst_n (cpu_intf_rst_n ),
.cfg_cska (cfg_ccska_aes_rp ),
- .wbd_clk_int (cpu_clk ),
+ .wbd_clk_int (cpu_clk_rp_aes ),
.wbd_clk_out (cpu_clk_aes ),
.dmem_req (aes_dmem_req ),
@@ -1259,7 +1275,7 @@
.rst_n (cpu_intf_rst_n ),
.cfg_cska (cfg_ccska_fpu_rp ),
- .wbd_clk_int (cpu_clk ),
+ .wbd_clk_int (cpu_clk_rp_fpu ),
.wbd_clk_out (cpu_clk_fpu ),
.dmem_req (fpu_dmem_req ),
@@ -1331,7 +1347,7 @@
wb_interconnect #(
`ifndef SYNTHESIS
- .CH_CLK_WD (4 ),
+ .CH_CLK_WD (14 ),
.CH_DATA_WD (154 )
`endif
) u_intercon (
@@ -1340,11 +1356,22 @@
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
.ch_clk_in ({
+ cpu_clk,
+ cpu_clk,
+ cpu_clk,
+ cpu_clk,
+ cpu_clk,
+ cpu_clk,
+ cpu_clk,
+ cpu_clk,
+ cpu_clk,
+ cpu_clk,
wbd_clk_int,
wbd_clk_int,
wbd_clk_int,
wbd_clk_int} ),
.ch_clk_out ({
+ cpu_clk_rp,
wbd_clk_pinmux_rp,
wbd_clk_uart_rp,
wbd_clk_qspi_rp,
@@ -1586,7 +1613,7 @@
.user_clock2 (user_clock2 ),
.int_pll_clock (int_pll_clock ),
.xtal_clk (xtal_clk ),
- .cpu_clk (cpu_clk ),
+ .cpu_clk (cpu_clk_rp_pinmux ),
.rtc_clk (rtc_clk ),
