commit c0e73d459285f9ba13c331275c6d8634a83e1e9a
author dineshannayya <dinesh.annayya@gmail.com> Tue Mar 29 18:03:10 2022 +0530
committer dineshannayya <dinesh.annayya@gmail.com> Tue Mar 29 18:03:10 2022 +0530
tree a2b39c60c50191d6d2d1a66a871b4cd60ef10e1e
parent c70869bfaed92ad8ea9c1511585f48ca9fcf0ebf

Doc update

README.md

diff --git a/README.md b/README.md
index a0a7e16..a1e80ec 100644
--- a/README.md
+++ b/README.md
@@ -621,7 +621,7 @@
     <td  align="center"> Riscduino</td>
     <td  align="center"> Single 32bit RISCV core without cache + Onchip SRAM + WB Interconnect</td>
     <td  align="center"> <a href="https://github.com/dineshannayya/riscduino">Github</a></td>
-    <td  align="center"> <a https://platform.efabless.com/projects/385">Efabless</a></td>
+    <td  align="center"> <a href="https://platform.efabless.com/projects/385">Efabless</a></td>
   </tr>
   <tr>
     <td  align="center"> MPW-4 </td> 
@@ -629,7 +629,7 @@
     <td  align="center"> Riscduino-R1</td>
     <td  align="center"> Single 32bit RISCV core with cache + Onchip SRAM + WB Inter Connect</td>
     <td  align="center"> <a href="https://github.com/dineshannayya/riscduino">Github</a></td>
-    <td  align="center"> <a https://platform.efabless.com/projects/575">Efabless</a></td>
+    <td  align="center"> <a href="https://platform.efabless.com/projects/575">Efabless</a></td>
   </tr>
   <tr>
     <td  align="center"> MPW-5 </td> 
@@ -637,7 +637,7 @@
     <td  align="center"> Riscduino-SCORE</td>
     <td  align="center"> Single 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
     <td  align="center"> <a href="https://github.com/dineshannayya/riscduino">Github</a></td>
-    <td  align="center"> <a https://platform.efabless.com/projects/670">Efabless</a></td>
+    <td  align="center"> <a href="https://platform.efabless.com/projects/670">Efabless</a></td>
   </tr>
   <tr>
     <td  align="center"> MPW-5 </td> 
@@ -645,7 +645,7 @@
     <td  align="center"> Riscduino-DCORE</td>
     <td  align="center"> Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
     <td  align="center"> <a href="https://github.com/dineshannayya/riscduino_dcore">Github</a></td>
-    <td  align="center"> <a https://platform.efabless.com/projects/718">Efabless</a></td>
+    <td  align="center"> <a href="https://platform.efabless.com/projects/718">Efabless</a></td>
   </tr>
   <tr>
     <td  align="center"> MPW-5 </td> 
@@ -653,7 +653,7 @@
     <td  align="center"> Riscduino-QCORE</td>
     <td  align="center"> Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
     <td  align="center"> <a href="https://github.com/dineshannayya/riscduino_qcore">Github</a></td>
-    <td  align="center"> <a https://platform.efabless.com/projects/782">Efabless</a></td>
+    <td  align="center"> <a href="https://platform.efabless.com/projects/782">Efabless</a></td>
   </tr>
 </table>