drc clean risc-4 integration
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 39a4885..7c6a411 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -125,15 +125,15 @@
set ::env(GND_PIN) "vssd1"
set ::env(GLB_RT_OBS) " \
- li1 150 150 833.1 566.54,\
- met1 150 150 833.1 566.54,\
- met2 150 150 833.1 566.54,\
- met3 150 150 833.1 566.54,\
+ li1 150 130 833.1 546.54,\
+ met1 150 130 833.1 546.54,\
+ met2 150 130 833.1 546.54,\
+ met3 150 130 833.1 546.54,\
- li1 950 150 1633.1 566.54,\
- met1 950 150 1633.1 566.54,\
- met2 950 150 1633.1 566.54,\
- met3 950 150 1633.1 566.54,\
+ li1 950 130 1633.1 546.54,\
+ met1 950 130 1633.1 546.54,\
+ met2 950 130 1633.1 546.54,\
+ met3 950 130 1633.1 546.54,\
li1 150 650 833.1 1066.54,\
met1 150 650 833.1 1066.54,\
@@ -191,7 +191,7 @@
set ::env(FP_PDN_VWIDTH) "3.1"
set ::env(FP_PDN_HOFFSET) "10"
-set ::env(FP_PDN_HPITCH) "100"
+set ::env(FP_PDN_HPITCH) "90"
set ::env(FP_PDN_HSPACING) "10"
set ::env(FP_PDN_HWIDTH) "3.1"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index b281fb9..055b296 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -4,12 +4,12 @@
u_riscv_top.i_core_top_0 50 1400 N
u_riscv_top.i_core_top_1 1200 1400 FN
-u_riscv_top.i_core_top_2 50 2400 N
-u_riscv_top.i_core_top_3 1200 2400 FN
+u_riscv_top.i_core_top_2 50 2450 N
+u_riscv_top.i_core_top_3 1200 2450 FN
u_riscv_top.u_connect 725 1400 N
u_riscv_top.u_intf 950 650 N
-u_icache_2kb 150 150 N
-u_dcache_2kb 950 150 N
+u_icache_2kb 150 130 N
+u_dcache_2kb 950 130 N
u_tsram0_2kb 150 650 N
diff --git a/openlane/ycr4_iconnect/config.tcl b/openlane/ycr4_iconnect/config.tcl
index d443c79..e6a3743 100644
--- a/openlane/ycr4_iconnect/config.tcl
+++ b/openlane/ycr4_iconnect/config.tcl
@@ -18,8 +18,8 @@
set ::env(ROUTING_CORES) "6"
set ::env(DESIGN_NAME) ycr4_iconnect
-set ::env(DESIGN_IS_CORE) "1"
-set ::env(FP_PDN_CORE_RING) "1"
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
# Timing configuration
set ::env(CLOCK_PERIOD) "10"
@@ -56,12 +56,12 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 390 1900"
+set ::env(DIE_AREA) "0 0 380 1900"
#set ::env(PDN_CFG) $script_dir/pdn_cfg.tcl
#set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
set ::env(PL_TARGET_DENSITY) 0.20
-set ::env(CELL_PAD) "12"
+set ::env(CELL_PAD) "14"
#set ::env(PL_ROUTABILITY_DRIVEN) "1"
set ::env(PL_TIME_DRIVEN) "1"
diff --git a/openlane/ycr4_iconnect/pin_order.cfg b/openlane/ycr4_iconnect/pin_order.cfg
index 28d1e97..4da31ff 100644
--- a/openlane/ycr4_iconnect/pin_order.cfg
+++ b/openlane/ycr4_iconnect/pin_order.cfg
@@ -441,7 +441,7 @@
core0_irq_lines\[0\]
core0_irq_soft
-core2_uid\[1\] 1200 00 2
+core2_uid\[1\] 1250 00 2
core2_uid\[0\]
core2_imem_req_ack
core2_imem_req
@@ -516,7 +516,7 @@
core2_imem_resp\[1\]
core2_imem_resp\[0\]
-core2_dmem_req_ack 1350 0 2
+core2_dmem_req_ack 1400 0 2
core2_dmem_req
core2_dmem_cmd
core2_dmem_width\[1\]
@@ -620,7 +620,7 @@
core2_dmem_resp\[1\]
core2_dmem_resp\[0\]
-core2_debug\[48\] 1500 0 2
+core2_debug\[48\] 1550 0 2
core2_debug\[47\]
core2_debug\[46\]
core2_debug\[45\]
@@ -670,7 +670,7 @@
core2_debug\[1\]
core2_debug\[0\]
-core2_timer_irq 1600 0 2
+core2_timer_irq 1650 0 2
core2_timer_val\[63\]
core2_timer_val\[62\]
core2_timer_val\[61\]
@@ -1067,7 +1067,7 @@
core1_irq_lines\[0\]
core1_irq_soft
-core3_uid\[1\] 1200 00 2
+core3_uid\[1\] 1250 00 2
core3_uid\[0\]
core3_imem_req_ack
core3_imem_req
@@ -1142,7 +1142,7 @@
core3_imem_resp\[1\]
core3_imem_resp\[0\]
-core3_dmem_req_ack 1350 0 2
+core3_dmem_req_ack 1400 0 2
core3_dmem_req
core3_dmem_cmd
core3_dmem_width\[1\]
@@ -1246,7 +1246,7 @@
core3_dmem_resp\[1\]
core3_dmem_resp\[0\]
-core3_debug\[48\] 1500 0 2
+core3_debug\[48\] 1550 0 2
core3_debug\[47\]
core3_debug\[46\]
core3_debug\[45\]
@@ -1296,7 +1296,7 @@
core3_debug\[1\]
core3_debug\[0\]
-core3_timer_irq 1600 0 2
+core3_timer_irq 1650 0 2
core3_timer_val\[63\]
core3_timer_val\[62\]
core3_timer_val\[61\]
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index 65347ff..ffbc279 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl
@@ -71,7 +71,7 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 590 930 "
+set ::env(DIE_AREA) "0 0 580 930 "
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
set ::env(PL_TARGET_DENSITY) 0.38
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 5f34d41..05ba7f1 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h1m53s0ms,0h4m26s0ms,-2.0,-1,-1,-1,597.46,18,0,0,0,0,0,0,-1,0,29,-1,-1,1507480,13275,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.57,8.93,1.79,2.26,0.0,391,4275,391,4275,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,100,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h2m47s0ms,0h4m13s0ms,-2.0,-1,-1,-1,588.16,14,0,0,0,0,0,0,-1,0,0,-1,-1,1516980,13216,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.65,8.91,1.7,2.19,0.0,389,4273,389,4273,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/ycr4_iconnect/final_summary_report.csv b/signoff/ycr4_iconnect/final_summary_report.csv
index 722abe2..6b94665 100644
--- a/signoff/ycr4_iconnect/final_summary_report.csv
+++ b/signoff/ycr4_iconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/ycr4_iconnect,ycr4_iconnect,ycr4_iconnect,flow completed,0h41m14s0ms,0h34m10s0ms,11387.31443994602,0.741,5693.65721997301,5.16,1613.16,4219,0,0,0,0,0,0,0,191,0,0,-1,1293111,71757,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,1105514567.0,0.0,28.93,60.6,13.63,53.45,-1,4301,10616,622,6874,0,0,0,4568,425,85,139,123,430,136,20,1551,1026,730,22,1380,10034,0,11414,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.2,0.3,sky130_fd_sc_hd,12,3
+0,/project/openlane/ycr4_iconnect,ycr4_iconnect,ycr4_iconnect,flow completed,0h38m19s0ms,0h31m37s0ms,11686.98060941828,0.722,5843.49030470914,5.29,1569.5,4219,0,0,0,0,0,0,0,177,0,0,-1,1273610,69630,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,1054561473.0,0.0,28.17,58.08,14.25,56.9,-1,4301,10616,622,6874,0,0,0,4568,425,85,139,123,430,136,20,1551,1026,730,22,1380,9688,0,11068,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.2,0.3,sky130_fd_sc_hd,14,3
diff --git a/signoff/ycr_core_top/final_summary_report.csv b/signoff/ycr_core_top/final_summary_report.csv
index 426bb7a..91617ca 100644
--- a/signoff/ycr_core_top/final_summary_report.csv
+++ b/signoff/ycr_core_top/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/ycr_core_top,ycr_core_top,ycr_core_top,flow completed,0h49m1s0ms,0h41m19s0ms,74058.68416256607,0.5487,37029.34208128304,37.04,2323.93,20318,0,0,0,0,0,0,0,138,0,0,-1,1252569,182628,0.0,-8.3,-1,0.0,0.0,0.0,-8105.44,-1,0.0,0.0,956691859.0,0.0,51.85,67.46,22.39,49.15,-1,16388,22628,537,6677,0,0,0,19143,686,261,526,603,2869,894,266,4810,2496,2403,42,666,7370,0,8036,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.38,0.3,sky130_fd_sc_hd,6,3
+0,/project/openlane/ycr_core_top,ycr_core_top,ycr_core_top,flow completed,0h59m58s0ms,0h49m49s0ms,75335.55802743789,0.5394,37667.779013718944,37.72,2294.39,20318,0,0,0,0,0,0,0,147,0,0,-1,1254475,182224,0.0,-8.36,-1,0.0,0.0,0.0,-8104.68,-1,0.0,0.0,962392628.0,0.0,51.91,69.19,23.06,51.39,-1,16388,22628,537,6677,0,0,0,19143,686,261,526,603,2869,894,266,4810,2496,2403,42,666,7370,0,8036,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.38,0.3,sky130_fd_sc_hd,6,3
