bus repeater + peri_top + ws281x pad direction bug fix
diff --git a/.gitmodules b/.gitmodules
index 4fc3d24..b4a0953 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -7,3 +7,6 @@
[submodule "verilog/dv/common/riscduino_board"]
path = verilog/dv/common/riscduino_board
url = https://github.com/dineshannayya/riscduino_board.git
+[submodule "rtc"]
+ path = verilog/rtl/rtc
+ url = https://github.com/dineshannayya/rtc
diff --git a/Makefile b/Makefile
index a54eedb..9eae04d 100644
--- a/Makefile
+++ b/Makefile
@@ -110,7 +110,7 @@
# Install DV setup
.PHONY: simenv
simenv:
- docker pull riscduino/dv_setup:mpw6
+ docker pull riscduino/dv_setup:mpw7
.PHONY: setup
setup: install check-env install_mcw openlane pdk-with-volare setup-timing-scripts
@@ -132,7 +132,7 @@
-e TOOLS=/opt/riscv32i \
-e DESIGNS=$(TARGET_PATH) \
-e GCC_PREFIX=riscv32-unknown-elf \
- -u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:mpw6 \
+ -u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:mpw7 \
sh -c $(verify_command)
@@ -247,18 +247,18 @@
fi
zip:
- gzip -f lef/*
- gzip -f gds/*
- gzip -f spef/*
- gzip -f spi/lvs/*
- gzip -f verilog/gl/*
+ gzip -f -r lef/*
+ gzip -f -r gds/*
+ gzip -f -r spef/*
+ gzip -f -r spi/lvs/*
+ gzip -f -r verilog/gl/*
unzip:
- gzip -d lef/*
- gzip -d gds/*
- gzip -d spef/*
- gzip -d spi/lvs/*
- gzip -d verilog/gl/*
+ gzip -d -r lef/*
+ gzip -d -r gds/*
+ gzip -d -r spef/*
+ gzip -d -r spi/lvs/*
+ gzip -d -r verilog/gl/*
.PHONY: help
help:
diff --git a/env/spef-mapping.tcl b/env/spef-mapping.tcl
index 5ac4c83..bed4e09 100644
--- a/env/spef-mapping.tcl
+++ b/env/spef-mapping.tcl
@@ -1,5 +1,6 @@
set spef_mapping(mprj/u_4x8bit_dac) "$::env(PROJECT_ROOT)/signoff/not-found/dac_top.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_intercon) "$::env(PROJECT_ROOT)/signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_peri) "$::env(PROJECT_ROOT)/signoff/peri_top/openlane-signoff/spef/peri_top.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_pinmux) "$::env(PROJECT_ROOT)/signoff/pinmux_top/openlane-signoff/spef/pinmux_top.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_pll) "$::env(PROJECT_ROOT)/signoff/dg_pll/openlane-signoff/spef/dg_pll.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_qspi_master) "$::env(PROJECT_ROOT)/signoff/qspim_top/openlane-signoff/spef/qspim_top.$::env(RCX_CORNER).spef"
@@ -9,5 +10,9 @@
set spef_mapping(mprj/\u_riscv_top.i_core_top_3) "$::env(PROJECT_ROOT)/signoff/ycr_core_top/openlane-signoff/spef/ycr_core_top.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/\u_riscv_top.u_connect) "$::env(PROJECT_ROOT)/signoff/ycr4_iconnect/openlane-signoff/spef/ycr4_iconnect.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/\u_riscv_top.u_intf) "$::env(PROJECT_ROOT)/signoff/ycr_intf/openlane-signoff/spef/ycr_intf.$::env(RCX_CORNER).spef"
-set spef_mapping(mprj/u_uart_i2c_usb_spi) "$::env(PROJECT_ROOT)/signoff/not-found/uart_i2c_usb_spi_top.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_rp_east) "$::env(PROJECT_ROOT)/signoff/bus_rep_east/openlane-signoff/spef/bus_rep_east.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_rp_north) "$::env(PROJECT_ROOT)/signoff/bus_rep_north/openlane-signoff/spef/bus_rep_north.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_rp_south) "$::env(PROJECT_ROOT)/signoff/bus_rep_south/openlane-signoff/spef/bus_rep_south.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_rp_west) "$::env(PROJECT_ROOT)/signoff/bus_rep_west/openlane-signoff/spef/bus_rep_west.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_uart_i2c_usb_spi) "$::env(PROJECT_ROOT)/signoff/uart_i2c_usb_spi_top/openlane-signoff/spef/uart_i2c_usb_spi_top.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_wb_host) "$::env(PROJECT_ROOT)/signoff/wb_host/openlane-signoff/spef/wb_host.$::env(RCX_CORNER).spef"
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 9aa0565..5370679 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 3ea7c80..6d2dfff 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/openlane/bus_rep_east/config.tcl b/openlane/bus_rep_east/config.tcl
new file mode 100755
index 0000000..0362cfc
--- /dev/null
+++ b/openlane/bus_rep_east/config.tcl
@@ -0,0 +1,134 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) bus_rep_east
+
+
+set ::env(DESIGN_IS_CORE) "1"
+set ::env(FP_PDN_CORE_RING) {1}
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_NET) ""
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_east.sv \
+ "
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=45 "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 3420 50"
+
+#set ::env(GRT_OBS) "met4 0 0 300 1725"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.20"
+set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) 0.2
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+## CTS
+set ::env(CLOCK_TREE_SYNTH) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0"
+
+## Routing
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+#set ::env(GLB_RT_MAXLAYER) 3
+set ::env(RT_MAX_LAYER) {met3}
+set ::env(FP_PDN_LOWER_LAYER) {met2}
+set ::env(FP_PDN_UPPER_LAYER) {met3}
+
+set ::env(FP_IO_HLAYER) {met2}
+set ::env(FP_IO_VLAYER) {met1}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
+
+set ::env(ECO_ENABLE) {0}
+#set ::env(CURRENT_STEP) "synthesis"
+#set ::env(LAST_STEP) "parasitics_sta"
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_east/interactive.tcl b/openlane/bus_rep_east/interactive.tcl
new file mode 100755
index 0000000..5b5c6c8
--- /dev/null
+++ b/openlane/bus_rep_east/interactive.tcl
@@ -0,0 +1,337 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+proc run_placement_step {args} {
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+ if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+ remove_buffers_from_nets
+ }
+}
+
+proc run_routing_step {args} {
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ if { $::env(ECO_ENABLE) == 0 } {
+ run_routing
+ }
+}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+ run_parasitics_sta
+ }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_irdrop_report_step {args} {
+ if { $::env(RUN_IRDROP_REPORT) } {
+ run_irdrop_report
+ }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_erc_step {args} {
+ if { $::env(RUN_CVC) } {
+ run_erc
+ }
+}
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
+}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
+proc run_post_run_hooks {} {
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
+}
+
+proc run_floorplan {args} {
+ # |----------------------------------------------------|
+ # |---------------- 2. FLOORPLAN ------------------|
+ # |----------------------------------------------------|
+ #
+ # intial fp
+ init_floorplan
+
+ # check for deprecated io variables
+ if { [info exists ::env(FP_IO_HMETAL)]} {
+ set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+ puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+ }
+
+ if { [info exists ::env(FP_IO_VMETAL)]} {
+ set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+ puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+ }
+
+
+ # place io
+ if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+ place_io_ol
+ } else {
+ if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+ place_io
+ global_placement_or
+ place_contextualized_io \
+ -lef $::env(FP_CONTEXT_LEF) \
+ -def $::env(FP_CONTEXT_DEF)
+ } else {
+ place_io
+ }
+ }
+
+ apply_def_template
+
+ #if { [info exist ::env(EXTRA_LEFS)] } {
+ if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+ file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+ manual_macro_placement -f
+ } else {
+ # global_placement_or
+ # basic_macro_placement
+ }
+ #}
+
+ if { $::env(RUN_TAP_DECAP_INSERTION) } {
+ tap_decap_or
+ }
+
+ scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
+
+ run_power_grid_generation
+}
+
+
+
+proc run_flow {args} {
+ set options {
+ {-design optional}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+ # signal trap SIGINT save_state;
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ load_overrides $arg_values(-override_env)
+ }
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 1
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+ set steps [dict create \
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "irdrop" "run_irdrop_report_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
+ ]
+
+ if { [info exists arg_values(-from) ]} {
+ puts_info "Starting flow at $arg_values(-from)..."
+ set ::env(CURRENT_STEP) $arg_values(-from)
+ } elseif { [info exists ::env(CURRENT_STEP) ] } {
+ puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+ } else {
+ set ::env(CURRENT_STEP) "synthesis"
+ }
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+ set_if_unset arg_values(-to) "cvc"
+
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ # Saves to <RUN_DIR>/results/final
+ save_final_views
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/bus_rep_east/macro.cfg b/openlane/bus_rep_east/macro.cfg
new file mode 100644
index 0000000..e84abca
--- /dev/null
+++ b/openlane/bus_rep_east/macro.cfg
@@ -0,0 +1,46 @@
+u_rp\[0\].u_buf 7.82 10.88 FN
+u_rp\[1\].u_buf 85.1 10.88 FN
+u_rp\[2\].u_buf 162.38 10.88 FN
+u_rp\[3\].u_buf 239.66 10.88 FN
+u_rp\[4\].u_buf 316.94 10.88 FN
+u_rp\[5\].u_buf 394.22 10.88 FN
+u_rp\[6\].u_buf 471.5 10.88 FN
+u_rp\[7\].u_buf 548.78 10.88 FN
+u_rp\[8\].u_buf 626.06 10.88 FN
+u_rp\[9\].u_buf 703.34 10.88 FN
+u_rp\[10\].u_buf 780.62 10.88 FN
+u_rp\[11\].u_buf 857.9 10.88 FN
+u_rp\[12\].u_buf 935.18 10.88 FN
+u_rp\[13\].u_buf 1012.46 10.88 FN
+u_rp\[14\].u_buf 1089.74 10.88 FN
+u_rp\[15\].u_buf 1167.02 10.88 FN
+u_rp\[16\].u_buf 1244.3 10.88 FN
+u_rp\[17\].u_buf 1321.58 10.88 FN
+u_rp\[18\].u_buf 1398.86 10.88 FN
+u_rp\[19\].u_buf 1476.14 10.88 FN
+u_rp\[20\].u_buf 1553.42 10.88 FN
+u_rp\[21\].u_buf 1630.7 10.88 FN
+u_rp\[22\].u_buf 1707.98 10.88 FN
+u_rp\[23\].u_buf 1785.26 10.88 FN
+u_rp\[24\].u_buf 1862.54 10.88 FN
+u_rp\[25\].u_buf 1939.82 10.88 FN
+u_rp\[26\].u_buf 2017.1 10.88 FN
+u_rp\[27\].u_buf 2094.38 10.88 FN
+u_rp\[28\].u_buf 2171.66 10.88 FN
+u_rp\[29\].u_buf 2248.94 10.88 FN
+u_rp\[30\].u_buf 2326.22 10.88 FN
+u_rp\[31\].u_buf 2403.5 10.88 FN
+u_rp\[32\].u_buf 2480.78 10.88 FN
+u_rp\[33\].u_buf 2558.06 10.88 FN
+u_rp\[34\].u_buf 2635.34 10.88 FN
+u_rp\[35\].u_buf 2712.62 10.88 FN
+u_rp\[36\].u_buf 2789.9 10.88 FN
+u_rp\[37\].u_buf 2867.18 10.88 FN
+u_rp\[38\].u_buf 2944.46 10.88 FN
+u_rp\[39\].u_buf 3021.74 10.88 FN
+u_rp\[40\].u_buf 3099.02 10.88 FN
+u_rp\[41\].u_buf 3176.3 10.88 FN
+u_rp\[42\].u_buf 3253.58 10.88 FN
+u_rp\[43\].u_buf 3330.86 10.88 FN
+u_rp\[44\].u_buf 3408.14 10.88 FN
+
diff --git a/openlane/uart_i2cm_usb_spi_top/pdn.tcl b/openlane/bus_rep_east/pdn.tcl
similarity index 100%
copy from openlane/uart_i2cm_usb_spi_top/pdn.tcl
copy to openlane/bus_rep_east/pdn.tcl
diff --git a/openlane/bus_rep_east/pin_order.cfg b/openlane/bus_rep_east/pin_order.cfg
new file mode 100644
index 0000000..bfe94f9
--- /dev/null
+++ b/openlane/bus_rep_east/pin_order.cfg
@@ -0,0 +1,99 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#N
+ch_out\[0\] 0 0 225
+ch_out\[1\]
+ch_in\[2\]
+ch_out\[3\]
+ch_out\[4\]
+ch_in\[5\]
+ch_out\[6\]
+ch_out\[7\]
+ch_in\[8\]
+ch_out\[9\]
+ch_out\[10\]
+ch_in\[11\]
+ch_out\[12\]
+ch_out\[13\]
+ch_in\[14\]
+ch_out\[15\]
+ch_out\[16\]
+ch_in\[17\]
+ch_out\[18\]
+ch_out\[19\]
+ch_in\[20\]
+ch_out\[21\]
+ch_out\[22\]
+ch_in\[23\]
+ch_out\[24\]
+ch_out\[25\]
+ch_in\[26\]
+ch_out\[27\]
+ch_out\[28\]
+ch_in\[29\]
+ch_out\[30\]
+ch_out\[31\]
+ch_in\[32\]
+ch_out\[33\]
+ch_out\[34\]
+ch_in\[35\]
+ch_out\[36\]
+ch_out\[37\]
+ch_in\[38\]
+ch_out\[39\]
+ch_out\[40\]
+ch_in\[41\]
+ch_out\[42\]
+ch_out\[43\]
+ch_in\[44\]
+
+#S
+ch_in\[0\] 1140 0 6
+ch_in\[1\]
+ch_out\[2\]
+ch_in\[3\]
+ch_in\[4\]
+ch_out\[5\]
+ch_in\[6\]
+ch_in\[7\]
+ch_out\[8\]
+ch_in\[9\]
+ch_in\[10\]
+ch_out\[11\]
+ch_in\[12\]
+ch_in\[13\]
+ch_out\[14\]
+ch_in\[15\]
+ch_in\[16\]
+ch_out\[17\]
+ch_in\[18\]
+ch_in\[19\]
+ch_out\[20\]
+ch_in\[21\]
+ch_in\[22\]
+ch_out\[23\]
+ch_in\[24\]
+ch_in\[25\]
+ch_out\[26\]
+ch_in\[27\]
+ch_in\[28\]
+ch_out\[29\]
+ch_in\[30\]
+ch_in\[31\]
+ch_out\[32\]
+ch_in\[33\]
+ch_in\[34\]
+ch_out\[35\]
+ch_in\[36\]
+ch_in\[37\]
+ch_out\[38\]
+ch_in\[39\]
+ch_in\[40\]
+ch_out\[41\]
+ch_in\[42\]
+ch_in\[43\]
+ch_out\[44\]
+
+
diff --git a/openlane/bus_rep_north/config.tcl b/openlane/bus_rep_north/config.tcl
new file mode 100755
index 0000000..e66bac5
--- /dev/null
+++ b/openlane/bus_rep_north/config.tcl
@@ -0,0 +1,135 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) bus_rep_north
+
+
+set ::env(DESIGN_IS_CORE) "1"
+set ::env(FP_PDN_CORE_RING) {1}
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_NET) ""
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_north.sv \
+ "
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=27 \
+ BUS_BUF_WD=42 "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2650 50"
+
+#set ::env(GRT_OBS) "met4 0 0 300 1725"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.20"
+set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) 0.2
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+## CTS
+set ::env(CLOCK_TREE_SYNTH) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0"
+
+## Routing
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+#set ::env(GLB_RT_MAXLAYER) 3
+set ::env(RT_MAX_LAYER) {met3}
+set ::env(FP_PDN_LOWER_LAYER) {met2}
+set ::env(FP_PDN_UPPER_LAYER) {met3}
+
+set ::env(FP_IO_HLAYER) {met2}
+set ::env(FP_IO_VLAYER) {met1}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
+
+set ::env(ECO_ENABLE) {0}
+#set ::env(CURRENT_STEP) "synthesis"
+#set ::env(LAST_STEP) "parasitics_sta"
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_north/interactive.tcl b/openlane/bus_rep_north/interactive.tcl
new file mode 100755
index 0000000..5b5c6c8
--- /dev/null
+++ b/openlane/bus_rep_north/interactive.tcl
@@ -0,0 +1,337 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+proc run_placement_step {args} {
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+ if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+ remove_buffers_from_nets
+ }
+}
+
+proc run_routing_step {args} {
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ if { $::env(ECO_ENABLE) == 0 } {
+ run_routing
+ }
+}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+ run_parasitics_sta
+ }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_irdrop_report_step {args} {
+ if { $::env(RUN_IRDROP_REPORT) } {
+ run_irdrop_report
+ }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_erc_step {args} {
+ if { $::env(RUN_CVC) } {
+ run_erc
+ }
+}
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
+}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
+proc run_post_run_hooks {} {
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
+}
+
+proc run_floorplan {args} {
+ # |----------------------------------------------------|
+ # |---------------- 2. FLOORPLAN ------------------|
+ # |----------------------------------------------------|
+ #
+ # intial fp
+ init_floorplan
+
+ # check for deprecated io variables
+ if { [info exists ::env(FP_IO_HMETAL)]} {
+ set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+ puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+ }
+
+ if { [info exists ::env(FP_IO_VMETAL)]} {
+ set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+ puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+ }
+
+
+ # place io
+ if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+ place_io_ol
+ } else {
+ if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+ place_io
+ global_placement_or
+ place_contextualized_io \
+ -lef $::env(FP_CONTEXT_LEF) \
+ -def $::env(FP_CONTEXT_DEF)
+ } else {
+ place_io
+ }
+ }
+
+ apply_def_template
+
+ #if { [info exist ::env(EXTRA_LEFS)] } {
+ if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+ file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+ manual_macro_placement -f
+ } else {
+ # global_placement_or
+ # basic_macro_placement
+ }
+ #}
+
+ if { $::env(RUN_TAP_DECAP_INSERTION) } {
+ tap_decap_or
+ }
+
+ scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
+
+ run_power_grid_generation
+}
+
+
+
+proc run_flow {args} {
+ set options {
+ {-design optional}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+ # signal trap SIGINT save_state;
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ load_overrides $arg_values(-override_env)
+ }
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 1
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+ set steps [dict create \
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "irdrop" "run_irdrop_report_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
+ ]
+
+ if { [info exists arg_values(-from) ]} {
+ puts_info "Starting flow at $arg_values(-from)..."
+ set ::env(CURRENT_STEP) $arg_values(-from)
+ } elseif { [info exists ::env(CURRENT_STEP) ] } {
+ puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+ } else {
+ set ::env(CURRENT_STEP) "synthesis"
+ }
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+ set_if_unset arg_values(-to) "cvc"
+
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ # Saves to <RUN_DIR>/results/final
+ save_final_views
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/bus_rep_north/macro.cfg b/openlane/bus_rep_north/macro.cfg
new file mode 100644
index 0000000..f743181
--- /dev/null
+++ b/openlane/bus_rep_north/macro.cfg
@@ -0,0 +1,27 @@
+u_rp\[0\].u_buf 7.82 10.88 FN
+u_rp\[1\].u_buf 97.98 10.88 FN
+u_rp\[2\].u_buf 188.14 10.88 FN
+u_rp\[3\].u_buf 278.3 10.88 FN
+u_rp\[4\].u_buf 368.46 10.88 FN
+u_rp\[5\].u_buf 458.62 10.88 FN
+u_rp\[6\].u_buf 548.78 10.88 FN
+u_rp\[7\].u_buf 638.94 10.88 FN
+u_rp\[8\].u_buf 729.1 10.88 FN
+u_rp\[9\].u_buf 819.26 10.88 FN
+u_rp\[10\].u_buf 909.42 10.88 FN
+u_rp\[11\].u_buf 999.58 10.88 FN
+u_rp\[12\].u_buf 1089.74 10.88 FN
+u_rp\[13\].u_buf 1179.9 10.88 FN
+u_rp\[14\].u_buf 1270.06 10.88 FN
+u_rp\[15\].u_buf 1360.22 10.88 FN
+u_rp\[16\].u_buf 1450.38 10.88 FN
+u_rp\[17\].u_buf 1540.54 10.88 FN
+u_rp\[18\].u_buf 1630.7 10.88 FN
+u_rp\[19\].u_buf 1720.86 10.88 FN
+u_rp\[20\].u_buf 1811.02 10.88 FN
+u_rp\[21\].u_buf 1901.18 10.88 FN
+u_rp\[22\].u_buf 1991.34 10.88 FN
+u_rp\[23\].u_buf 2081.5 10.88 FN
+u_rp\[24\].u_buf 2171.66 10.88 FN
+u_rp\[25\].u_buf 2261.82 10.88 FN
+u_rp\[26\].u_buf 2351.98 10.88 FN
diff --git a/openlane/uart_i2cm_usb_spi_top/pdn.tcl b/openlane/bus_rep_north/pdn.tcl
similarity index 100%
copy from openlane/uart_i2cm_usb_spi_top/pdn.tcl
copy to openlane/bus_rep_north/pdn.tcl
diff --git a/openlane/bus_rep_north/pin_order.cfg b/openlane/bus_rep_north/pin_order.cfg
new file mode 100644
index 0000000..3fc1b58
--- /dev/null
+++ b/openlane/bus_rep_north/pin_order.cfg
@@ -0,0 +1,149 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#N
+ch_out\[0\] 0 0 250
+ch_out\[1\]
+ch_in\[2\]
+ch_out\[3\]
+ch_out\[4\]
+ch_in\[5\]
+ch_out\[6\]
+ch_out\[7\]
+ch_in\[8\]
+ch_out\[9\]
+ch_out\[10\]
+ch_in\[11\]
+ch_out\[12\]
+ch_out\[13\]
+ch_in\[14\]
+ch_out\[15\]
+ch_out\[16\]
+ch_in\[17\]
+ch_out\[18\]
+ch_out\[19\]
+ch_in\[20\]
+ch_out\[21\]
+ch_out\[22\]
+ch_in\[23\]
+ch_out\[24\]
+ch_out\[25\]
+ch_in\[26\]
+
+#S
+buf_in\[0\] 0100 0 4
+buf_out\[1\]
+buf_out\[2\]
+buf_in\[3\]
+buf_out\[4\]
+buf_out\[5\]
+buf_in\[6\]
+buf_out\[7\]
+buf_out\[8\]
+buf_in\[9\]
+buf_out\[10\]
+buf_out\[11\]
+buf_in\[12\]
+buf_out\[13\]
+buf_out\[14\]
+buf_in\[15\]
+buf_out\[16\]
+buf_out\[17\]
+buf_in\[18\]
+buf_out\[19\]
+buf_out\[20\]
+buf_in\[21\]
+buf_out\[22\]
+buf_out\[23\]
+buf_in\[24\]
+buf_out\[25\]
+buf_out\[26\]
+buf_in\[27\]
+buf_out\[28\]
+buf_out\[29\]
+buf_in\[30\]
+buf_out\[31\]
+buf_out\[32\]
+buf_in\[33\]
+buf_out\[34\]
+buf_out\[35\]
+buf_in\[36\]
+buf_out\[37\]
+buf_out\[38\]
+buf_in\[39\]
+buf_out\[40\]
+buf_out\[41\]
+
+buf_in\[41\] 2000 0 4
+buf_in\[40\]
+buf_out\[39\]
+buf_in\[38\]
+buf_in\[37\]
+buf_out\[36\]
+buf_in\[35\]
+buf_in\[34\]
+buf_out\[33\]
+buf_in\[32\]
+buf_in\[31\]
+buf_out\[30\]
+buf_in\[29\]
+buf_in\[28\]
+buf_out\[27\]
+buf_in\[26\]
+buf_in\[25\]
+buf_out\[24\]
+buf_in\[23\]
+buf_in\[22\]
+buf_out\[21\]
+buf_in\[20\]
+buf_in\[19\]
+buf_out\[18\]
+buf_in\[17\]
+buf_in\[16\]
+buf_out\[15\]
+buf_in\[14\]
+buf_in\[13\]
+buf_out\[12\]
+buf_in\[11\]
+buf_in\[10\]
+buf_out\[9\]
+buf_in\[8\]
+buf_in\[7\]
+buf_out\[6\]
+buf_in\[5\]
+buf_in\[4\]
+buf_out\[3\]
+buf_in\[2\]
+buf_in\[1\]
+buf_out\[0\]
+
+
+
+ch_in\[0\] 2400 0 16
+ch_in\[1\]
+ch_out\[2\]
+ch_in\[3\]
+ch_in\[4\]
+ch_out\[5\]
+ch_in\[6\]
+ch_in\[7\]
+ch_out\[8\]
+ch_in\[9\]
+ch_in\[10\]
+ch_out\[11\]
+ch_in\[12\]
+ch_in\[13\]
+ch_out\[14\]
+ch_in\[15\]
+ch_in\[16\]
+ch_out\[17\]
+ch_in\[18\]
+ch_in\[19\]
+ch_out\[20\]
+ch_in\[21\]
+ch_in\[22\]
+ch_out\[23\]
+ch_in\[24\]
+ch_in\[25\]
+ch_out\[26\]
diff --git a/openlane/bus_rep_south/config.tcl b/openlane/bus_rep_south/config.tcl
new file mode 100755
index 0000000..eec763c
--- /dev/null
+++ b/openlane/bus_rep_south/config.tcl
@@ -0,0 +1,134 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) bus_rep_south
+
+
+set ::env(DESIGN_IS_CORE) "1"
+set ::env(FP_PDN_CORE_RING) {1}
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_NET) ""
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_south.sv \
+ "
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=253 "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2650 50"
+
+#set ::env(GRT_OBS) "met4 0 0 300 1725"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.20"
+set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) 0.2
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+## CTS
+set ::env(CLOCK_TREE_SYNTH) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0"
+
+## Routing
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+#set ::env(GLB_RT_MAXLAYER) 3
+set ::env(RT_MAX_LAYER) {met3}
+set ::env(FP_PDN_LOWER_LAYER) {met2}
+set ::env(FP_PDN_UPPER_LAYER) {met3}
+
+set ::env(FP_IO_HLAYER) {met2}
+set ::env(FP_IO_VLAYER) {met1}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "600"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
+
+set ::env(ECO_ENABLE) {0}
+#set ::env(CURRENT_STEP) "synthesis"
+#set ::env(LAST_STEP) "parasitics_sta"
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_south/interactive.tcl b/openlane/bus_rep_south/interactive.tcl
new file mode 100755
index 0000000..5b5c6c8
--- /dev/null
+++ b/openlane/bus_rep_south/interactive.tcl
@@ -0,0 +1,337 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+proc run_placement_step {args} {
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+ if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+ remove_buffers_from_nets
+ }
+}
+
+proc run_routing_step {args} {
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ if { $::env(ECO_ENABLE) == 0 } {
+ run_routing
+ }
+}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+ run_parasitics_sta
+ }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_irdrop_report_step {args} {
+ if { $::env(RUN_IRDROP_REPORT) } {
+ run_irdrop_report
+ }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_erc_step {args} {
+ if { $::env(RUN_CVC) } {
+ run_erc
+ }
+}
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
+}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
+proc run_post_run_hooks {} {
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
+}
+
+proc run_floorplan {args} {
+ # |----------------------------------------------------|
+ # |---------------- 2. FLOORPLAN ------------------|
+ # |----------------------------------------------------|
+ #
+ # intial fp
+ init_floorplan
+
+ # check for deprecated io variables
+ if { [info exists ::env(FP_IO_HMETAL)]} {
+ set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+ puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+ }
+
+ if { [info exists ::env(FP_IO_VMETAL)]} {
+ set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+ puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+ }
+
+
+ # place io
+ if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+ place_io_ol
+ } else {
+ if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+ place_io
+ global_placement_or
+ place_contextualized_io \
+ -lef $::env(FP_CONTEXT_LEF) \
+ -def $::env(FP_CONTEXT_DEF)
+ } else {
+ place_io
+ }
+ }
+
+ apply_def_template
+
+ #if { [info exist ::env(EXTRA_LEFS)] } {
+ if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+ file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+ manual_macro_placement -f
+ } else {
+ # global_placement_or
+ # basic_macro_placement
+ }
+ #}
+
+ if { $::env(RUN_TAP_DECAP_INSERTION) } {
+ tap_decap_or
+ }
+
+ scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
+
+ run_power_grid_generation
+}
+
+
+
+proc run_flow {args} {
+ set options {
+ {-design optional}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+ # signal trap SIGINT save_state;
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ load_overrides $arg_values(-override_env)
+ }
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 1
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+ set steps [dict create \
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "irdrop" "run_irdrop_report_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
+ ]
+
+ if { [info exists arg_values(-from) ]} {
+ puts_info "Starting flow at $arg_values(-from)..."
+ set ::env(CURRENT_STEP) $arg_values(-from)
+ } elseif { [info exists ::env(CURRENT_STEP) ] } {
+ puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+ } else {
+ set ::env(CURRENT_STEP) "synthesis"
+ }
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+ set_if_unset arg_values(-to) "cvc"
+
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ # Saves to <RUN_DIR>/results/final
+ save_final_views
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/bus_rep_south/macro.cfg b/openlane/bus_rep_south/macro.cfg
new file mode 100644
index 0000000..535d4ee
--- /dev/null
+++ b/openlane/bus_rep_south/macro.cfg
@@ -0,0 +1,254 @@
+u_rp\[0\].u_buf 7.82 10.88 FN
+u_rp\[1\].u_buf 7.82 16.32 FN
+u_rp\[2\].u_buf 20.7 10.88 FN
+u_rp\[3\].u_buf 20.7 16.32 FN
+u_rp\[4\].u_buf 33.58 10.88 FN
+u_rp\[5\].u_buf 33.58 16.32 FN
+u_rp\[6\].u_buf 46.46 10.88 FN
+u_rp\[7\].u_buf 46.46 16.32 FN
+u_rp\[8\].u_buf 59.34 10.88 FN
+u_rp\[9\].u_buf 59.34 16.32 FN
+u_rp\[10\].u_buf 72.22 10.88 FN
+u_rp\[11\].u_buf 72.22 16.32 FN
+u_rp\[12\].u_buf 85.1 10.88 FN
+u_rp\[13\].u_buf 85.1 16.32 FN
+u_rp\[14\].u_buf 97.98 10.88 FN
+u_rp\[15\].u_buf 97.98 16.32 FN
+u_rp\[16\].u_buf 110.86 10.88 FN
+u_rp\[17\].u_buf 110.86 16.32 FN
+u_rp\[18\].u_buf 123.74 10.88 FN
+u_rp\[19\].u_buf 123.74 16.32 FN
+u_rp\[20\].u_buf 136.62 10.88 FN
+u_rp\[21\].u_buf 136.62 16.32 FN
+u_rp\[22\].u_buf 149.5 10.88 FN
+u_rp\[23\].u_buf 149.5 16.32 FN
+u_rp\[24\].u_buf 162.38 10.88 FN
+u_rp\[25\].u_buf 162.38 16.32 FN
+u_rp\[26\].u_buf 175.26 10.88 FN
+u_rp\[27\].u_buf 175.26 16.32 FN
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+u_rp\[29\].u_buf 188.14 16.32 FN
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+u_rp\[35\].u_buf 226.78 16.32 FN
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+u_rp\[39\].u_buf 252.54 16.32 FN
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+u_rp\[41\].u_buf 265.42 16.32 FN
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+u_rp\[43\].u_buf 278.3 16.32 FN
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+u_rp\[47\].u_buf 304.06 16.32 FN
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+u_rp\[71\].u_buf 458.62 16.32 FN
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+u_rp\[252\].u_buf 2570.94 10.88 FN
+
diff --git a/openlane/uart_i2cm_usb_spi_top/pdn.tcl b/openlane/bus_rep_south/pdn.tcl
similarity index 100%
copy from openlane/uart_i2cm_usb_spi_top/pdn.tcl
copy to openlane/bus_rep_south/pdn.tcl
diff --git a/openlane/bus_rep_south/pin_order.cfg b/openlane/bus_rep_south/pin_order.cfg
new file mode 100644
index 0000000..4546535
--- /dev/null
+++ b/openlane/bus_rep_south/pin_order.cfg
@@ -0,0 +1,528 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#N
+ch_out\[0\] 1000 0 8
+ch_out\[1\]
+ch_in\[2\]
+ch_out\[3\]
+ch_out\[4\]
+ch_out\[5\]
+ch_out\[6\]
+ch_out\[7\]
+ch_in\[8\]
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+ch_out\[23\]
+ch_in\[24\]
+
+ch_out\[25\]
+ch_out\[26\]
+ch_in\[27\]
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+ch_out\[31\]
+ch_out\[32\]
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+ch_in\[102\]
+ch_out\[103\]
+ch_out\[104\]
+ch_in\[105\]
+
+
+
+
+ch_out\[106\] 1800 0 8
+ch_in\[107\]
+ch_out\[108\]
+ch_in\[109\]
+ch_out\[110\]
+ch_in\[111\]
+ch_out\[112\]
+ch_in\[113\]
+ch_out\[114\]
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+ch_in\[141\]
+ch_in\[142\]
+ch_in\[143\]
+ch_in\[144\]
+ch_in\[145\]
+ch_in\[146\]
+ch_in\[147\]
+ch_in\[148\]
+ch_in\[149\]
+ch_in\[150\]
+ch_in\[151\]
+ch_in\[152\]
+ch_in\[153\]
+ch_in\[154\]
+ch_in\[155\]
+ch_in\[156\]
+ch_in\[157\]
+ch_in\[158\]
+ch_in\[159\]
+ch_in\[160\]
+ch_in\[161\]
+ch_in\[162\]
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+ch_in\[164\]
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+ch_in\[166\]
+ch_in\[167\]
+ch_in\[168\]
+ch_in\[169\]
+ch_in\[170\]
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+ch_in\[172\]
+ch_in\[173\]
+ch_in\[174\]
+ch_in\[175\]
+ch_in\[176\]
+ch_in\[177\]
+ch_in\[178\]
+ch_in\[179\]
+ch_in\[180\]
+ch_in\[181\]
+ch_in\[182\]
+ch_in\[183\]
+ch_in\[184\]
+ch_in\[185\]
+ch_in\[186\]
+ch_in\[187\]
+
+ch_in\[188\] 2200 0 4
+ch_in\[189\]
+ch_in\[190\]
+ch_in\[191\]
+ch_in\[192\]
+ch_in\[193\]
+ch_in\[194\]
+ch_in\[195\]
+ch_in\[196\]
+ch_in\[197\]
+ch_in\[198\]
+ch_in\[199\]
+ch_in\[200\]
+ch_in\[201\]
+ch_in\[202\]
+ch_in\[203\]
+ch_in\[204\]
+ch_in\[205\]
+ch_in\[206\]
+ch_in\[207\]
+ch_in\[208\]
+ch_in\[209\]
+ch_in\[210\]
+ch_in\[211\]
+ch_in\[212\]
+ch_in\[213\]
+ch_in\[214\]
+ch_in\[215\]
+ch_in\[216\]
+ch_in\[217\]
+ch_in\[218\]
+ch_in\[219\]
+
+ch_in\[220\] 2400 0 4
+ch_in\[221\]
+ch_in\[222\]
+ch_in\[223\]
+ch_in\[224\]
+ch_in\[225\]
+ch_in\[226\]
+ch_in\[227\]
+ch_in\[228\]
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+ch_in\[231\]
+ch_in\[232\]
+ch_in\[233\]
+ch_in\[234\]
+ch_in\[235\]
+ch_in\[236\]
+ch_in\[237\]
+ch_in\[238\]
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+ch_in\[245\]
+ch_in\[246\]
+ch_in\[247\]
+ch_in\[248\]
+ch_in\[249\]
+ch_in\[250\]
+ch_in\[251\]
+ch_out\[252\]
+
+
+#S
+ch_in\[0\] 0 0 16
+ch_in\[1\]
+ch_out\[2\]
+ch_in\[3\]
+ch_in\[4\]
+ch_in\[5\]
+ch_in\[6\]
+ch_in\[7\]
+ch_out\[8\]
+ch_in\[9\]
+ch_in\[10\]
+ch_in\[11\]
+ch_out\[12\]
+ch_in\[13\]
+ch_in\[14\]
+ch_in\[15\]
+ch_out\[16\]
+ch_in\[17\]
+ch_in\[18\]
+ch_in\[19\]
+ch_out\[20\]
+ch_in\[21\]
+ch_in\[22\]
+ch_in\[23\]
+ch_out\[24\]
+ch_in\[25\]
+ch_in\[26\]
+ch_out\[27\]
+ch_in\[28\]
+ch_in\[29\]
+ch_out\[30\]
+ch_in\[31\]
+ch_in\[32\]
+ch_out\[33\]
+ch_in\[34\]
+ch_in\[35\]
+ch_out\[36\]
+ch_in\[37\]
+ch_in\[38\]
+ch_out\[39\]
+ch_in\[40\]
+ch_in\[41\]
+ch_out\[42\]
+ch_in\[43\]
+ch_in\[44\]
+ch_out\[45\]
+ch_in\[46\]
+ch_in\[47\]
+ch_out\[48\]
+ch_in\[49\]
+ch_in\[50\]
+ch_out\[51\]
+ch_in\[52\]
+ch_in\[53\]
+ch_out\[54\]
+ch_in\[55\]
+ch_in\[56\]
+ch_out\[57\]
+ch_in\[58\]
+ch_in\[59\]
+ch_out\[60\]
+ch_in\[61\]
+ch_in\[62\]
+ch_out\[63\]
+ch_in\[64\]
+ch_in\[65\]
+ch_out\[66\]
+ch_in\[67\]
+ch_in\[68\]
+ch_out\[69\]
+ch_in\[70\]
+ch_in\[71\]
+ch_out\[72\]
+ch_in\[73\]
+ch_in\[74\]
+ch_out\[75\]
+ch_in\[76\]
+ch_in\[77\]
+ch_out\[78\]
+ch_in\[79\]
+ch_in\[80\]
+ch_out\[81\]
+ch_in\[82\]
+ch_in\[83\]
+ch_out\[84\]
+ch_in\[85\]
+ch_in\[86\]
+ch_out\[87\]
+ch_in\[88\]
+ch_in\[89\]
+ch_out\[90\]
+ch_in\[91\]
+ch_in\[92\]
+ch_out\[93\]
+ch_in\[94\]
+ch_in\[95\]
+ch_out\[96\]
+ch_in\[97\]
+ch_in\[98\]
+ch_out\[99\]
+ch_in\[100\]
+ch_in\[101\]
+ch_out\[102\]
+ch_in\[103\]
+ch_in\[104\]
+ch_out\[105\]
+
+
+ch_in\[106\] 600 0 32
+ch_out\[107\]
+ch_in\[108\]
+ch_out\[109\]
+ch_in\[110\]
+ch_out\[111\]
+ch_in\[112\]
+ch_out\[113\]
+ch_in\[114\]
+ch_out\[115\]
+ch_in\[116\]
+ch_out\[117\]
+ch_in\[118\]
+ch_out\[119\]
+ch_in\[120\]
+ch_out\[121\]
+ch_in\[122\]
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+ch_out\[125\]
+
+ch_in\[126\] 810 0 32
+ch_out\[127\]
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+
+
+ch_out\[142\] 1100 0 32
+ch_out\[143\]
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+
+ch_out\[188\] 1800 0 32
+ch_out\[189\]
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+ch_out\[251\]
+ch_in\[252\]
+
diff --git a/openlane/bus_rep_west/config.tcl b/openlane/bus_rep_west/config.tcl
new file mode 100755
index 0000000..7cae84a
--- /dev/null
+++ b/openlane/bus_rep_west/config.tcl
@@ -0,0 +1,134 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) bus_rep_west
+
+
+set ::env(DESIGN_IS_CORE) "1"
+set ::env(FP_PDN_CORE_RING) {1}
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_NET) ""
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/bus_rep/bus_rep_west.sv \
+ "
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=42 "
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+#set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 3250 50"
+
+#set ::env(GRT_OBS) "met4 0 0 300 1725"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.20"
+set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) 0.2
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+## CTS
+set ::env(CLOCK_TREE_SYNTH) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0"
+
+## Routing
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+#set ::env(GLB_RT_MAXLAYER) 3
+set ::env(RT_MAX_LAYER) {met3}
+set ::env(FP_PDN_LOWER_LAYER) {met2}
+set ::env(FP_PDN_UPPER_LAYER) {met3}
+
+set ::env(FP_IO_HLAYER) {met2}
+set ::env(FP_IO_VLAYER) {met1}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+## Placement
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "500"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0"
+
+set ::env(ECO_ENABLE) {0}
+#set ::env(CURRENT_STEP) "synthesis"
+#set ::env(LAST_STEP) "parasitics_sta"
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/bus_rep_west/interactive.tcl b/openlane/bus_rep_west/interactive.tcl
new file mode 100755
index 0000000..5b5c6c8
--- /dev/null
+++ b/openlane/bus_rep_west/interactive.tcl
@@ -0,0 +1,337 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+proc run_placement_step {args} {
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+ if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+ remove_buffers_from_nets
+ }
+}
+
+proc run_routing_step {args} {
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ if { $::env(ECO_ENABLE) == 0 } {
+ run_routing
+ }
+}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+ run_parasitics_sta
+ }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_irdrop_report_step {args} {
+ if { $::env(RUN_IRDROP_REPORT) } {
+ run_irdrop_report
+ }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_erc_step {args} {
+ if { $::env(RUN_CVC) } {
+ run_erc
+ }
+}
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
+}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
+proc run_post_run_hooks {} {
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
+}
+
+proc run_floorplan {args} {
+ # |----------------------------------------------------|
+ # |---------------- 2. FLOORPLAN ------------------|
+ # |----------------------------------------------------|
+ #
+ # intial fp
+ init_floorplan
+
+ # check for deprecated io variables
+ if { [info exists ::env(FP_IO_HMETAL)]} {
+ set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+ puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+ }
+
+ if { [info exists ::env(FP_IO_VMETAL)]} {
+ set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+ puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+ }
+
+
+ # place io
+ if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+ place_io_ol
+ } else {
+ if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+ place_io
+ global_placement_or
+ place_contextualized_io \
+ -lef $::env(FP_CONTEXT_LEF) \
+ -def $::env(FP_CONTEXT_DEF)
+ } else {
+ place_io
+ }
+ }
+
+ apply_def_template
+
+ #if { [info exist ::env(EXTRA_LEFS)] } {
+ if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+ file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+ manual_macro_placement -f
+ } else {
+ # global_placement_or
+ # basic_macro_placement
+ }
+ #}
+
+ if { $::env(RUN_TAP_DECAP_INSERTION) } {
+ tap_decap_or
+ }
+
+ scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
+
+ run_power_grid_generation
+}
+
+
+
+proc run_flow {args} {
+ set options {
+ {-design optional}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+ # signal trap SIGINT save_state;
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ load_overrides $arg_values(-override_env)
+ }
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 1
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+ set steps [dict create \
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "irdrop" "run_irdrop_report_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
+ ]
+
+ if { [info exists arg_values(-from) ]} {
+ puts_info "Starting flow at $arg_values(-from)..."
+ set ::env(CURRENT_STEP) $arg_values(-from)
+ } elseif { [info exists ::env(CURRENT_STEP) ] } {
+ puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+ } else {
+ set ::env(CURRENT_STEP) "synthesis"
+ }
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+ set_if_unset arg_values(-to) "cvc"
+
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ # Saves to <RUN_DIR>/results/final
+ save_final_views
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/bus_rep_west/macro.cfg b/openlane/bus_rep_west/macro.cfg
new file mode 100644
index 0000000..5bd9eb4
--- /dev/null
+++ b/openlane/bus_rep_west/macro.cfg
@@ -0,0 +1,42 @@
+u_rp\[0\].u_buf 7.82 10.88 FN
+u_rp\[1\].u_buf 85.1 10.88 FN
+u_rp\[2\].u_buf 162.38 10.88 FN
+u_rp\[3\].u_buf 239.66 10.88 FN
+u_rp\[4\].u_buf 316.94 10.88 FN
+u_rp\[5\].u_buf 394.22 10.88 FN
+u_rp\[6\].u_buf 471.5 10.88 FN
+u_rp\[7\].u_buf 548.78 10.88 FN
+u_rp\[8\].u_buf 626.06 10.88 FN
+u_rp\[9\].u_buf 703.34 10.88 FN
+u_rp\[10\].u_buf 780.62 10.88 FN
+u_rp\[11\].u_buf 857.9 10.88 FN
+u_rp\[12\].u_buf 935.18 10.88 FN
+u_rp\[13\].u_buf 1012.46 10.88 FN
+u_rp\[14\].u_buf 1089.74 10.88 FN
+u_rp\[15\].u_buf 1167.02 10.88 FN
+u_rp\[16\].u_buf 1244.3 10.88 FN
+u_rp\[17\].u_buf 1321.58 10.88 FN
+u_rp\[18\].u_buf 1398.86 10.88 FN
+u_rp\[19\].u_buf 1476.14 10.88 FN
+u_rp\[20\].u_buf 1553.42 10.88 FN
+u_rp\[21\].u_buf 1630.7 10.88 FN
+u_rp\[22\].u_buf 1707.98 10.88 FN
+u_rp\[23\].u_buf 1785.26 10.88 FN
+u_rp\[24\].u_buf 1862.54 10.88 FN
+u_rp\[25\].u_buf 1939.82 10.88 FN
+u_rp\[26\].u_buf 2017.1 10.88 FN
+u_rp\[27\].u_buf 2094.38 10.88 FN
+u_rp\[28\].u_buf 2171.66 10.88 FN
+u_rp\[29\].u_buf 2248.94 10.88 FN
+u_rp\[30\].u_buf 2326.22 10.88 FN
+u_rp\[31\].u_buf 2403.5 10.88 FN
+u_rp\[32\].u_buf 2480.78 10.88 FN
+u_rp\[33\].u_buf 2558.06 10.88 FN
+u_rp\[34\].u_buf 2635.34 10.88 FN
+u_rp\[35\].u_buf 2712.62 10.88 FN
+u_rp\[36\].u_buf 2789.9 10.88 FN
+u_rp\[37\].u_buf 2867.18 10.88 FN
+u_rp\[38\].u_buf 2944.46 10.88 FN
+u_rp\[39\].u_buf 3021.74 10.88 FN
+u_rp\[40\].u_buf 3099.02 10.88 FN
+u_rp\[41\].u_buf 3176.3 10.88 FN
diff --git a/openlane/uart_i2cm_usb_spi_top/pdn.tcl b/openlane/bus_rep_west/pdn.tcl
similarity index 100%
copy from openlane/uart_i2cm_usb_spi_top/pdn.tcl
copy to openlane/bus_rep_west/pdn.tcl
diff --git a/openlane/bus_rep_west/pin_order.cfg b/openlane/bus_rep_west/pin_order.cfg
new file mode 100644
index 0000000..74e6240
--- /dev/null
+++ b/openlane/bus_rep_west/pin_order.cfg
@@ -0,0 +1,91 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#S
+ch_in\[0\] 0 0 225
+ch_out\[1\]
+ch_out\[2\]
+ch_in\[3\]
+ch_out\[4\]
+ch_out\[5\]
+ch_in\[6\]
+ch_out\[7\]
+ch_out\[8\]
+ch_in\[9\]
+ch_out\[10\]
+ch_out\[11\]
+ch_in\[12\]
+ch_out\[13\]
+ch_out\[14\]
+ch_in\[15\]
+ch_out\[16\]
+ch_out\[17\]
+ch_in\[18\]
+ch_out\[19\]
+ch_out\[20\]
+ch_in\[21\]
+ch_out\[22\]
+ch_out\[23\]
+ch_in\[24\]
+ch_out\[25\]
+ch_out\[26\]
+ch_in\[27\]
+ch_out\[28\]
+ch_out\[29\]
+ch_in\[30\]
+ch_out\[31\]
+ch_out\[32\]
+ch_in\[33\]
+ch_out\[34\]
+ch_out\[35\]
+ch_in\[36\]
+ch_out\[37\]
+ch_out\[38\]
+ch_in\[39\]
+ch_out\[40\]
+ch_out\[41\]
+
+#N
+ch_out\[0\] 100 0 4
+ch_in\[1\]
+ch_in\[2\]
+ch_out\[3\]
+ch_in\[4\]
+ch_in\[5\]
+ch_out\[6\]
+ch_in\[7\]
+ch_in\[8\]
+ch_out\[9\]
+ch_in\[10\]
+ch_in\[11\]
+ch_out\[12\]
+ch_in\[13\]
+ch_in\[14\]
+ch_out\[15\]
+ch_in\[16\]
+ch_in\[17\]
+ch_out\[18\]
+ch_in\[19\]
+ch_in\[20\]
+ch_out\[21\]
+ch_in\[22\]
+ch_in\[23\]
+ch_out\[24\]
+ch_in\[25\]
+ch_in\[26\]
+ch_out\[27\]
+ch_in\[28\]
+ch_in\[29\]
+ch_out\[30\]
+ch_in\[31\]
+ch_in\[32\]
+ch_out\[33\]
+ch_in\[34\]
+ch_in\[35\]
+ch_out\[36\]
+ch_in\[37\]
+ch_in\[38\]
+ch_out\[39\]
+ch_in\[40\]
+ch_in\[41\]
diff --git a/openlane/dg_pll/base.sdc b/openlane/dg_pll/base.sdc
new file mode 100644
index 0000000..b10a47b
--- /dev/null
+++ b/openlane/dg_pll/base.sdc
@@ -0,0 +1,28 @@
+current_design dg_pll
+
+create_clock [get_pins {"ringosc.ibufp01/Y"} ] -name "pll_control_clock" -period 6.6666666666667
+
+set_propagated_clock [get_clocks {pll_control_clock}]
+
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+set_max_transition 1.00 [current_design]
+set_max_capacitance 0.2 [current_design]
+set_max_fanout 10 [current_design]
diff --git a/openlane/dg_pll/config.tcl b/openlane/dg_pll/config.tcl
new file mode 100644
index 0000000..ab632d6
--- /dev/null
+++ b/openlane/dg_pll/config.tcl
@@ -0,0 +1,94 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) dg_pll
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/dg_pll/src/dg_pll.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/dg_pll/src/digital_pll_controller.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/dg_pll/src/ring_osc2x13.v"
+
+set ::env(CLOCK_PORT) ""
+set ::env(CLOCK_TREE_SYNTH) 0
+
+# Synthesis
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(SYNTH_BUFFERING) 0
+set ::env(SYNTH_SIZING) 0
+
+# Timing configuration
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+## Floorplan
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 90 100"
+set ::env(GRT_OBS) "met4 0 0 90 100"
+
+
+#set ::env(TOP_MARGIN_MULT) 2
+#set ::env(BOTTOM_MARGIN_MULT) 2
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+
+set ::env(CELL_PAD) 0
+
+## PDN
+set ::env(FP_PDN_VPITCH) 40
+set ::env(FP_PDN_HPITCH) 40
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+set ::env(FP_PDN_VOFFSET) "5"
+set ::env(FP_PDN_HOFFSET) "5"
+set ::env(FP_PDN_HSPACING) {13.8}
+set ::env(FP_PDN_VSPACING) {13.8}
+set ::env(FP_PDN_HORIZONTAL_HALO) "10"
+set ::env(FP_PDN_VERTICAL_HALO) "10"
+
+## Placement
+set ::env(PL_TARGET_DENSITY) 0.82
+
+
+## Routing
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+set ::env(DIODE_INSERTION_STRATEGY) 0
+#set ::env(FILL_INSERTION) 0
+#set ::env(TAP_DECAP_INSERTION) 0
+set ::env(CLOCK_TREE_SYNTH) 0
+
+## Diode Insertion
+#set ::env(DIODE_INSERTION_STRATEGY) "4"
+
+
diff --git a/openlane/dg_pll/interactive.tcl b/openlane/dg_pll/interactive.tcl
new file mode 100755
index 0000000..5b5c6c8
--- /dev/null
+++ b/openlane/dg_pll/interactive.tcl
@@ -0,0 +1,337 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+proc run_placement_step {args} {
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+ if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+ remove_buffers_from_nets
+ }
+}
+
+proc run_routing_step {args} {
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ if { $::env(ECO_ENABLE) == 0 } {
+ run_routing
+ }
+}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+ run_parasitics_sta
+ }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_irdrop_report_step {args} {
+ if { $::env(RUN_IRDROP_REPORT) } {
+ run_irdrop_report
+ }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_erc_step {args} {
+ if { $::env(RUN_CVC) } {
+ run_erc
+ }
+}
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
+}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
+proc run_post_run_hooks {} {
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
+}
+
+proc run_floorplan {args} {
+ # |----------------------------------------------------|
+ # |---------------- 2. FLOORPLAN ------------------|
+ # |----------------------------------------------------|
+ #
+ # intial fp
+ init_floorplan
+
+ # check for deprecated io variables
+ if { [info exists ::env(FP_IO_HMETAL)]} {
+ set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+ puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+ }
+
+ if { [info exists ::env(FP_IO_VMETAL)]} {
+ set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+ puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+ }
+
+
+ # place io
+ if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+ place_io_ol
+ } else {
+ if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+ place_io
+ global_placement_or
+ place_contextualized_io \
+ -lef $::env(FP_CONTEXT_LEF) \
+ -def $::env(FP_CONTEXT_DEF)
+ } else {
+ place_io
+ }
+ }
+
+ apply_def_template
+
+ #if { [info exist ::env(EXTRA_LEFS)] } {
+ if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+ file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+ manual_macro_placement -f
+ } else {
+ # global_placement_or
+ # basic_macro_placement
+ }
+ #}
+
+ if { $::env(RUN_TAP_DECAP_INSERTION) } {
+ tap_decap_or
+ }
+
+ scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
+
+ run_power_grid_generation
+}
+
+
+
+proc run_flow {args} {
+ set options {
+ {-design optional}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+ # signal trap SIGINT save_state;
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ load_overrides $arg_values(-override_env)
+ }
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 1
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+ set steps [dict create \
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "irdrop" "run_irdrop_report_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
+ ]
+
+ if { [info exists arg_values(-from) ]} {
+ puts_info "Starting flow at $arg_values(-from)..."
+ set ::env(CURRENT_STEP) $arg_values(-from)
+ } elseif { [info exists ::env(CURRENT_STEP) ] } {
+ puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+ } else {
+ set ::env(CURRENT_STEP) "synthesis"
+ }
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+ set_if_unset arg_values(-to) "cvc"
+
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ # Saves to <RUN_DIR>/results/final
+ save_final_views
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/dg_pll/macro.cfg b/openlane/dg_pll/macro.cfg
new file mode 100644
index 0000000..927d153
--- /dev/null
+++ b/openlane/dg_pll/macro.cfg
@@ -0,0 +1,110 @@
+
+ringosc.iss.reseten0 7.82 10.88 FN
+ringosc.iss.ctrlen0 14.72 10.88 FN
+ringosc.iss.const1 19.78 10.88 FN
+
+ringosc.iss.delaybuf0 7.82 13.60 S
+ringosc.iss.delayen1 11.5 13.60 S
+ringosc.iss.delayint0 19.78 13.60 FS
+ringosc.iss.delayenb1 7.82 16.32 FN
+ringosc.iss.delayen0 13.34 16.32 FN
+ringosc.iss.delayenb0 19.78 16.32 FN
+
+ringosc.dstage\[0\].id.delaybuf0 7.82 19.04 FS
+ringosc.dstage\[0\].id.delaybuf1 11.5 19.04 S
+ringosc.dstage\[0\].id.delayen1 14.72 19.04 S
+ringosc.dstage\[0\].id.delayint0 20.24 19.04 FS
+ringosc.dstage\[0\].id.delayenb1 7.82 21.76 FN
+ringosc.dstage\[0\].id.delayen0 13.34 21.76 FN
+ringosc.dstage\[0\].id.delayenb0 19.78 21.76 FN
+
+ringosc.dstage\[1\].id.delaybuf0 7.82 24.48 FS
+ringosc.dstage\[1\].id.delaybuf1 11.5 24.48 S
+ringosc.dstage\[1\].id.delayen1 14.72 24.48 S
+ringosc.dstage\[1\].id.delayint0 20.24 24.48 FS
+ringosc.dstage\[1\].id.delayenb1 7.82 27.2 FN
+ringosc.dstage\[1\].id.delayen0 13.34 27.2 FN
+ringosc.dstage\[1\].id.delayenb0 19.78 27.2 FN
+
+ringosc.dstage\[2\].id.delaybuf0 7.82 29.92 FS
+ringosc.dstage\[2\].id.delaybuf1 11.5 29.92 S
+ringosc.dstage\[2\].id.delayen1 14.72 29.92 S
+ringosc.dstage\[2\].id.delayint0 20.24 29.92 FS
+ringosc.dstage\[2\].id.delayenb1 7.82 32.64 FN
+ringosc.dstage\[2\].id.delayen0 13.34 32.64 FN
+ringosc.dstage\[2\].id.delayenb0 19.78 32.64 FN
+
+ringosc.dstage\[3\].id.delaybuf0 7.82 35.36 FS
+ringosc.dstage\[3\].id.delaybuf1 11.5 35.36 S
+ringosc.dstage\[3\].id.delayen1 14.72 35.36 S
+ringosc.dstage\[3\].id.delayint0 20.24 35.36 FS
+ringosc.dstage\[3\].id.delayenb1 7.82 38.08 FN
+ringosc.dstage\[3\].id.delayen0 13.34 38.08 FN
+ringosc.dstage\[3\].id.delayenb0 19.78 38.08 FN
+
+ringosc.dstage\[4\].id.delaybuf0 7.82 40.8 FS
+ringosc.dstage\[4\].id.delaybuf1 11.5 40.8 S
+ringosc.dstage\[4\].id.delayen1 14.72 40.8 S
+ringosc.dstage\[4\].id.delayint0 20.24 40.8 FS
+ringosc.dstage\[4\].id.delayenb1 7.82 43.52 FN
+ringosc.dstage\[4\].id.delayen0 13.34 43.52 FN
+ringosc.dstage\[4\].id.delayenb0 19.78 43.52 FN
+
+ringosc.dstage\[5\].id.delaybuf0 7.82 46.24 FS
+ringosc.dstage\[5\].id.delaybuf1 11.5 46.24 S
+ringosc.dstage\[5\].id.delayen1 14.72 46.24 S
+ringosc.dstage\[5\].id.delayint0 20.24 46.24 FS
+ringosc.dstage\[5\].id.delayenb1 7.82 48.96 FN
+ringosc.dstage\[5\].id.delayen0 13.34 48.96 FN
+ringosc.dstage\[5\].id.delayenb0 19.78 48.96 FN
+
+ringosc.dstage\[6\].id.delaybuf0 31.74 48.96 FN
+ringosc.dstage\[6\].id.delaybuf1 35.42 48.96 N
+ringosc.dstage\[6\].id.delayen1 38.64 48.96 N
+ringosc.dstage\[6\].id.delayint0 45.54 48.96 FN
+ringosc.dstage\[6\].id.delayenb1 32.66 46.24 FS
+ringosc.dstage\[6\].id.delayen0 38.18 46.24 FS
+ringosc.dstage\[6\].id.delayenb0 44.62 46.24 FS
+
+ringosc.dstage\[7\].id.delaybuf0 31.74 43.52 FN
+ringosc.dstage\[7\].id.delaybuf1 35.42 43.52 N
+ringosc.dstage\[7\].id.delayen1 38.64 43.52 N
+ringosc.dstage\[7\].id.delayint0 45.54 43.52 FN
+ringosc.dstage\[7\].id.delayenb1 32.66 40.8 FS
+ringosc.dstage\[7\].id.delayen0 38.18 40.8 FS
+ringosc.dstage\[7\].id.delayenb0 44.62 40.8 FS
+
+ringosc.dstage\[8\].id.delaybuf0 31.74 38.08 FN
+ringosc.dstage\[8\].id.delaybuf1 35.42 38.08 N
+ringosc.dstage\[8\].id.delayen1 38.64 38.08 N
+ringosc.dstage\[8\].id.delayint0 45.54 38.08 FN
+ringosc.dstage\[8\].id.delayenb1 32.66 35.36 FS
+ringosc.dstage\[8\].id.delayen0 38.18 35.36 FS
+ringosc.dstage\[8\].id.delayenb0 44.62 35.36 FS
+
+ringosc.dstage\[9\].id.delaybuf0 31.74 32.64 FN
+ringosc.dstage\[9\].id.delaybuf1 35.42 32.64 N
+ringosc.dstage\[9\].id.delayen1 38.64 32.64 N
+ringosc.dstage\[9\].id.delayint0 45.54 32.64 FN
+ringosc.dstage\[9\].id.delayenb1 32.66 29.92 FS
+ringosc.dstage\[9\].id.delayen0 38.18 29.92 FS
+ringosc.dstage\[9\].id.delayenb0 44.62 29.92 FS
+
+ringosc.dstage\[10\].id.delaybuf0 31.74 27.2 FN
+ringosc.dstage\[10\].id.delaybuf1 35.42 27.2 N
+ringosc.dstage\[10\].id.delayen1 38.64 27.2 N
+ringosc.dstage\[10\].id.delayint0 45.54 27.2 FN
+ringosc.dstage\[10\].id.delayenb1 32.66 24.48 FS
+ringosc.dstage\[10\].id.delayen0 38.18 24.48 FS
+ringosc.dstage\[10\].id.delayenb0 44.62 24.48 FS
+
+ringosc.dstage\[11\].id.delaybuf0 31.74 21.76 FN
+ringosc.dstage\[11\].id.delaybuf1 35.42 21.76 N
+ringosc.dstage\[11\].id.delayen1 38.64 21.76 N
+ringosc.dstage\[11\].id.delayint0 45.54 21.76 FN
+ringosc.dstage\[11\].id.delayenb1 32.66 19.04 FS
+ringosc.dstage\[11\].id.delayen0 38.18 19.04 FS
+ringosc.dstage\[11\].id.delayenb0 44.62 19.04 FS
+
+
+
diff --git a/openlane/dg_pll/pin_order.cfg b/openlane/dg_pll/pin_order.cfg
new file mode 100644
index 0000000..247fd42
--- /dev/null
+++ b/openlane/dg_pll/pin_order.cfg
@@ -0,0 +1,49 @@
+
+#BUS_SORT
+#MANUAL_PLACE
+
+#N
+ext_trim\[7\]
+ext_trim\[8\]
+ext_trim\[9\]
+ext_trim\[19\]
+ext_trim\[18\]
+ext_trim\[17\]
+ext_trim\[16\]
+ext_trim\[15\]
+ext_trim\[14\]
+ext_trim\[13\]
+ext_trim\[12\]
+ext_trim\[11\]
+ext_trim\[10\]
+
+#E
+ext_trim\[25\]
+ext_trim\[24\]
+ext_trim\[23\]
+ext_trim\[22\]
+ext_trim\[21\]
+ext_trim\[20\]
+
+#W
+clockp\[1\]
+clockp\[0\]
+div\[4\]
+div\[3\]
+div\[2\]
+div\[1\]
+div\[0\]
+enable
+dco
+ext_trim\[6\]
+ext_trim\[5\]
+ext_trim\[4\]
+ext_trim\[3\]
+ext_trim\[2\]
+ext_trim\[1\]
+ext_trim\[0\]
+
+#S
+resetb
+osc
+
diff --git a/openlane/peri_top/base.sdc b/openlane/peri_top/base.sdc
new file mode 100644
index 0000000..d3b6015
--- /dev/null
+++ b/openlane/peri_top/base.sdc
@@ -0,0 +1,216 @@
+###############################################################################
+# Created by write_sdc
+# Wed Dec 7 16:59:07 2022
+###############################################################################
+current_design peri_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+create_clock -name rtc_clk -period 100.0000 [get_ports {rtc_clk}]
+
+set_clock_groups \
+ -name clock_group \
+ -logically_exclusive \
+ -group [get_clocks {mclk}]\
+ -group [get_clocks {rtc_clk}]\
+ -comment {Async Clock group}
+
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty 0.2500 [all_clocks]
+set_propagated_clock [all_clocks]
+
+#set_dont_touch { u_skew_peri.* }
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+### ClkSkew Adjust
+set_case_analysis 0 [get_ports {cfg_cska_peri[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[3]}]
+
+set_max_delay 3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay 2 -to [get_ports {wbd_clk_peri}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_peri
+
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {s_reset_n}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {s_reset_n}]
+
+## RTC - Sys Clk
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+
+### DAC I/F
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac0_mux_sel[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac1_mux_sel[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac2_mux_sel[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac3_mux_sel[*]}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac0_mux_sel[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac1_mux_sel[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac2_mux_sel[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac3_mux_sel[*]}]
+
+### RTC clock domain
+set_output_delay -max 6.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_date_d}]
+set_output_delay -max 6.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_time_s}]
+set_output_delay -max 6.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {rtc_intr}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_date_d}]
+set_output_delay -min 1.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_time_s}]
+set_output_delay -min 1.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {rtc_intr}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {inc_date_d}]
+set_load -pin_load 0.0334 [get_ports {inc_time_s}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {rtc_intr}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_peri}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/openlane/peri_top/config.tcl b/openlane/peri_top/config.tcl
new file mode 100755
index 0000000..ec9157d
--- /dev/null
+++ b/openlane/peri_top/config.tcl
@@ -0,0 +1,153 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) peri_top
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk rtc_clk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/rtc/verilog/rtl/core/rtc_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/rtc/verilog/rtl/core/rtc_core.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/rtc/verilog/rtl/core/rtc_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/peripheral/src/peri_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/dig2ana/src/dig2ana_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_reg_bus.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/nec_ir/src/nec_ir_rx.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/nec_ir/src/nec_ir_frame_decoder.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/nec_ir/src/nec_ir_event_catcher.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/nec_ir/src/nec_ir_regs.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/nec_ir/src/nec_div8.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/nec_ir/src/nec_ir_tx.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/nec_ir/src/nec_ir_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_fifo_occ.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/prescaler.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/metastability_filter.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_filter.sv \
+ "
+
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/ ]
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+#set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 400 400"
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+#set ::env(RSZ_DONT_TOUCH_RX) { u_skew_peri.* }
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.42"
+set ::env(CELL_PAD) "8"
+#set ::env(GRT_ADJUSTMENT) {0.2}
+
+
+######################################################################################
+# Metal-2/3 Signal are Routed near to block boundary is creating DRC violation at Top-level
+# during pad connectivity
+
+#set ::env(GRT_OBS) " \
+# met2 0 2 500 3, \
+# met2 0 747 500 748, \
+# met3 2 0 3 750, \
+# met3 497 0 498 750"
+
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "1"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {0}
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/peri_top/interactive.tcl b/openlane/peri_top/interactive.tcl
new file mode 100755
index 0000000..5b5c6c8
--- /dev/null
+++ b/openlane/peri_top/interactive.tcl
@@ -0,0 +1,337 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+proc run_placement_step {args} {
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+ if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+ remove_buffers_from_nets
+ }
+}
+
+proc run_routing_step {args} {
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ if { $::env(ECO_ENABLE) == 0 } {
+ run_routing
+ }
+}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+ run_parasitics_sta
+ }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_irdrop_report_step {args} {
+ if { $::env(RUN_IRDROP_REPORT) } {
+ run_irdrop_report
+ }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_erc_step {args} {
+ if { $::env(RUN_CVC) } {
+ run_erc
+ }
+}
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
+}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
+proc run_post_run_hooks {} {
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
+}
+
+proc run_floorplan {args} {
+ # |----------------------------------------------------|
+ # |---------------- 2. FLOORPLAN ------------------|
+ # |----------------------------------------------------|
+ #
+ # intial fp
+ init_floorplan
+
+ # check for deprecated io variables
+ if { [info exists ::env(FP_IO_HMETAL)]} {
+ set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
+ puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
+ }
+
+ if { [info exists ::env(FP_IO_VMETAL)]} {
+ set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
+ puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
+ puts_warn "We recommend you update your configuration as follows:"
+ puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
+ }
+
+
+ # place io
+ if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+ place_io_ol
+ } else {
+ if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+ place_io
+ global_placement_or
+ place_contextualized_io \
+ -lef $::env(FP_CONTEXT_LEF) \
+ -def $::env(FP_CONTEXT_DEF)
+ } else {
+ place_io
+ }
+ }
+
+ apply_def_template
+
+ #if { [info exist ::env(EXTRA_LEFS)] } {
+ if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+ file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
+ manual_macro_placement -f
+ } else {
+ # global_placement_or
+ # basic_macro_placement
+ }
+ #}
+
+ if { $::env(RUN_TAP_DECAP_INSERTION) } {
+ tap_decap_or
+ }
+
+ scrot_klayout -layout $::env(CURRENT_DEF) -log $::env(floorplan_logs)/screenshot.log
+
+ run_power_grid_generation
+}
+
+
+
+proc run_flow {args} {
+ set options {
+ {-design optional}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+ # signal trap SIGINT save_state;
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ load_overrides $arg_values(-override_env)
+ }
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 1
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+ set steps [dict create \
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "irdrop" "run_irdrop_report_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
+ ]
+
+ if { [info exists arg_values(-from) ]} {
+ puts_info "Starting flow at $arg_values(-from)..."
+ set ::env(CURRENT_STEP) $arg_values(-from)
+ } elseif { [info exists ::env(CURRENT_STEP) ] } {
+ puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+ } else {
+ set ::env(CURRENT_STEP) "synthesis"
+ }
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+ set_if_unset arg_values(-to) "cvc"
+
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ # Saves to <RUN_DIR>/results/final
+ save_final_views
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/peri_top/macro.cfg b/openlane/peri_top/macro.cfg
new file mode 100644
index 0000000..443abfd
--- /dev/null
+++ b/openlane/peri_top/macro.cfg
@@ -0,0 +1,31 @@
+u_skew_peri.clkbuf_1.u_dly0 7.82 10.88 FN
+u_skew_peri.clkbuf_1.u_dly1 7.82 13.6 N
+u_skew_peri.clkbuf_2.u_dly0 7.82 19.04 N
+u_skew_peri.clkbuf_2.u_dly1 7.82 21.76 FN
+u_skew_peri.clkbuf_3.u_dly0 20.7 10.88 FN
+u_skew_peri.clkbuf_3.u_dly1 20.7 13.6 N
+u_skew_peri.clkbuf_4.u_dly0 20.7 19.04 N
+u_skew_peri.clkbuf_4.u_dly1 20.7 21.76 FN
+u_skew_peri.clkbuf_5.u_dly0 33.58 10.88 FN
+u_skew_peri.clkbuf_5.u_dly1 33.58 13.6 N
+u_skew_peri.clkbuf_6.u_dly0 33.58 19.04 N
+u_skew_peri.clkbuf_6.u_dly1 33.58 21.76 FN
+u_skew_peri.clkbuf_7.u_dly0 46.46 10.88 FN
+u_skew_peri.clkbuf_7.u_dly1 46.46 13.6 N
+u_skew_peri.clkbuf_8.u_dly0 46.46 19.04 N
+u_skew_peri.clkbuf_8.u_dly1 46.46 21.76 FN
+u_skew_peri.clkbuf_9.u_dly0 59.34 10.88 FN
+u_skew_peri.clkbuf_9.u_dly1 59.34 13.6 N
+u_skew_peri.clkbuf_10.u_dly0 59.34 19.04 N
+u_skew_peri.clkbuf_10.u_dly1 59.34 21.76 FN
+u_skew_peri.clkbuf_11.u_dly0 72.22 10.88 FN
+u_skew_peri.clkbuf_11.u_dly1 72.22 13.6 N
+u_skew_peri.clkbuf_12.u_dly0 72.22 19.04 N
+u_skew_peri.clkbuf_12.u_dly1 72.22 21.76 FN
+u_skew_peri.clkbuf_13.u_dly0 85.1 10.88 FN
+u_skew_peri.clkbuf_13.u_dly1 85.1 13.6 N
+u_skew_peri.clkbuf_14.u_dly0 85.1 19.04 N
+u_skew_peri.clkbuf_14.u_dly1 85.1 21.76 FN
+u_skew_peri.clkbuf_15.u_dly0 97.98 10.88 FN
+u_skew_peri.clkbuf_15.u_dly1 97.98 13.6 N
+
diff --git a/openlane/peri_top/pin_order.cfg b/openlane/peri_top/pin_order.cfg
new file mode 100644
index 0000000..59c656b
--- /dev/null
+++ b/openlane/peri_top/pin_order.cfg
@@ -0,0 +1,145 @@
+#BUS_SORT
+#MANUAL_PLACE
+
+#W
+s_reset_n
+mclk
+wbd_clk_int
+wbd_clk_peri
+cfg_cska_peri\[3\]
+cfg_cska_peri\[2\]
+cfg_cska_peri\[1\]
+cfg_cska_peri\[0\]
+
+cfg_dac3_mux_sel\[7\]
+cfg_dac3_mux_sel\[6\]
+cfg_dac3_mux_sel\[5\]
+cfg_dac3_mux_sel\[4\]
+cfg_dac3_mux_sel\[3\]
+cfg_dac3_mux_sel\[2\]
+cfg_dac3_mux_sel\[1\]
+cfg_dac3_mux_sel\[0\]
+
+cfg_dac2_mux_sel\[7\]
+cfg_dac2_mux_sel\[6\]
+cfg_dac2_mux_sel\[5\]
+cfg_dac2_mux_sel\[4\]
+cfg_dac2_mux_sel\[3\]
+cfg_dac2_mux_sel\[2\]
+cfg_dac2_mux_sel\[1\]
+cfg_dac2_mux_sel\[0\]
+
+cfg_dac1_mux_sel\[7\]
+cfg_dac1_mux_sel\[6\]
+cfg_dac1_mux_sel\[5\]
+cfg_dac1_mux_sel\[4\]
+cfg_dac1_mux_sel\[3\]
+cfg_dac1_mux_sel\[2\]
+cfg_dac1_mux_sel\[1\]
+cfg_dac1_mux_sel\[0\]
+
+cfg_dac0_mux_sel\[7\]
+cfg_dac0_mux_sel\[6\]
+cfg_dac0_mux_sel\[5\]
+cfg_dac0_mux_sel\[4\]
+cfg_dac0_mux_sel\[3\]
+cfg_dac0_mux_sel\[2\]
+cfg_dac0_mux_sel\[1\]
+cfg_dac0_mux_sel\[0\]
+
+
+#S
+rtc_clk 200 0 2
+rtc_intr
+inc_date_d
+inc_time_s
+ir_rx
+ir_tx
+ir_intr
+
+
+reg_cs 250 0 2
+reg_wr
+reg_addr\[10\]
+reg_addr\[9\]
+reg_addr\[8\]
+reg_addr\[7\]
+reg_addr\[6\]
+reg_addr\[5\]
+reg_addr\[4\]
+reg_addr\[3\]
+reg_addr\[2\]
+reg_addr\[1\]
+reg_addr\[0\]
+reg_be\[3\]
+reg_be\[2\]
+reg_be\[1\]
+reg_be\[0\]
+reg_wdata\[31\]
+reg_wdata\[30\]
+reg_wdata\[29\]
+reg_wdata\[28\]
+reg_wdata\[27\]
+reg_wdata\[26\]
+reg_wdata\[25\]
+reg_wdata\[24\]
+reg_wdata\[23\]
+reg_wdata\[22\]
+reg_wdata\[21\]
+reg_wdata\[20\]
+reg_wdata\[19\]
+reg_wdata\[18\]
+reg_wdata\[17\]
+reg_wdata\[16\]
+reg_wdata\[15\]
+reg_wdata\[14\]
+reg_wdata\[13\]
+reg_wdata\[12\]
+reg_wdata\[11\]
+reg_wdata\[10\]
+reg_wdata\[9\]
+reg_wdata\[8\]
+reg_wdata\[7\]
+reg_wdata\[6\]
+reg_wdata\[5\]
+reg_wdata\[4\]
+reg_wdata\[3\]
+reg_wdata\[2\]
+reg_wdata\[1\]
+reg_wdata\[0\]
+reg_rdata\[31\]
+reg_rdata\[30\]
+reg_rdata\[29\]
+reg_rdata\[28\]
+reg_rdata\[27\]
+reg_rdata\[26\]
+reg_rdata\[25\]
+reg_rdata\[24\]
+reg_rdata\[23\]
+reg_rdata\[22\]
+reg_rdata\[21\]
+reg_rdata\[20\]
+reg_rdata\[19\]
+reg_rdata\[18\]
+reg_rdata\[17\]
+reg_rdata\[16\]
+reg_rdata\[15\]
+reg_rdata\[14\]
+reg_rdata\[13\]
+reg_rdata\[12\]
+reg_rdata\[11\]
+reg_rdata\[10\]
+reg_rdata\[9\]
+reg_rdata\[8\]
+reg_rdata\[7\]
+reg_rdata\[6\]
+reg_rdata\[5\]
+reg_rdata\[4\]
+reg_rdata\[3\]
+reg_rdata\[2\]
+reg_rdata\[1\]
+reg_rdata\[0\]
+reg_ack
+
+
+
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index 3900d26..a60c4f4 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -30,6 +30,7 @@
set ::env(CLOCK_PORT) "mclk"
set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
## CTS BUFFER
set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
@@ -45,6 +46,7 @@
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_top.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pseudorandom.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/gpio/src/gpio_top.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/gpio/src/gpio_reg.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/gpio/src/gpio_intr.sv \
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index 811a5cf..f7ea26f 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -69,7 +69,6 @@
int_pll_clock
xtal_clk
s_reset_n
-rtc_clk
usb_clk
pinmux_debug\[0\] 0300 0 2
@@ -104,6 +103,7 @@
pinmux_debug\[29\]
pinmux_debug\[30\]
pinmux_debug\[31\]
+cpu_clk
#W
strap_sticky\[31\] 000 0 2
@@ -225,6 +225,7 @@
reg_cs 260 0 2
reg_wr
+reg_addr\[10\]
reg_addr\[9\]
reg_addr\[8\]
reg_addr\[7\]
@@ -305,47 +306,9 @@
reg_rdata\[0\]
reg_ack
-cpu_clk
#N
-
-cfg_dac3_mux_sel\[7\]
-cfg_dac3_mux_sel\[6\]
-cfg_dac3_mux_sel\[5\]
-cfg_dac3_mux_sel\[4\]
-cfg_dac3_mux_sel\[3\]
-cfg_dac3_mux_sel\[2\]
-cfg_dac3_mux_sel\[1\]
-cfg_dac3_mux_sel\[0\]
-
-cfg_dac2_mux_sel\[7\]
-cfg_dac2_mux_sel\[6\]
-cfg_dac2_mux_sel\[5\]
-cfg_dac2_mux_sel\[4\]
-cfg_dac2_mux_sel\[3\]
-cfg_dac2_mux_sel\[2\]
-cfg_dac2_mux_sel\[1\]
-cfg_dac2_mux_sel\[0\]
-
-cfg_dac1_mux_sel\[7\]
-cfg_dac1_mux_sel\[6\]
-cfg_dac1_mux_sel\[5\]
-cfg_dac1_mux_sel\[4\]
-cfg_dac1_mux_sel\[3\]
-cfg_dac1_mux_sel\[2\]
-cfg_dac1_mux_sel\[1\]
-cfg_dac1_mux_sel\[0\]
-
-cfg_dac0_mux_sel\[7\]
-cfg_dac0_mux_sel\[6\]
-cfg_dac0_mux_sel\[5\]
-cfg_dac0_mux_sel\[4\]
-cfg_dac0_mux_sel\[3\]
-cfg_dac0_mux_sel\[2\]
-cfg_dac0_mux_sel\[1\]
-cfg_dac0_mux_sel\[0\]
-
-digital_io_oen\[37\] 100 0 4
+digital_io_oen\[37\] 000 0 2
digital_io_out\[37\]
digital_io_in\[37\]
digital_io_oen\[36\]
@@ -374,9 +337,112 @@
digital_io_in\[29\]
digital_io_oen\[28\]
digital_io_out\[28\]
+digital_io_in\[28\]
+digital_io_oen\[27\]
+digital_io_out\[27\]
+digital_io_in\[27\]
+digital_io_oen\[26\]
+digital_io_out\[26\]
+digital_io_in\[26\]
+digital_io_oen\[25\]
+digital_io_out\[25\]
+digital_io_in\[25\]
+digital_io_oen\[24\]
+digital_io_out\[24\]
+digital_io_in\[24\]
+
+rtc_clk 150 0 2
+rtc_intr
+ir_rx
+ir_tx
+ir_intr
+
+reg_peri_cs 200 0 2
+reg_peri_wr
+reg_peri_addr\[10\]
+reg_peri_addr\[9\]
+reg_peri_addr\[8\]
+reg_peri_addr\[7\]
+reg_peri_addr\[6\]
+reg_peri_addr\[5\]
+reg_peri_addr\[4\]
+reg_peri_addr\[3\]
+reg_peri_addr\[2\]
+reg_peri_addr\[1\]
+reg_peri_addr\[0\]
+reg_peri_be\[3\]
+reg_peri_be\[2\]
+reg_peri_be\[1\]
+reg_peri_be\[0\]
+reg_peri_wdata\[31\]
+reg_peri_wdata\[30\]
+reg_peri_wdata\[29\]
+reg_peri_wdata\[28\]
+reg_peri_wdata\[27\]
+reg_peri_wdata\[26\]
+reg_peri_wdata\[25\]
+reg_peri_wdata\[24\]
+reg_peri_wdata\[23\]
+reg_peri_wdata\[22\]
+reg_peri_wdata\[21\]
+reg_peri_wdata\[20\]
+reg_peri_wdata\[19\]
+reg_peri_wdata\[18\]
+reg_peri_wdata\[17\]
+reg_peri_wdata\[16\]
+reg_peri_wdata\[15\]
+reg_peri_wdata\[14\]
+reg_peri_wdata\[13\]
+reg_peri_wdata\[12\]
+reg_peri_wdata\[11\]
+reg_peri_wdata\[10\]
+reg_peri_wdata\[9\]
+reg_peri_wdata\[8\]
+reg_peri_wdata\[7\]
+reg_peri_wdata\[6\]
+reg_peri_wdata\[5\]
+reg_peri_wdata\[4\]
+reg_peri_wdata\[3\]
+reg_peri_wdata\[2\]
+reg_peri_wdata\[1\]
+reg_peri_wdata\[0\]
+reg_peri_rdata\[31\]
+reg_peri_rdata\[30\]
+reg_peri_rdata\[29\]
+reg_peri_rdata\[28\]
+reg_peri_rdata\[27\]
+reg_peri_rdata\[26\]
+reg_peri_rdata\[25\]
+reg_peri_rdata\[24\]
+reg_peri_rdata\[23\]
+reg_peri_rdata\[22\]
+reg_peri_rdata\[21\]
+reg_peri_rdata\[20\]
+reg_peri_rdata\[19\]
+reg_peri_rdata\[18\]
+reg_peri_rdata\[17\]
+reg_peri_rdata\[16\]
+reg_peri_rdata\[15\]
+reg_peri_rdata\[14\]
+reg_peri_rdata\[13\]
+reg_peri_rdata\[12\]
+reg_peri_rdata\[11\]
+reg_peri_rdata\[10\]
+reg_peri_rdata\[9\]
+reg_peri_rdata\[8\]
+reg_peri_rdata\[7\]
+reg_peri_rdata\[6\]
+reg_peri_rdata\[5\]
+reg_peri_rdata\[4\]
+reg_peri_rdata\[3\]
+reg_peri_rdata\[2\]
+reg_peri_rdata\[1\]
+reg_peri_rdata\[0\]
+reg_peri_ack
-cfg_dco_mode 0200 0 2
+
+cfg_dco_mode 0300 0 2
cfg_pll_enb
pll_ref_clk
cfg_pll_fed_div\[4\]
@@ -411,37 +477,7 @@
cfg_dc_trim\[1\]
cfg_dc_trim\[0\]
-digital_io_in\[28\] 0300 0 2
-digital_io_oen\[27\]
-digital_io_out\[27\]
-digital_io_in\[27\]
-digital_io_oen\[26\]
-digital_io_out\[26\]
-digital_io_in\[26\]
-digital_io_oen\[25\]
-digital_io_out\[25\]
-digital_io_in\[25\]
-digital_io_oen\[24\]
-digital_io_out\[24\]
-digital_io_in\[24\]
-sflash_oen\[0\] 350 0 2
-sflash_oen\[1\]
-sflash_oen\[2\]
-sflash_oen\[3\]
-sflash_ss\[0\]
-sflash_ss\[1\]
-sflash_ss\[2\]
-sflash_ss\[3\]
-sflash_sck
-sflash_do\[0\]
-sflash_do\[1\]
-sflash_do\[2\]
-sflash_do\[3\]
-sflash_di\[0\]
-sflash_di\[1\]
-sflash_di\[2\]
-sflash_di\[3\]
digital_io_in\[23\] 400 0
digital_io_out\[23\]
@@ -473,8 +509,25 @@
#E
+sflash_oen\[0\]
+sflash_oen\[1\]
+sflash_oen\[2\]
+sflash_oen\[3\]
+sflash_ss\[0\]
+sflash_ss\[1\]
+sflash_ss\[2\]
+sflash_ss\[3\]
+sflash_sck
+sflash_do\[0\]
+sflash_do\[1\]
+sflash_do\[2\]
+sflash_do\[3\]
+sflash_di\[0\]
+sflash_di\[1\]
+sflash_di\[2\]
+sflash_di\[3\]
-digital_io_in\[0\] 0200 0 4
+digital_io_in\[0\] 0300 0 4
digital_io_out\[0\]
digital_io_oen\[0\]
digital_io_in\[1\]
diff --git a/openlane/qspim_top/pin_order.cfg b/openlane/qspim_top/pin_order.cfg
index c078759..afea1d2 100644
--- a/openlane/qspim_top/pin_order.cfg
+++ b/openlane/qspim_top/pin_order.cfg
@@ -2,40 +2,8 @@
#MANUAL_PLACE
#E
-spi_debug\[0\] 0000 0 2
-spi_debug\[1\]
-spi_debug\[2\]
-spi_debug\[3\]
-spi_debug\[4\]
-spi_debug\[5\]
-spi_debug\[6\]
-spi_debug\[7\]
-spi_debug\[8\]
-spi_debug\[9\]
-spi_debug\[10\]
-spi_debug\[11\]
-spi_debug\[12\]
-spi_debug\[13\]
-spi_debug\[14\]
-spi_debug\[15\]
-spi_debug\[16\]
-spi_debug\[17\]
-spi_debug\[18\]
-spi_debug\[19\]
-spi_debug\[20\]
-spi_debug\[21\]
-spi_debug\[22\]
-spi_debug\[23\]
-spi_debug\[24\]
-spi_debug\[25\]
-spi_debug\[26\]
-spi_debug\[27\]
-spi_debug\[28\]
-spi_debug\[29\]
-spi_debug\[30\]
-spi_debug\[31\]
-spi_sdi\[3\] 0200 0 2
+spi_sdi\[3\] 0500 0 2
spi_sdi\[2\]
spi_sdi\[1\]
spi_sdi\[0\]
@@ -55,7 +23,7 @@
#W
-cfg_cska_sp_co\[3\] 0200 0 2
+cfg_cska_sp_co\[3\] 0300 0 2
cfg_cska_sp_co\[2\]
cfg_cska_sp_co\[1\]
cfg_cska_sp_co\[0\]
@@ -67,7 +35,7 @@
wbd_clk_spi
mclk
-wbd_stb_i 0300 0 2
+wbd_stb_i 0350 0 2
wbd_we_i
wbd_adr_i\[31\]
wbd_adr_i\[30\]
@@ -192,3 +160,36 @@
strap_pre_sram
strap_flash\[1\]
strap_flash\[0\]
+
+spi_debug\[0\] 0050 0 2
+spi_debug\[1\]
+spi_debug\[2\]
+spi_debug\[3\]
+spi_debug\[4\]
+spi_debug\[5\]
+spi_debug\[6\]
+spi_debug\[7\]
+spi_debug\[8\]
+spi_debug\[9\]
+spi_debug\[10\]
+spi_debug\[11\]
+spi_debug\[12\]
+spi_debug\[13\]
+spi_debug\[14\]
+spi_debug\[15\]
+spi_debug\[16\]
+spi_debug\[17\]
+spi_debug\[18\]
+spi_debug\[19\]
+spi_debug\[20\]
+spi_debug\[21\]
+spi_debug\[22\]
+spi_debug\[23\]
+spi_debug\[24\]
+spi_debug\[25\]
+spi_debug\[26\]
+spi_debug\[27\]
+spi_debug\[28\]
+spi_debug\[29\]
+spi_debug\[30\]
+spi_debug\[31\]
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2c_usb_spi_top/base.sdc
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/base.sdc
rename to openlane/uart_i2c_usb_spi_top/base.sdc
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2c_usb_spi_top/config.tcl
similarity index 99%
rename from openlane/uart_i2cm_usb_spi_top/config.tcl
rename to openlane/uart_i2c_usb_spi_top/config.tcl
index 358a009..fcf98c4 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2c_usb_spi_top/config.tcl
@@ -30,6 +30,7 @@
set ::env(CLOCK_PORT) "app_clk usb_clk u_uart0_core.u_lineclk_buf.genblk1.u_mux/X u_uart1_core.u_lineclk_buf.genblk1.u_mux/X"
set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
## CTS BUFFER
set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
diff --git a/openlane/uart_i2cm_usb_spi_top/pdn.tcl b/openlane/uart_i2c_usb_spi_top/pdn.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/pdn.tcl
rename to openlane/uart_i2c_usb_spi_top/pdn.tcl
diff --git a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
similarity index 97%
rename from openlane/uart_i2cm_usb_spi_top/pin_order.cfg
rename to openlane/uart_i2c_usb_spi_top/pin_order.cfg
index 2801070..cbc75a4 100644
--- a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
+++ b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
@@ -2,7 +2,7 @@
#MANUAL_PLACE
#W
-cfg_cska_uart\[3\] 0200 0 2
+cfg_cska_uart\[3\] 0300 0 2
cfg_cska_uart\[2\]
cfg_cska_uart\[1\]
cfg_cska_uart\[0\]
@@ -10,7 +10,7 @@
wbd_clk_uart
app_clk
-reg_cs 0300 0 2
+reg_cs 0400 0 2
reg_wr
reg_addr\[8\]
reg_addr\[7\]
@@ -101,7 +101,7 @@
usb_rstn
-#E
+#N
scl_pad_i
scl_pad_o
scl_pad_oen_o
diff --git a/openlane/uart_i2cm_usb_spi_top/sta.tcl b/openlane/uart_i2c_usb_spi_top/sta.tcl
similarity index 100%
rename from openlane/uart_i2cm_usb_spi_top/sta.tcl
rename to openlane/uart_i2c_usb_spi_top/sta.tcl
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 60d31ef..51c26d0 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -76,6 +76,11 @@
$::env(DESIGN_DIR)/../../verilog/gl/dg_pll.v \
$::env(DESIGN_DIR)/../../verilog/gl/dac_top.v \
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_south.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_north.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_east.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_west.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/peri_top.v \
"
set ::env(EXTRA_LEFS) "\
@@ -90,6 +95,11 @@
$lef_root/dg_pll.lef \
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
$lef_root/dac_top.lef \
+ $lef_root/bus_rep_south.lef \
+ $lef_root/bus_rep_north.lef \
+ $lef_root/bus_rep_east.lef \
+ $lef_root/bus_rep_west.lef \
+ $lef_root/peri_top.lef \
"
set ::env(EXTRA_GDS_FILES) "\
@@ -104,6 +114,11 @@
$gds_root/dg_pll.gds \
$gds_root/dac_top.gds \
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
+ $gds_root/bus_rep_south.gds \
+ $gds_root/bus_rep_north.gds \
+ $gds_root/bus_rep_east.gds \
+ $gds_root/bus_rep_west.gds \
+ $gds_root/peri_top.gds \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -115,6 +130,10 @@
## Internal Macros
### Macro PDN Connections
+set ::env(FP_PDN_CHECK_NODES) 1
+set ::env(FP_PDN_IRDROP) "1"
+set ::env(RUN_IRDROP_REPORT) "1"
+####################
set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "0"
@@ -127,8 +146,8 @@
set ::env(FP_PDN_VPITCH) "80"
set ::env(FP_PDN_HOFFSET) "5"
set ::env(FP_PDN_HPITCH) "80"
-set ::env(FP_PDN_HWIDTH) {6.2}
-set ::env(FP_PDN_VWIDTH) {6.2}
+set ::env(FP_PDN_HWIDTH) {5.2}
+set ::env(FP_PDN_VWIDTH) {5.2}
set ::env(FP_PDN_HSPACING) {13.8}
set ::env(FP_PDN_VSPACING) {13.8}
@@ -169,13 +188,18 @@
u_dcache_2kb vccd1 vssd1 vccd1 vssd1,\
u_uart_i2c_usb_spi vccd1 vssd1 vccd1 vssd1,\
u_wb_host vccd1 vssd1 vccd1 vssd1,\
- u_riscv_top.i_core_top_0 vccd1 vssd1 vccd1 vssd1, \
- u_riscv_top.i_core_top_1 vccd1 vssd1 vccd1 vssd1, \
- u_riscv_top.i_core_top_2 vccd1 vssd1 vccd1 vssd1, \
- u_riscv_top.i_core_top_3 vccd1 vssd1 vccd1 vssd1, \
+ u_riscv_top.i_core_top_0 vccd1 vssd1 vccd1 vssd1,\
+ u_riscv_top.i_core_top_1 vccd1 vssd1 vccd1 vssd1,\
+ u_riscv_top.i_core_top_2 vccd1 vssd1 vccd1 vssd1,\
+ u_riscv_top.i_core_top_3 vccd1 vssd1 vccd1 vssd1,\
u_riscv_top.u_connect vccd1 vssd1 VPWR VGND, \
- u_riscv_top.u_intf vccd1 vssd1 vccd1 vssd1, \
- u_4x8bit_dac vdda1 vssa1 vccd1 vssd1
+ u_riscv_top.u_intf vccd1 vssd1 vccd1 vssd1,\
+ u_4x8bit_dac vdda1 vssa1 vccd1 vssd1,\
+ u_rp_south vccd1 vssd1 vccd1 vssd1,\
+ u_rp_north vccd1 vssd1 vccd1 vssd1,\
+ u_rp_east vccd1 vssd1 vccd1 vssd1,\
+ u_rp_west vccd1 vssd1 vccd1 vssd1,\
+ u_peri vccd1 vssd1 vccd1 vssd1
"
@@ -197,4 +221,6 @@
set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+## Temp Masked due to long Run Time
+set ::env(RUN_KLAYOUT_XOR) {0}
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index f7cee8c..b6a603c 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,20 +1,24 @@
-u_4x8bit_dac 1850 2500 N
-u_qspi_master 2250 450 N
-u_uart_i2c_usb_spi 2250 1100 N
-u_pinmux 2250 2000 N
-u_pll 2500 3028 N
+u_4x8bit_dac 1850 2500 N
+u_qspi_master 2250 350 N
+u_uart_i2c_usb_spi 2250 1000 N
+u_pinmux 2250 1900 N
+u_peri 2200 2900 N
+u_pll 2650 2900 N
-u_riscv_top.i_core_top_0 75 1400 N
-u_riscv_top.i_core_top_1 1200 1400 FN
-u_riscv_top.i_core_top_2 75 2475 N
-u_riscv_top.i_core_top_3 1200 2475 FN
-u_riscv_top.u_connect 735 1400 N
-u_riscv_top.u_intf 950 650 N
-u_dcache_2kb 150 130 N
-u_icache_2kb 950 130 N
-u_tsram0_2kb 150 750 N
+u_riscv_top.i_core_top_0 150 1400 N
+u_riscv_top.i_core_top_1 1200 1400 FN
+u_riscv_top.i_core_top_2 150 2400 N
+u_riscv_top.i_core_top_3 1200 2400 FN
+u_riscv_top.u_connect 740 1400 N
+u_riscv_top.u_intf 950 650 N
+u_dcache_2kb 150 130 N
+u_icache_2kb 950 130 N
+u_tsram0_2kb 150 750 N
-u_intercon 1850 650 N
-u_wb_host 1750 100 N
-
+u_intercon 1850 650 N
+u_wb_host 1750 100 N
+u_rp_south 100 20 N
+u_rp_north 100 3400 N
+u_rp_east 2820 50 E
+u_rp_west 50 100 E
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index b2a2b42..a7d900d 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -150,14 +150,46 @@
-spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
-core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
}
+##################################
+# Common Macro Power Hook Up
+# Power Connect met-4 to met-5
+##################################
define_pdn_grid \
-macro \
- -default \
- -name macro \
+ -name macro_1 \
+ -instances "u_pll u_intercon u_pinmux u_qspi_master u_tsram0_2kb u_icache_2kb u_dcache_2kb u_uart_i2c_usb_spi u_wb_host u_riscv_top.i_core_top_0 u_riscv_top.i_core_top_1 u_riscv_top.i_core_top_2 u_riscv_top.i_core_top_3 u_riscv_top.u_connect u_riscv_top.u_intf u_4x8bit_dac u_peri" \
-starts_with POWER \
-halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
add_pdn_connect \
- -grid macro \
+ -grid macro_1 \
-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+
+##################################
+# u_rp_North & u_rp_south Power Hook Up
+# Power connect met-3 to met-4
+##################################
+
+define_pdn_grid \
+ -macro \
+ -name macro_2 \
+ -instances "u_rp_south u_rp_north" \
+ -starts_with POWER \
+ -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+
+add_pdn_connect -grid macro_2 -layers "met3 met4"
+
+##################################
+# u_rp_east Power Hook Up
+# Power connect met-3 to met-5
+##################################
+
+define_pdn_grid \
+ -macro \
+ -name macro_3 \
+ -instances "u_rp_east u_rp_west" \
+ -starts_with POWER \
+ -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+
+add_pdn_connect -grid macro_3 -layers "met3 met5"
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 006cdfe..48a791b 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -85,7 +85,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 425"
+set ::env(DIE_AREA) "0 0 425 425"
set ::env(GRT_OBS) " \
met4 0 0 400 425"
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 8c93e59..60315f0 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -3,12 +3,6 @@
#MANUAL_PLACE
-#W
-
-cpu_clk 0100 0 2
-
-
-
#S
user_clock2 0000 0 2
user_clock1
@@ -158,21 +152,9 @@
#N
-cfg_clk_skew_ctrl2\[31\] 0000 0 2
-cfg_clk_skew_ctrl2\[30\]
-cfg_clk_skew_ctrl2\[29\]
-cfg_clk_skew_ctrl2\[28\]
-cfg_clk_skew_ctrl2\[27\]
-cfg_clk_skew_ctrl2\[26\]
-cfg_clk_skew_ctrl2\[25\]
-cfg_clk_skew_ctrl2\[24\]
-cfg_clk_skew_ctrl1\[31\]
-cfg_clk_skew_ctrl1\[30\]
-cfg_clk_skew_ctrl1\[29\]
-cfg_clk_skew_ctrl1\[28\]
-cfg_clk_skew_ctrl1\[7\]
+cfg_clk_skew_ctrl1\[7\] 0000 0 2
cfg_cska_wh\[3\]
cfg_clk_skew_ctrl1\[6\]
cfg_cska_wh\[2\]
@@ -181,7 +163,9 @@
cfg_clk_skew_ctrl1\[4\]
cfg_cska_wh\[0\]
-wbd_int_rst_n 0100 0 2
+cpu_clk 0100 0 2
+
+wbd_int_rst_n 0120 0 2
cfg_clk_skew_ctrl2\[23\]
cfg_clk_skew_ctrl2\[22\]
cfg_clk_skew_ctrl2\[21\]
@@ -347,7 +331,21 @@
wbs_cyc_o
-strap_sticky\[31\] 325 0 2
+cfg_clk_skew_ctrl1\[31\] 325 0 2
+cfg_clk_skew_ctrl1\[30\]
+cfg_clk_skew_ctrl1\[29\]
+cfg_clk_skew_ctrl1\[28\]
+
+cfg_clk_skew_ctrl2\[31\]
+cfg_clk_skew_ctrl2\[30\]
+cfg_clk_skew_ctrl2\[29\]
+cfg_clk_skew_ctrl2\[28\]
+cfg_clk_skew_ctrl2\[27\]
+cfg_clk_skew_ctrl2\[26\]
+cfg_clk_skew_ctrl2\[25\]
+cfg_clk_skew_ctrl2\[24\]
+
+strap_sticky\[31\]
strap_sticky\[30\]
strap_sticky\[29\]
strap_sticky\[28\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 38f2c70..743d701 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -54,8 +54,8 @@
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=7\
- CH_DATA_WD=154 \
+set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=8\
+ CH_DATA_WD=158 \
"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
diff --git a/openlane/wb_interconnect/interactive.tcl b/openlane/wb_interconnect/interactive.tcl
new file mode 100755
index 0000000..a96ddb6
--- /dev/null
+++ b/openlane/wb_interconnect/interactive.tcl
@@ -0,0 +1,355 @@
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+package require openlane; # provides the utils as well
+
+proc run_placement_step {args} {
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
+
+ run_placement
+}
+
+proc run_cts_step {args} {
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
+
+ run_cts
+ run_resizer_timing
+}
+
+proc run_routing_step {args} {
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ if { $::env(ECO_ENABLE) == 0 } {
+ run_routing
+ }
+}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+ run_parasitics_sta
+ }
+}
+
+proc run_diode_insertion_2_5_step {args} {
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
+}
+
+proc run_irdrop_report_step {args} {
+ if { $::env(RUN_IRDROP_REPORT) } {
+ run_irdrop_report
+ }
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
+ if { $antenna_check_enabled } {
+ run_antenna_check
+ }
+}
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
+}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
+proc run_post_run_hooks {} {
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
+}
+
+proc run_magic_drc_batch {args} {
+ set options {
+ {-magicrc optional}
+ {-tech optional}
+ {-report required}
+ {-design required}
+ {-gds required}
+ }
+ set flags {}
+ parse_key_args "run_magic_drc_batch" args arg_values $options flags_mag $flags
+ if { [info exists arg_values(-magicrc)] } {
+ set magicrc [file normalize $arg_values(-magicrc)]
+ }
+ if { [info exists arg_values(-tech)] } {
+ set ::env(TECH) [file normalize $arg_values(-tech)]
+ }
+ set ::env(GDS_INPUT) [file normalize $arg_values(-gds)]
+ set ::env(REPORT_OUTPUT) [file normalize $arg_values(-report)]
+ set ::env(DESIGN_NAME) $arg_values(-design)
+
+ if { [info exists magicrc] } {
+ exec magic \
+ -noconsole \
+ -dnull \
+ -rcfile $magicrc \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ } else {
+ exec magic \
+ -noconsole \
+ -dnull \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ }
+}
+
+proc run_lvs_batch {args} {
+ # runs device level lvs on -gds/CURRENT_GDS and -net/CURRENT_NETLIST
+ # extracts gds only if EXT_NETLIST does not exist
+ set options {
+ {-design required}
+ {-gds optional}
+ {-net optional}
+ }
+ set flags {}
+ parse_key_args "run_lvs_batch" args arg_values $options flags_lvs $flags -no_consume
+
+ prep {*}$args
+
+ if { [info exists arg_values(-gds)] } {
+ set ::env(CURRENT_GDS) [file normalize $arg_values(-gds)]
+ } else {
+ set ::env(CURRENT_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).gds
+ }
+ if { [info exists arg_values(-net)] } {
+ set ::env(CURRENT_NETLIST) [file normalize $arg_values(-net)]
+ }
+
+ assert_files_exist "$::env(CURRENT_GDS) $::env(CURRENT_NETLIST)"
+
+ set ::env(MAGIC_EXT_USE_GDS) 1
+ set ::env(EXT_NETLIST) $::env(signoff_results)/$::env(DESIGN_NAME).gds.spice
+ if { [file exists $::env(EXT_NETLIST)] } {
+ puts_warn "The file $::env(EXT_NETLIST) will be used. If you would like the file re-exported, please delete it."
+ } else {
+ run_magic_spice_export
+ }
+
+ run_lvs
+}
+
+
+proc run_file {args} {
+ set ::env(TCLLIBPATH) $::auto_path
+ exec tclsh {*}$args >&@stdout
+}
+
+
+
+proc run_flow {args} {
+ set options {
+ {-design optional}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
+ # signal trap SIGINT save_state;
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ load_overrides $arg_values(-override_env)
+ }
+
+ set LVS_ENABLED 1
+ set DRC_ENABLED 1
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
+ set steps [dict create \
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "irdrop" "run_irdrop_report_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
+ ]
+
+ if { [info exists arg_values(-from) ]} {
+ puts_info "Starting flow at $arg_values(-from)..."
+ set ::env(CURRENT_STEP) $arg_values(-from)
+ } elseif { [info exists ::env(CURRENT_STEP) ] } {
+ puts_info "Resuming flow from $::env(CURRENT_STEP)..."
+ } else {
+ set ::env(CURRENT_STEP) "synthesis"
+ }
+ #Dinesh-A: Addition for LAST_STEP
+ if { [info exists arg_values(-to) ]} {
+ puts_info "Last flow Will be at $arg_values(-to)..."
+ set ::env(LAST_STEP) $arg_values(-to)
+ } elseif { [info exists ::env(LAST_STEP) ] } {
+ puts_info "Last flow Will be at $::env(LAST_STEP)..."
+ } else {
+ set ::env(LAST_STEP) "cvc"
+ }
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+ set_if_unset arg_values(-to) $::env(LAST_STEP)
+
+ set exe 0;
+ dict for {step_name step_exe} $steps {
+ if { [ string equal $arg_values(-from) $step_name ] } {
+ set exe 1;
+ }
+
+ if { $exe } {
+ # For when it fails
+ set ::env(CURRENT_STEP) $step_name
+ [lindex $step_exe 0] [lindex $step_exe 1] ;
+ }
+
+ if { [ string equal $arg_values(-to) $step_name ] } {
+ set exe 0:
+ break;
+ }
+
+ }
+
+ # for when it resumes
+ set steps_as_list [dict keys $steps]
+ set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+ set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+ # Saves to <RUN_DIR>/results/final
+ save_final_views
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
+}
+
+run_flow {*}$argv
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 5d9f81e..af8e9cf 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -3,9 +3,9 @@
#MANUAL_PLACE
#S
-ch_clk_in\[6\] 000 0 2
+ch_clk_in\[7\] 000 0 2
+ch_clk_in\[6\]
ch_clk_in\[5\]
-ch_clk_in\[4\]
rst_n 020 0 2
@@ -59,6 +59,7 @@
cfg_cska_wi\[1\]
cfg_cska_wi\[0\]
+ch_clk_in\[4\]
ch_clk_in\[3\]
ch_clk_in\[2\]
ch_clk_in\[1\]
@@ -175,7 +176,13 @@
m0_wbd_err_o
m0_wbd_cyc_i
-ch_data_in\[153\] 225 0 2
+
+ch_data_in\[157\] 225 0 2
+ch_data_in\[156\]
+ch_data_in\[155\]
+ch_data_in\[154\]
+
+ch_data_in\[153\]
ch_data_in\[152\]
ch_data_in\[151\]
ch_data_in\[150\]
@@ -265,7 +272,7 @@
ch_data_out\[22\]
ch_data_out\[21\]
ch_data_out\[20\]
-ch_clk_out\[4\]
+ch_clk_out\[5\]
ch_data_out\[3\] 050 0 2
ch_data_out\[2\]
@@ -615,7 +622,7 @@
ch_data_out\[26\]
ch_data_out\[25\]
ch_data_out\[24\]
-ch_clk_out\[5\]
+ch_clk_out\[6\]
ch_data_out\[76\] 1600 0 2
ch_data_out\[75\]
@@ -672,7 +679,7 @@
ch_data_out\[4\]
ch_clk_out\[1\]
-s0_wbd_stb_o 0100 0 2
+s0_wbd_stb_o 0050 0 2
s0_wbd_we_o
s0_wbd_adr_o\[31\]
s0_wbd_adr_o\[30\]
@@ -879,7 +886,9 @@
s1_wbd_cyc_o
-ch_data_in\[145\] 1350 0 2
+
+
+ch_data_in\[145\] 1250 0 2
ch_data_in\[144\]
ch_data_in\[143\]
ch_data_in\[142\]
@@ -953,7 +962,7 @@
ch_data_out\[78\]
ch_data_out\[77\]
-ch_data_in\[76\] 1550 0 2
+ch_data_in\[76\] 1450 0 2
ch_data_in\[75\]
ch_data_in\[74\]
ch_data_in\[73\]
@@ -993,8 +1002,9 @@
ch_data_out\[12\]
ch_clk_out\[3\]
-s2_wbd_stb_o 1610 0 2
+s2_wbd_stb_o 1510 0 2
s2_wbd_we_o
+s2_wbd_adr_o\[10\]
s2_wbd_adr_o\[9\]
s2_wbd_adr_o\[8\]
s2_wbd_adr_o\[7\]
@@ -1076,5 +1086,10 @@
s2_wbd_ack_i
s2_wbd_cyc_o
-ch_clk_out\[6\]
+ch_clk_out\[7\]
+ch_clk_out\[4\] 1750 0 2
+ch_data_out\[154\]
+ch_data_out\[155\]
+ch_data_out\[156\]
+ch_data_out\[157\]
diff --git a/openlane/ycr4_iconnect/config.tcl b/openlane/ycr4_iconnect/config.tcl
index 63ccd07..5139fc9 100644
--- a/openlane/ycr4_iconnect/config.tcl
+++ b/openlane/ycr4_iconnect/config.tcl
@@ -61,7 +61,7 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 2000"
+set ::env(DIE_AREA) "0 0 400 1900"
set ::env(PL_TARGET_DENSITY) 0.20
#set ::env(CELL_PAD) 8
diff --git a/openlane/ycr4_iconnect/pin_order.cfg b/openlane/ycr4_iconnect/pin_order.cfg
index eed55ba..c509d57 100644
--- a/openlane/ycr4_iconnect/pin_order.cfg
+++ b/openlane/ycr4_iconnect/pin_order.cfg
@@ -458,7 +458,7 @@
core0_irq_lines\[0\]
core0_irq_soft
-core2_clk 1250 00 2
+core2_clk 1200 00 2
core2_uid\[1\]
core2_uid\[0\]
core2_imem_req_ack
@@ -534,7 +534,7 @@
core2_imem_resp\[1\]
core2_imem_resp\[0\]
-core2_dmem_req_ack 1400 0 2
+core2_dmem_req_ack 1350 0 2
core2_dmem_req
core2_dmem_cmd
core2_dmem_width\[1\]
@@ -638,7 +638,7 @@
core2_dmem_resp\[1\]
core2_dmem_resp\[0\]
-core2_debug\[48\] 1550 0 2
+core2_debug\[48\] 1500 0 2
core2_debug\[47\]
core2_debug\[46\]
core2_debug\[45\]
@@ -688,7 +688,7 @@
core2_debug\[1\]
core2_debug\[0\]
-core2_timer_irq 1650 0 2
+core2_timer_irq 1600 0 2
core2_timer_val\[63\]
core2_timer_val\[62\]
core2_timer_val\[61\]
@@ -1084,70 +1084,70 @@
core_debug_sel\[1\] 300 0 2
core_debug_sel\[0\]
-riscv_debug\[63\]
-riscv_debug\[62\]
-riscv_debug\[61\]
-riscv_debug\[60\]
-riscv_debug\[59\]
-riscv_debug\[58\]
-riscv_debug\[57\]
-riscv_debug\[56\]
-riscv_debug\[55\]
-riscv_debug\[54\]
-riscv_debug\[53\]
-riscv_debug\[52\]
-riscv_debug\[51\]
-riscv_debug\[50\]
-riscv_debug\[49\]
-riscv_debug\[48\]
-riscv_debug\[47\]
-riscv_debug\[46\]
-riscv_debug\[45\]
-riscv_debug\[44\]
-riscv_debug\[43\]
-riscv_debug\[42\]
-riscv_debug\[41\]
-riscv_debug\[40\]
-riscv_debug\[39\]
-riscv_debug\[38\]
-riscv_debug\[37\]
-riscv_debug\[36\]
-riscv_debug\[35\]
-riscv_debug\[34\]
-riscv_debug\[33\]
-riscv_debug\[32\]
-riscv_debug\[31\]
-riscv_debug\[30\]
-riscv_debug\[29\]
-riscv_debug\[28\]
-riscv_debug\[27\]
-riscv_debug\[26\]
-riscv_debug\[25\]
-riscv_debug\[24\]
-riscv_debug\[23\]
-riscv_debug\[22\]
-riscv_debug\[21\]
-riscv_debug\[20\]
-riscv_debug\[19\]
-riscv_debug\[18\]
-riscv_debug\[17\]
-riscv_debug\[16\]
-riscv_debug\[15\]
-riscv_debug\[14\]
-riscv_debug\[13\]
-riscv_debug\[12\]
-riscv_debug\[11\]
-riscv_debug\[10\]
-riscv_debug\[9\]
-riscv_debug\[8\]
-riscv_debug\[7\]
-riscv_debug\[6\]
-riscv_debug\[5\]
-riscv_debug\[4\]
-riscv_debug\[3\]
-riscv_debug\[2\]
-riscv_debug\[1\]
riscv_debug\[0\]
+riscv_debug\[1\]
+riscv_debug\[2\]
+riscv_debug\[3\]
+riscv_debug\[4\]
+riscv_debug\[5\]
+riscv_debug\[6\]
+riscv_debug\[7\]
+riscv_debug\[8\]
+riscv_debug\[9\]
+riscv_debug\[10\]
+riscv_debug\[11\]
+riscv_debug\[12\]
+riscv_debug\[13\]
+riscv_debug\[14\]
+riscv_debug\[15\]
+riscv_debug\[16\]
+riscv_debug\[17\]
+riscv_debug\[18\]
+riscv_debug\[19\]
+riscv_debug\[20\]
+riscv_debug\[21\]
+riscv_debug\[22\]
+riscv_debug\[23\]
+riscv_debug\[24\]
+riscv_debug\[25\]
+riscv_debug\[26\]
+riscv_debug\[27\]
+riscv_debug\[28\]
+riscv_debug\[29\]
+riscv_debug\[30\]
+riscv_debug\[31\]
+riscv_debug\[32\]
+riscv_debug\[33\]
+riscv_debug\[34\]
+riscv_debug\[35\]
+riscv_debug\[36\]
+riscv_debug\[37\]
+riscv_debug\[38\]
+riscv_debug\[39\]
+riscv_debug\[40\]
+riscv_debug\[41\]
+riscv_debug\[42\]
+riscv_debug\[43\]
+riscv_debug\[44\]
+riscv_debug\[45\]
+riscv_debug\[46\]
+riscv_debug\[47\]
+riscv_debug\[48\]
+riscv_debug\[49\]
+riscv_debug\[50\]
+riscv_debug\[51\]
+riscv_debug\[52\]
+riscv_debug\[53\]
+riscv_debug\[54\]
+riscv_debug\[55\]
+riscv_debug\[56\]
+riscv_debug\[57\]
+riscv_debug\[58\]
+riscv_debug\[59\]
+riscv_debug\[60\]
+riscv_debug\[61\]
+riscv_debug\[62\]
+riscv_debug\[63\]
#E
cfg_ccska\[3\]
@@ -1487,7 +1487,50 @@
core1_irq_lines\[0\]
core1_irq_soft
-core3_clk 1250 00 2
+
+core_irq_lines_i\[31\] 1000 0 2
+core_irq_lines_i\[30\]
+core_irq_lines_i\[29\]
+core_irq_lines_i\[28\]
+core_irq_lines_i\[27\]
+core_irq_lines_i\[26\]
+core_irq_lines_i\[25\]
+core_irq_lines_i\[24\]
+core_irq_lines_i\[23\]
+core_irq_lines_i\[22\]
+core_irq_lines_i\[21\]
+core_irq_lines_i\[20\]
+core_irq_lines_i\[19\]
+core_irq_lines_i\[18\]
+core_irq_lines_i\[17\]
+core_irq_lines_i\[16\]
+core_irq_lines_i\[15\]
+core_irq_lines_i\[14\]
+core_irq_lines_i\[13\]
+core_irq_lines_i\[12\]
+core_irq_lines_i\[11\]
+core_irq_lines_i\[10\]
+core_irq_lines_i\[9\]
+core_irq_lines_i\[8\]
+core_irq_lines_i\[7\]
+core_irq_lines_i\[6\]
+core_irq_lines_i\[5\]
+core_irq_lines_i\[4\]
+core_irq_lines_i\[3\]
+core_irq_lines_i\[2\]
+core_irq_lines_i\[1\]
+core_irq_lines_i\[0\]
+core_irq_soft_i
+
+rtc_clk
+pwrup_rst_n
+cpu_intf_rst_n
+cfg_bypass_icache
+cfg_bypass_dcache
+
+
+
+core3_clk 1200 00 2
core3_uid\[1\]
core3_uid\[0\]
core3_imem_req_ack
@@ -1563,7 +1606,7 @@
core3_imem_resp\[1\]
core3_imem_resp\[0\]
-core3_dmem_req_ack 1400 0 2
+core3_dmem_req_ack 1350 0 2
core3_dmem_req
core3_dmem_cmd
core3_dmem_width\[1\]
@@ -1667,7 +1710,7 @@
core3_dmem_resp\[1\]
core3_dmem_resp\[0\]
-core3_debug\[48\] 1550 0 2
+core3_debug\[48\] 1500 0 2
core3_debug\[47\]
core3_debug\[46\]
core3_debug\[45\]
@@ -1717,7 +1760,7 @@
core3_debug\[1\]
core3_debug\[0\]
-core3_timer_irq 1650 0 2
+core3_timer_irq 1600 0 2
core3_timer_val\[63\]
core3_timer_val\[62\]
core3_timer_val\[61\]
@@ -1818,42 +1861,3 @@
core3_irq_soft
#N
-core_irq_lines_i\[31\]
-core_irq_lines_i\[30\]
-core_irq_lines_i\[29\]
-core_irq_lines_i\[28\]
-core_irq_lines_i\[27\]
-core_irq_lines_i\[26\]
-core_irq_lines_i\[25\]
-core_irq_lines_i\[24\]
-core_irq_lines_i\[23\]
-core_irq_lines_i\[22\]
-core_irq_lines_i\[21\]
-core_irq_lines_i\[20\]
-core_irq_lines_i\[19\]
-core_irq_lines_i\[18\]
-core_irq_lines_i\[17\]
-core_irq_lines_i\[16\]
-core_irq_lines_i\[15\]
-core_irq_lines_i\[14\]
-core_irq_lines_i\[13\]
-core_irq_lines_i\[12\]
-core_irq_lines_i\[11\]
-core_irq_lines_i\[10\]
-core_irq_lines_i\[9\]
-core_irq_lines_i\[8\]
-core_irq_lines_i\[7\]
-core_irq_lines_i\[6\]
-core_irq_lines_i\[5\]
-core_irq_lines_i\[4\]
-core_irq_lines_i\[3\]
-core_irq_lines_i\[2\]
-core_irq_lines_i\[1\]
-core_irq_lines_i\[0\]
-core_irq_soft_i
-
-rtc_clk
-pwrup_rst_n
-cpu_intf_rst_n
-cfg_bypass_icache
-cfg_bypass_dcache
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index b364acb..f232816 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl
@@ -77,7 +77,7 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 540 950 "
+set ::env(DIE_AREA) "0 0 500 925 "
set ::env(PL_TARGET_DENSITY) 0.45
set ::env(CELL_PAD) "8"
@@ -101,8 +101,8 @@
set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
-set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {1000}
-set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {1000}
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
set ::env(QUIT_ON_MAGIC_DRC) "1"
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
index 61647d9..1c2794b 100644
--- a/openlane/ycr_intf/config.tcl
+++ b/openlane/ycr_intf/config.tcl
@@ -26,6 +26,7 @@
set ::env(CLOCK_PORT) "wb_clk core_clk"
set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
## CTS BUFFER
set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
@@ -64,8 +65,9 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 810 640 "
-set ::env(CELL_PAD) "6"
+set ::env(DIE_AREA) "0 0 775 630 "
+set ::env(CELL_PAD) "8"
+set ::env(GRT_ADJUSTMENT) {0.2}
set ::env(PL_TARGET_DENSITY) 0.37
diff --git a/sdc/bus_rep_east.sdc b/sdc/bus_rep_east.sdc
new file mode 100644
index 0000000..5011d20
--- /dev/null
+++ b/sdc/bus_rep_east.sdc
@@ -0,0 +1,199 @@
+###############################################################################
+# Created by write_sdc
+# Tue Dec 13 17:11:49 2022
+###############################################################################
+current_design bus_rep_east
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[42]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[43]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[44]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[42]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[43]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[44]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {ch_out[44]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[43]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[42]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[41]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[40]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[39]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[38]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[37]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[36]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[35]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[34]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[33]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[32]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[31]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[30]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[29]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[28]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[27]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/bus_rep_north.sdc b/sdc/bus_rep_north.sdc
new file mode 100644
index 0000000..328d79e
--- /dev/null
+++ b/sdc/bus_rep_north.sdc
@@ -0,0 +1,295 @@
+###############################################################################
+# Created by write_sdc
+# Tue Dec 13 17:09:57 2022
+###############################################################################
+current_design bus_rep_north
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[9]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {buf_out[41]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[40]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[39]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[38]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[37]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[36]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[35]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[34]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[33]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[32]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[31]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[30]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[29]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[28]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[27]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[26]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[25]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[24]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[23]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[22]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[21]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[20]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[19]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[18]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[17]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[16]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[15]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[14]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[13]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[12]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[11]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[10]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[9]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[8]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[7]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[6]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[5]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[4]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[3]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[2]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[1]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[0]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/bus_rep_south.sdc b/sdc/bus_rep_south.sdc
new file mode 100644
index 0000000..72da6f9
--- /dev/null
+++ b/sdc/bus_rep_south.sdc
@@ -0,0 +1,1031 @@
+###############################################################################
+# Created by write_sdc
+# Tue Dec 13 17:10:22 2022
+###############################################################################
+current_design bus_rep_south
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[100]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[101]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[102]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[103]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[104]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[105]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[106]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[107]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[108]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[109]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[110]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[111]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[112]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[113]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[114]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[115]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[116]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[117]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[118]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[119]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[120]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[121]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[122]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[123]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[124]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[125]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[126]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[127]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[128]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[129]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[130]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[131]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[132]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[133]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[134]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[135]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[136]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[137]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[138]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[139]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[140]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[141]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[142]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[143]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[144]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[145]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[146]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[147]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[148]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[149]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[150]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[151]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[152]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[153]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[154]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[155]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[156]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[157]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[158]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[159]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[160]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[161]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[162]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[163]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[164]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[165]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[166]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[167]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[168]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[169]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[170]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[171]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[172]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[173]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[174]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[175]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[176]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[177]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[178]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[179]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[180]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[181]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[182]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[183]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[184]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[185]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[186]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[187]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[188]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[189]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[190]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[191]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[192]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[193]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[194]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[195]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[196]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[197]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[198]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[199]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[200]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[201]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[202]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[203]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[204]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[205]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[206]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[207]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[208]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[209]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[210]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[211]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[212]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[213]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[214]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[215]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[216]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[217]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[218]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[219]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[220]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[221]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[222]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[223]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[224]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[225]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[226]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[227]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[228]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[229]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[230]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[231]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[232]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[233]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[234]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[235]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[236]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[237]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[238]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[239]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[240]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[241]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[242]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[243]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[244]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[245]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[246]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[247]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[248]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[249]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[250]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[251]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[252]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[42]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[43]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[44]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[45]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[46]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[47]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[48]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[49]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[50]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[51]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[52]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[53]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[54]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[55]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[56]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[57]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[58]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[59]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[60]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[61]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[62]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[63]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[64]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[65]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[66]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[67]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[68]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[69]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[70]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[71]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[72]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[73]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[74]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[75]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[76]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[77]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[78]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[79]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[80]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[81]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[82]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[83]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[84]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[85]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[86]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[87]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[88]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[89]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[90]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[91]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[92]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[93]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[94]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[95]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[96]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[97]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[98]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[99]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[100]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[101]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[102]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[103]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[104]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[105]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[106]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[107]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[108]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[109]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[110]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[111]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[112]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[113]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[114]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[115]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[116]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[117]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[118]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[119]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[120]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[121]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[122]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[123]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[124]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[125]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[126]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[127]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[128]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[129]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[130]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[131]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[132]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[133]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[134]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[135]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[136]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[137]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[138]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[139]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[140]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[141]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[142]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[143]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[144]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[145]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[146]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[147]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[148]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[149]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[150]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[151]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[152]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[153]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[154]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[155]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[156]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[157]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[158]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[159]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[160]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[161]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[162]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[163]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[164]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[165]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[166]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[167]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[168]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[169]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[170]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[171]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[172]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[173]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[174]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[175]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[176]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[177]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[178]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[179]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[180]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[181]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[182]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[183]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[184]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[185]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[186]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[187]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[188]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[189]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[190]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[191]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[192]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[193]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[194]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[195]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[196]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[197]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[198]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[199]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[200]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[201]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[202]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[203]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[204]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[205]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[206]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[207]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[208]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[209]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[210]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[211]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[212]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[213]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[214]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[215]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[216]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[217]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[218]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[219]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[220]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[221]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[222]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[223]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[224]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[225]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[226]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[227]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[228]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[229]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[230]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[231]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[232]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[233]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[234]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[235]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[236]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[237]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[238]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[239]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[240]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[241]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[242]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[243]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[244]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[245]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[246]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[247]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[248]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[249]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[250]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[251]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[252]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[42]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[43]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[44]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[45]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[46]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[47]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[48]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[49]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[50]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[51]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[52]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[53]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[54]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[55]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[56]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[57]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[58]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[59]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[60]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[61]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[62]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[63]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[64]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[65]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[66]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[67]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[68]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[69]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[70]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[71]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[72]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[73]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[74]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[75]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[76]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[77]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[78]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[79]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[80]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[81]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[82]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[83]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[84]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[85]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[86]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[87]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[88]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[89]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[90]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[91]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[92]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[93]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[94]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[95]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[96]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[97]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[98]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[99]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {ch_out[252]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[251]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[250]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[249]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[248]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[247]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[246]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[245]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[244]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[243]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[242]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[241]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[240]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[239]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[238]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[237]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[236]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[235]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[234]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[233]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[232]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[231]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[230]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[229]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[228]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[227]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[226]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[225]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[224]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[223]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[222]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[221]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[220]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[219]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[218]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[217]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[216]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[215]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[214]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[213]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[212]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[211]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[210]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[209]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[208]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[207]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[206]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[205]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[204]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[203]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[202]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[201]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[200]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[199]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[198]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[197]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[196]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[195]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[194]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[193]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[192]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[191]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[190]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[189]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[188]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[187]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[186]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[185]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[184]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[183]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[182]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[181]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[180]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[179]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[178]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[177]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[176]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[175]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[174]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[173]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[172]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[171]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[170]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[169]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[168]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[167]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[166]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[165]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[164]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[163]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[162]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[161]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[160]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[159]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[158]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[157]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[156]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[155]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[154]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[153]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[152]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[151]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[150]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[149]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[148]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[147]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[146]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[145]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[144]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[143]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[142]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[141]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[140]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[139]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[138]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[137]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[136]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[135]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[134]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[133]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[132]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[131]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[130]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[129]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[128]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[127]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[126]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[125]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[124]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[123]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[122]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[121]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[120]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[119]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[118]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[117]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[116]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[115]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[114]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[113]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[112]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[111]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[110]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[109]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[108]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[107]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[106]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[105]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[104]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[103]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[102]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[101]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[100]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[99]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[98]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[97]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[96]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[95]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[94]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[93]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[92]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[91]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[90]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[89]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[88]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[87]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[86]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[85]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[84]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[83]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[82]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[81]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[80]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[79]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[78]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[77]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[76]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[75]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[74]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[73]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[72]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[71]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[70]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[69]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[68]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[67]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[66]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[65]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[64]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[63]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[62]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[61]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[60]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[59]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[58]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[57]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[56]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[55]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[54]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[53]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[52]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[51]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[50]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[49]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[48]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[47]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[46]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[45]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[44]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[43]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[42]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[41]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[40]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[39]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[38]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[37]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[36]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[35]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[34]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[33]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[32]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[31]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[30]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[29]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[28]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[27]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[252]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[251]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[250]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[249]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[248]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[247]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[246]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[245]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[244]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[243]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[242]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[241]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[240]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[239]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[238]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[237]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[236]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[235]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[234]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[233]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[232]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[231]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[230]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[229]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[228]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[227]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[226]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[225]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[224]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[223]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[222]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[221]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[220]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[219]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[218]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[217]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[216]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[215]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[214]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[213]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[212]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[211]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[210]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[209]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[208]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[207]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[206]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[205]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[204]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[203]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[202]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[201]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[200]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[199]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[198]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[197]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[196]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[195]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[194]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[193]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[192]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[191]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[190]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[189]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[188]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[187]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[186]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[185]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[184]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[183]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[182]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[181]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[180]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[179]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[178]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[177]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[176]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[175]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[174]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[173]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[172]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[171]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[170]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[169]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[168]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[167]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[166]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[165]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[164]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[163]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[162]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[161]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[160]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[157]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[152]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[151]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[150]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[149]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[148]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[147]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[146]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[145]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[144]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[143]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[142]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[141]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[140]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[139]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[138]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[137]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[136]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[135]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[134]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[133]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[132]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[131]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[130]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[129]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[128]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[99]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[98]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[97]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[96]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[95]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[94]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[80]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[78]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[77]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[69]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[68]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[67]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[66]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[64]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/bus_rep_west.sdc b/sdc/bus_rep_west.sdc
new file mode 100644
index 0000000..8d7fb3d
--- /dev/null
+++ b/sdc/bus_rep_west.sdc
@@ -0,0 +1,187 @@
+###############################################################################
+# Created by write_sdc
+# Tue Dec 13 17:13:09 2022
+###############################################################################
+current_design bus_rep_west
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {ch_out[41]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[40]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[39]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[38]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[37]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[36]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[35]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[34]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[33]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[32]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[31]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[30]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[29]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[28]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[27]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/caravel.sdc b/sdc/caravel.sdc
index 70ea73d..11667e9 100644
--- a/sdc/caravel.sdc
+++ b/sdc/caravel.sdc
@@ -17,7 +17,7 @@
create_clock -name int_pll_clock -period 5.0000 [get_pins {mprj/u_pinmux/int_pll_clock}]
create_clock -name wbs_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_reg.u_wbs_ref_clkbuf.u_buf/X}]
-create_clock -name wbs_clk_i -period 26.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
+create_clock -name wbs_clk_i -period 30.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
create_clock -name cpu_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_reg.u_cpu_ref_clkbuf.u_buf/X}]
create_clock -name cpu_clk -period 40.0000 [get_pins {mprj/u_wb_host/cpu_clk}]
@@ -156,6 +156,10 @@
#################################################################
## User Case analysis
#################################################################
+set_case_analysis 0 [get_pins {mprj/u_peri/cfg_cska_peri[3]}]
+set_case_analysis 1 [get_pins {mprj/u_peri/cfg_cska_peri[2]}]
+set_case_analysis 1 [get_pins {mprj/u_peri/cfg_cska_peri[1]}]
+set_case_analysis 0 [get_pins {mprj/u_peri/cfg_cska_peri[0]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}]
@@ -167,25 +171,25 @@
set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}]
set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}]
-set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
-set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
-set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
-set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}]
set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[1]}]
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[0]}]
set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
-set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}]
set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}]
@@ -214,15 +218,18 @@
set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}]
set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}]
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}]
-set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}]
-set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}]
set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[3]}]
set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[2]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}]
-set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}]
+
+
+
#Keept the SRAM clock driving edge at pos edge
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}]
@@ -231,15 +238,6 @@
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[0]}]
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}]
-set_case_analysis 1 [get_pins {mprj/u_aes/cfg_cska[3]}]
-set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[2]}]
-set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[1]}]
-set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[0]}]
-
-set_case_analysis 1 [get_pins {mprj/u_fpu/cfg_cska[3]}]
-set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[2]}]
-set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[1]}]
-set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[0]}]
## FALSE PATHS (ASYNCHRONOUS INPUTS)
set_false_path -from [get_ports {resetb}]
@@ -304,6 +302,17 @@
set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]]
set_false_path -from [get_ports gpio]
+#### LA Input to wb_host are false path
+set_false_path -through [get_pins mprj/u_wb_host/la_data_in[*] ]
+
+### These reset has reset synchronozation
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/i2c_rstn ]
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/spi_rstn ]
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/usb_rstn ]
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/uart_rstn[*] ]
+
+
+
# add loads for output ports (pads)
set min_cap 5
set max_cap 10
diff --git a/sdc/peri_top.sdc b/sdc/peri_top.sdc
new file mode 100644
index 0000000..9a778d4
--- /dev/null
+++ b/sdc/peri_top.sdc
@@ -0,0 +1,401 @@
+###############################################################################
+# Created by write_sdc
+# Tue Dec 13 13:54:21 2022
+###############################################################################
+current_design peri_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+create_clock -name rtc_clk -period 100.0000 [get_ports {rtc_clk}]
+set_clock_transition 0.1500 [get_clocks {rtc_clk}]
+set_clock_uncertainty 0.2500 rtc_clk
+set_propagated_clock [get_clocks {rtc_clk}]
+set_clock_groups -name clock_group -logically_exclusive \
+ -group [get_clocks {mclk}]\
+ -group [get_clocks {rtc_clk}] -comment {Async Clock group}
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {s_reset_n}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {s_reset_n}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {inc_date_d}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {inc_date_d}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {inc_time_s}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {inc_time_s}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {rtc_intr}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {rtc_intr}]
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_peri}] 3.5000
+set_max_delay\
+ -to [get_ports {wbd_clk_peri}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {inc_date_d}]
+set_load -pin_load 0.0334 [get_ports {inc_time_s}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {rtc_intr}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_peri}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/pinmux_top.sdc b/sdc/pinmux_top.sdc
index 897365d..12e0b9a 100644
--- a/sdc/pinmux_top.sdc
+++ b/sdc/pinmux_top.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Wed Nov 30 08:04:48 2022
+# Tue Dec 13 10:55:59 2022
###############################################################################
current_design pinmux_top
###############################################################################
@@ -55,6 +55,8 @@
-group [get_clocks {user_clock2}] -comment {Async Clock group}
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
@@ -233,10 +235,13 @@
set_load -pin_load 0.0334 [get_ports {i2cm_clk_i}]
set_load -pin_load 0.0334 [get_ports {i2cm_data_i}]
set_load -pin_load 0.0334 [get_ports {i2cm_rst_n}]
+set_load -pin_load 0.0334 [get_ports {ir_rx}]
set_load -pin_load 0.0334 [get_ports {pll_ref_clk}]
set_load -pin_load 0.0334 [get_ports {pulse1m_mclk}]
set_load -pin_load 0.0334 [get_ports {qspim_rst_n}]
set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_cs}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wr}]
set_load -pin_load 0.0334 [get_ports {rtc_clk}]
set_load -pin_load 0.0334 [get_ports {soft_irq}]
set_load -pin_load 0.0334 [get_ports {spim_mosi}]
@@ -251,38 +256,6 @@
set_load -pin_load 0.0334 [get_ports {usb_rst_n}]
set_load -pin_load 0.0334 [get_ports {wbd_clk_pinmux}]
set_load -pin_load 0.0334 [get_ports {xtal_clk}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[0]}]
set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[25]}]
set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[24]}]
set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[23]}]
@@ -474,6 +447,53 @@
set_load -pin_load 0.0334 [get_ports {pinmux_debug[2]}]
set_load -pin_load 0.0334 [get_ports {pinmux_debug[1]}]
set_load -pin_load 0.0334 [get_ports {pinmux_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[0]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
@@ -560,10 +580,14 @@
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_oen}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_intr}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {int_pll_clock}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ir_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ir_tx}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {p_reset_n}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_ack}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_intr}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_sck}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_miso}]
@@ -619,6 +643,7 @@
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
@@ -633,6 +658,38 @@
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
diff --git a/sdc/qspim_top.sdc b/sdc/qspim_top.sdc
index fccd211..4d980e6 100644
--- a/sdc/qspim_top.sdc
+++ b/sdc/qspim_top.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Mon Nov 28 03:20:00 2022
+# Tue Dec 13 10:43:36 2022
###############################################################################
current_design qspim_top
###############################################################################
diff --git a/sdc/uart_i2c_usb_spi_top.sdc b/sdc/uart_i2c_usb_spi_top.sdc
index f1f6df4..87906a8 100644
--- a/sdc/uart_i2c_usb_spi_top.sdc
+++ b/sdc/uart_i2c_usb_spi_top.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Mon Nov 28 03:22:27 2022
+# Tue Dec 13 10:50:17 2022
###############################################################################
current_design uart_i2c_usb_spi_top
###############################################################################
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
index 8f2415b..d17c586 100644
--- a/sdc/user_project_wrapper.sdc
+++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Thu Dec 1 05:35:24 2022
+# Wed Dec 14 04:23:47 2022
###############################################################################
current_design user_project_wrapper
###############################################################################
diff --git a/sdc/wb_host.sdc b/sdc/wb_host.sdc
index 1176297..33e1c32 100644
--- a/sdc/wb_host.sdc
+++ b/sdc/wb_host.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Thu Dec 1 02:40:04 2022
+# Tue Dec 13 13:33:27 2022
###############################################################################
current_design wb_host
###############################################################################
diff --git a/sdc/wb_interconnect.sdc b/sdc/wb_interconnect.sdc
index 16bb907..130ea81 100644
--- a/sdc/wb_interconnect.sdc
+++ b/sdc/wb_interconnect.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Wed Nov 30 08:02:57 2022
+# Tue Dec 13 10:44:07 2022
###############################################################################
current_design wb_interconnect
###############################################################################
@@ -1063,6 +1063,8 @@
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_we_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[2]}]
@@ -1192,6 +1194,7 @@
set_load -pin_load 0.0334 [get_ports {s2_wbd_stb_o}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_we_o}]
set_load -pin_load 0.0334 [get_ports {wbd_clk_wi}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[7]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[6]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[5]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[4]}]
@@ -1199,6 +1202,10 @@
set_load -pin_load 0.0334 [get_ports {ch_clk_out[2]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[1]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[0]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[157]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[156]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[155]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[154]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[153]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[152]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[151]}]
@@ -1604,6 +1611,7 @@
set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[2]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[1]}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[10]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[9]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[8]}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[7]}]
@@ -1676,6 +1684,7 @@
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[4]}]
@@ -1683,6 +1692,10 @@
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[157]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[156]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[155]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[154]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[153]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[152]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[151]}]
diff --git a/sdc/ycr4_iconnect.sdc b/sdc/ycr4_iconnect.sdc
index fccebd8..15f4e2a 100644
--- a/sdc/ycr4_iconnect.sdc
+++ b/sdc/ycr4_iconnect.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Wed Nov 30 11:46:32 2022
+# Wed Dec 14 02:51:22 2022
###############################################################################
current_design ycr4_iconnect
###############################################################################
diff --git a/sdc/ycr_core_top.sdc b/sdc/ycr_core_top.sdc
index 8de6607..7d5e22c 100644
--- a/sdc/ycr_core_top.sdc
+++ b/sdc/ycr_core_top.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Wed Nov 30 14:16:33 2022
+# Wed Dec 14 02:58:45 2022
###############################################################################
current_design ycr_core_top
###############################################################################
diff --git a/sdc/ycr_intf.sdc b/sdc/ycr_intf.sdc
index 1decbbe..8f8a05e 100644
--- a/sdc/ycr_intf.sdc
+++ b/sdc/ycr_intf.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Thu Dec 1 02:18:56 2022
+# Wed Dec 14 02:55:34 2022
###############################################################################
current_design ycr_intf
###############################################################################
diff --git a/signoff/pinmux_top/OPENLANE_VERSION b/signoff/pinmux_top/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/pinmux_top/OPENLANE_VERSION
+++ b/signoff/pinmux_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/pinmux_top/PDK_SOURCES b/signoff/pinmux_top/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/pinmux_top/PDK_SOURCES
+++ b/signoff/pinmux_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/qspim_top/OPENLANE_VERSION
+++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/qspim_top/PDK_SOURCES
+++ b/signoff/qspim_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/user_project_wrapper/OPENLANE_VERSION
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/user_project_wrapper/PDK_SOURCES
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/ycr4_iconnect/OPENLANE_VERSION b/signoff/ycr4_iconnect/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/ycr4_iconnect/OPENLANE_VERSION
+++ b/signoff/ycr4_iconnect/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/ycr4_iconnect/PDK_SOURCES b/signoff/ycr4_iconnect/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/ycr4_iconnect/PDK_SOURCES
+++ b/signoff/ycr4_iconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/ycr_core_top/OPENLANE_VERSION
+++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/ycr_core_top/PDK_SOURCES
+++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/ycr_intf/OPENLANE_VERSION
+++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/ycr_intf/PDK_SOURCES
+++ b/signoff/ycr_intf/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/sta/scripts/ycr_intf.tcl b/sta/scripts/ycr_intf.tcl
new file mode 100644
index 0000000..8c444b1
--- /dev/null
+++ b/sta/scripts/ycr_intf.tcl
@@ -0,0 +1,50 @@
+
+ set ::env(USER_ROOT) ".."
+ set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-7/caravel"
+
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib
+
+ # User project netlist
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
+
+
+ link_design ycr_intf
+
+
+ ## User Project Spef
+ read_spef $::env(USER_ROOT)/spef/ycr_intf.spef
+
+
+ read_sdc -echo ./sdc/ycr_intf.sdc
+ set_propagated_clock [all_clocks]
+
+ report_annotated_check -list_annotated
+ report_annotated_check -list_not_annotated
+
+ check_setup -verbose > unconstraints.rpt
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
+ report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
+ report_worst_slack -max
+ report_worst_slack -min
+ report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10
+ report_check_types -max_slew -max_capacitance -max_fanout -violators > slew.cap.fanout.vio.rpt
+
+
+
diff --git a/sta/sdc/ycr_intf.sdc b/sta/sdc/ycr_intf.sdc
new file mode 100644
index 0000000..ecebcbc
--- /dev/null
+++ b/sta/sdc/ycr_intf.sdc
@@ -0,0 +1,262 @@
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
+create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
+create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
+
+create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock0} [get_ports dcache_mem_clk0]
+create_generated_clock -name dcache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock1} [get_ports dcache_mem_clk1]
+create_generated_clock -name icache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock0} [get_ports icache_mem_clk0]
+create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock1} [get_ports icache_mem_clk1]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {core_clk dcache_mem_clk0 dcache_mem_clk1 icache_mem_clk0 icache_mem_clk1}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {wb_clk}] -comment {Async Clock group}
+
+# Set case analysis
+set_case_analysis 0 [get_ports {cfg_ccska[3]}]
+set_case_analysis 0 [get_ports {cfg_ccska[2]}]
+set_case_analysis 0 [get_ports {cfg_ccska[1]}]
+set_case_analysis 0 [get_ports {cfg_ccska[0]}]
+
+set_case_analysis 0 [get_ports {cfg_wcska[3]}]
+set_case_analysis 0 [get_ports {cfg_wcska[2]}]
+set_case_analysis 0 [get_ports {cfg_wcska[1]}]
+set_case_analysis 0 [get_ports {cfg_wcska[0]}]
+
+#Assumed config are static
+set_false_path -from [get_ports {cfg_dcache_force_flush}]
+set_false_path -from [get_ports {cfg_dcache_pfet_dis}]
+set_false_path -from [get_ports {cfg_icache_ntag_pfet_dis}]
+set_false_path -from [get_ports {cfg_icache_pfet_dis}]
+
+
+set_false_path -from [get_ports {cfg_sram_lphase[1]}]
+set_false_path -from [get_ports {cfg_sram_lphase[0]}]
+
+#All reset has reset synchronization logic inside block ??
+set_false_path -from [get_ports {cpu_intf_rst_n}]
+set_false_path -from [get_ports {pwrup_rst_n}]
+set_false_path -from [get_ports {wb_rst_n}]
+
+#CORE Instruction Memory Interface
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_resp[*]}]
+
+
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_cmd}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_addr[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_bl[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_width[*]}]
+
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_bl[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_width[*]}]
+
+#Wishbone ICACHE I/F
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bry_o}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -max 2.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bry_o}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_lack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_err_i}]
+
+
+
+# CORE Data Memory Interface
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_resp[*]}]
+
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_cmd}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_width[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_addr[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_wdata[*]}]
+
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_width[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_wdata[*]}]
+
+
+# Data memory interface from router to WB bridge
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_resp[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_width[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_wdata[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_wdata[*]}]
+
+#WB Data Memory Interface
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}]
+
+
+## ICACHE PORT-0 SRAM Memory I/F
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}]
+
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}]
+
+## ICACHE PORT-1 SRAM Memory I/F
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_dout1[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_dout1[*]}]
+
+
+# Wishbone DCACHE I/F
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bry_o}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_cyc_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -max 5.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bry_o}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_err_i}]
+
+## DCACHE PORT-0 SRAM I/F
+set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}]
+set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}]
+set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}]
+
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}]
+
+
+## DCACHE PORT-1 SRAM I/F
+set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}]
+set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}]
+
+set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}]
+set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}]
+
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+set_max_transition 1.00 [current_design]
+set_max_capacitance 0.2 [current_design]
+set_max_fanout 10 [current_design]
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index dabc09e..cbcb742 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,19 +19,19 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_mcore_test1 user_mcore_test2
+PATTERNS = user_random user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_rtc user_ir_tx user_ir_rx user_mcore_test1 user_mcore_test2
all: ${PATTERNS}
echo "################# RTL Test case Summary #####################" > regression.rpt
xterm -e /usr/bin/watch -n 25 /bin/cat regression.rpt &
- for i in ${PATTERNS}; do \
- ( cd $$i && make | tee run.rtl.log && grep Monitor run.rtl.log | grep $$i >> ../regression.rpt) ; \
- done
- #echo "################# GL Test case Summary #####################" >> regression.rpt
- #\rm -rf */*.vvp
#for i in ${PATTERNS}; do \
- # ( cd $$i && make SIM=GL | tee run.gl.log && grep Monitor run.gl.log | grep $$i >> ../regression.rpt) ; \
+ # ( cd $$i && make | tee run.rtl.log && grep Monitor run.rtl.log | grep $$i >> ../regression.rpt) ; \
#done
+ echo "################# GL Test case Summary #####################" >> regression.rpt
+ \rm -rf */*.vvp
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make SIM=GL | tee run.gl.log && grep Monitor run.gl.log | grep $$i >> ../regression.rpt) ; \
+ done
echo "################# End of Test case Summary #####################" >> regression.rpt
DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
diff --git a/verilog/dv/arduino_arrays/arduino_arrays_tb.v b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
index f7f4808..a5bbcde 100644
--- a/verilog/dv/arduino_arrays/arduino_arrays_tb.v
+++ b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
@@ -145,14 +145,14 @@
* Pin-13 7 PD7/A1N1 digital_io[15]/analog_io[3]
* ********************************************************/
- wire [7:0] port_d_in = { io_out[15],
- io_out[14],
- io_out[13],
- io_out[10],
- io_out[9],
- io_out[8],
- io_out[7],
- io_out[6]
+ wire [7:0] port_d_in = { (io_oeb[15] == 1'b0)? io_out[15]: 1'b0 ,
+ (io_oeb[14] == 1'b0)? io_out[14]: 1'b0 ,
+ (io_oeb[13] == 1'b0)? io_out[13]: 1'b0 ,
+ (io_oeb[10] == 1'b0)? io_out[10]: 1'b0 ,
+ (io_oeb[9] == 1'b0)? io_out[9] : 1'b0 ,
+ (io_oeb[8] == 1'b0)? io_out[8] : 1'b0 ,
+ (io_oeb[7] == 1'b0)? io_out[7] : 1'b0 ,
+ (io_oeb[6] == 1'b0)? io_out[6] : 1'b0
};
@@ -270,8 +270,8 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
wire #1 io_oeb_33 = io_oeb[33];
wire #1 io_oeb_34 = io_oeb[34];
@@ -282,10 +282,10 @@
tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -304,7 +304,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
index 368b494..8df7f5c 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -236,8 +236,8 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
wire #1 io_oeb_33 = io_oeb[33];
wire #1 io_oeb_34 = io_oeb[34];
@@ -248,10 +248,10 @@
tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -270,7 +270,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
@@ -289,8 +289,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[7];
-assign io_in[6] = uart_rxd ;
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7] : 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart_rxd : 1'b0 ;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
index 7cce107..f85e347 100644
--- a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -286,22 +286,22 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -320,7 +320,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
@@ -339,8 +339,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[7];
-assign io_in[6] = uart_rxd ;
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7]: 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart_rxd : 1'b0;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
index eaf97d5..1a90746 100644
--- a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
@@ -232,9 +232,9 @@
// Integrate the Serial SPI to ad5204/5206 (4-/6-Channel Digital Potentiometers)
// https://www.analog.com/media/en/technical-documentation/data-sheets/ad5204_5206.pdf
// -----------------------------------------------------------------------------------
- wire sspi_sck = io_out[21];
- wire sspi_sdi = io_out[20];
- wire sspi_ssn = io_out[18];
+ wire sspi_sck = (io_oeb[21] == 1'b0) ? io_out[21] : 1'b0;
+ wire sspi_sdi = (io_oeb[20] == 1'b0) ? io_out[20] : 1'b0;
+ wire sspi_ssn = (io_oeb[18] == 1'b0) ? io_out[18] : 1'b0;
wire [2:0] p_channel; // potentiometer channel
wire [7:0] p_position; // potentiometer position
@@ -260,22 +260,22 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -294,7 +294,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
diff --git a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
index 30797d1..e2d9b91 100644
--- a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
+++ b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
@@ -163,28 +163,28 @@
reg [21:2] arduino_din;
assign {
//io_in[0], - Exclude RESET
- io_in[12],
- io_in[11],
- io_in[27],
- io_in[26],
- io_in[25],
- io_in[24],
- io_in[23],
- io_in[22],
- io_in[21],
- io_in[20],
- io_in[19],
- io_in[18],
- io_in[17],
- io_in[16],
- io_in[15],
- io_in[14],
- io_in[13],
- io_in[10],
- io_in[9],
- io_in[8]
+ io_in[12] ,
+ io_in[11] ,
+ io_in[27] ,
+ io_in[26] ,
+ io_in[25] ,
+ io_in[24] ,
+ io_in[23] ,
+ io_in[22] ,
+ io_in[21] ,
+ io_in[20] ,
+ io_in[19] ,
+ io_in[18] ,
+ io_in[17] ,
+ io_in[16] ,
+ io_in[15] ,
+ io_in[14] ,
+ io_in[13] ,
+ io_in[10] ,
+ io_in[9] ,
+ io_in[8]
// Uart pins io_in[2], io_in[1] are excluded
- } = (u_top.p_reset_n == 0) ? 23'hZZ_ZZZZ: arduino_din; // Tri-state untill Strap pull completed
+ } = (u_top.p_reset_n == 0) ? 23'hZZ_ZZZZ: (&io_oeb[27:8]) ? arduino_din: 'h0; // Tri-state untill Strap pull completed
reg[7:0] pinmap[0:22]; //ardiono to gpio pinmaping
@@ -359,8 +359,8 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
wire #1 io_oeb_33 = io_oeb[33];
wire #1 io_oeb_34 = io_oeb[34];
@@ -371,10 +371,10 @@
tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -393,7 +393,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
@@ -412,8 +412,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[7];
-assign io_in[6] = uart_rxd ;
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7] : 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart_rxd : 1'b0;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
index 6f91eae..0f1e173 100644
--- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
+++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -238,8 +238,8 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
wire #1 io_oeb_33 = io_oeb[33];
wire #1 io_oeb_34 = io_oeb[34];
@@ -250,10 +250,10 @@
tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -272,7 +272,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
@@ -291,8 +291,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[7];
-assign io_in[6] = uart_rxd ;
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7] : 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart_rxd : 1'b0 ;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
index 1ae2309..9df55f9 100644
--- a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -239,8 +239,8 @@
// --------------------------
tri scl,sda;
-assign sda = (io_oeb[26] == 1'b0) ? io_out[26] : 1'bz;
-assign scl = (io_oeb[27] == 1'b0) ? io_out[27]: 1'bz;
+assign sda = (io_oeb[26] == 1'b0) ? io_out[26] : 1'bz;
+assign scl = (io_oeb[27] == 1'b0) ? io_out[27]: 1'bz;
assign io_in[26] = sda;
assign io_in[27] = scl;
@@ -285,8 +285,8 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
wire #1 io_oeb_33 = io_oeb[33];
wire #1 io_oeb_34 = io_oeb[34];
@@ -297,10 +297,10 @@
tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -319,7 +319,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
@@ -338,8 +338,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[7];
-assign io_in[6] = uart_rxd ;
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7]: 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart_rxd : 1'b0;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
index 882a549..a7b1e87 100644
--- a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
+++ b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
@@ -266,8 +266,8 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
wire #1 io_oeb_33 = io_oeb[33];
wire #1 io_oeb_34 = io_oeb[34];
@@ -278,10 +278,10 @@
tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -300,7 +300,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
@@ -319,8 +319,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[7];
-assign io_in[6] = uart_rxd ;
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7]: 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart_rxd : 1'b0;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
index 45fe601..330f568 100644
--- a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
+++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
@@ -258,8 +258,8 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
wire #1 io_oeb_33 = io_oeb[33];
wire #1 io_oeb_34 = io_oeb[34];
@@ -270,10 +270,10 @@
tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -292,7 +292,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
@@ -310,8 +310,8 @@
// --------------------------
wire uart0_txd,uart0_rxd;
-assign uart0_txd = io_out[7];
-assign io_in[6] = uart0_rxd ;
+assign uart0_txd = (io_oeb[7] == 1'b0) ? io_out[7]: 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart0_rxd : 1'b0;
uart_agent tb_uart0(
.mclk (clock ),
@@ -324,8 +324,8 @@
// --------------------------
wire uart1_txd,uart1_rxd;
-assign uart1_txd = io_out[10];
-assign io_in[8] = uart1_rxd ;
+assign uart1_txd = (io_oeb[10] == 1'b0) ? io_out[10] : 1'b0;
+assign io_in[8] = (io_oeb[8] == 1'b1) ? uart1_rxd : 1'b0;
uart_agent tb_uart1(
.mclk (clock ),
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
index 46e8d54..f2d4f91 100644
--- a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
+++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
@@ -172,22 +172,22 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -206,7 +206,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
diff --git a/verilog/dv/arduino_string/arduino_string_tb.v b/verilog/dv/arduino_string/arduino_string_tb.v
index 567a67c..b52d2d6 100644
--- a/verilog/dv/arduino_string/arduino_string_tb.v
+++ b/verilog/dv/arduino_string/arduino_string_tb.v
@@ -231,8 +231,8 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
wire #1 io_oeb_33 = io_oeb[33];
wire #1 io_oeb_34 = io_oeb[34];
@@ -243,10 +243,10 @@
tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -265,7 +265,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
@@ -284,8 +284,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[7];
-assign io_in[6] = uart_rxd ;
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7] : 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart_rxd : 1'b0 ;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
index 8493415..527f790 100644
--- a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
+++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
@@ -294,8 +294,8 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
wire #1 io_oeb_33 = io_oeb[33];
wire #1 io_oeb_34 = io_oeb[34];
@@ -306,10 +306,10 @@
tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -328,7 +328,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
@@ -346,8 +346,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[7];
-assign io_in[6] = uart_rxd ;
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7] : 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart_rxd : 1'b0 ;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
index f3f29e1..77a1f7f 100644
--- a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
+++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
@@ -245,8 +245,8 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
wire #1 io_oeb_33 = io_oeb[33];
wire #1 io_oeb_34 = io_oeb[34];
@@ -257,10 +257,10 @@
tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -279,7 +279,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
@@ -297,8 +297,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[7];
-assign io_in[6] = uart_rxd ;
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7] : 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart_rxd : 1'b0 ;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v b/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
index 43929a1..67c4996 100644
--- a/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
+++ b/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
@@ -270,8 +270,8 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
wire #1 io_oeb_33 = io_oeb[33];
wire #1 io_oeb_34 = io_oeb[34];
@@ -282,10 +282,10 @@
tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -304,7 +304,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31] == 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("none"))
u_sram (
@@ -321,7 +321,7 @@
//-----------------------------------------------
// WS281X BFM integration
//----------------------------------------------
-assign ws281x_port[0] = io_out[8];
+assign ws281x_port[0] = (io_oeb[8] == 1'b0) ? io_out[8] : 1'b0;
bfm_ws281x #(
.PORT_ID(0),
@@ -335,7 +335,7 @@
//-----------------------------------------------
// WS281X BFM integration
//----------------------------------------------
-assign ws281x_port[1] = io_out[9];
+assign ws281x_port[1] = (io_oeb[9] == 1'b0 ) ? io_out[9] : 1'b0;
bfm_ws281x #(
.PORT_ID(1),
@@ -349,7 +349,7 @@
//-----------------------------------------------
// WS281X BFM integration
//----------------------------------------------
-assign ws281x_port[2] = io_out[13];
+assign ws281x_port[2] = (io_oeb[13] == 1'b0) ? io_out[13] : 1'b0 ;
bfm_ws281x #(
.PORT_ID(2),
@@ -363,7 +363,7 @@
//-----------------------------------------------
// WS281X BFM integration
//----------------------------------------------
-assign ws281x_port[3] = io_out[17];
+assign ws281x_port[3] = (io_oeb[17] == 1'b0) ? io_out[17] : 1'b0 ;
bfm_ws281x #(
.PORT_ID(3),
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv
index 75cd3e9..7ae4257 100644
--- a/verilog/dv/common/agents/user_tasks.sv
+++ b/verilog/dv/common/agents/user_tasks.sv
@@ -90,7 +90,11 @@
begin
// Run in Fast Sim Mode
`ifdef GL
- force u_top.u_wb_host._10252_.Q= 1'b1;
+ // Note During wb_host resynth this FF is changes,
+ // Keep cross-check during Gate Sim
+ force u_top.u_wb_host._10265_.Q= 1'b1;
+ //force u_top.u_wb_host.u_reg.u_fastsim_buf.u_buf.X = 1'b1;
+ //force u_top.u_wb_host.u_reg.cfg_fast_sim = 1'b1;
`else
force u_top.u_wb_host.u_reg.u_fastsim_buf.X = 1'b1;
`endif
diff --git a/verilog/dv/common/bfm/bfm_ir.v b/verilog/dv/common/bfm/bfm_ir.v
new file mode 100644
index 0000000..8de85a1
--- /dev/null
+++ b/verilog/dv/common/bfm/bfm_ir.v
@@ -0,0 +1,136 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
+`timescale 1ns/1ps
+
+module bfm_ir (
+ output reg ir_signal
+);
+
+ reg p_polarity;
+ integer p_period;
+ integer i;
+ integer state;
+
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // TASK : init
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ task init(
+ input polarity,
+ input integer tick_period_ns
+ );
+ begin
+ $display("simetime = %g : Init IR interface with", $time);
+ $display("simetime = %g : - polarity = %b", $time, polarity);
+ $display("simetime = %g : - period to %d ns", $time, tick_period_ns);
+
+ // Parameters
+ p_polarity = polarity;
+ p_period = tick_period_ns;
+
+ // Init output signals
+ ir_signal = ~p_polarity;
+
+ end
+ endtask
+
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // TASK : write
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ task send_nec(
+ input [7:0] addr,
+ input [7:0] data
+ );
+ begin
+ $display("simetime = %g : Send IR NEC trame (0x%h -> 0x%h)", $time, addr, data);
+
+ state = 0;
+ send_start();
+
+ state = 1;
+ // Send address
+ for (i=0 ; i<8 ; i=i+1) begin
+ send_bit(addr[i]);
+ end
+
+ state = 2;
+ // Send address (complement)
+ for (i=0 ; i<8 ; i=i+1) begin
+ send_bit(~addr[i]);
+ end
+
+ state = 3;
+ // Send data
+ for (i=0 ; i<8 ; i=i+1) begin
+ send_bit(data[i]);
+ end
+
+ state = 4;
+ // Send data (complement)
+ for (i=0 ; i<8 ; i=i+1) begin
+ send_bit(~data[i]);
+ end
+
+ state = 5;
+ // Send stop
+ send_stop();
+ state = 6;
+
+
+ end
+ endtask
+
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // TASK : send_start
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ task send_start;
+ begin
+ ir_signal = p_polarity;
+ #(p_period*16) ir_signal = ~p_polarity;
+ #(p_period*8) ir_signal = p_polarity;
+ end
+ endtask
+
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // TASK : send_bit
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ task send_bit(
+ input reg value
+ );
+ begin
+ ir_signal = p_polarity;
+ #(p_period) ir_signal = ~p_polarity;
+ if (value == 1'b1) begin
+ #(p_period*3) ir_signal = p_polarity;
+ end else begin
+ #(p_period) ir_signal = p_polarity;
+ end
+ end
+ endtask
+
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ // TASK : send_stop
+ /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+ task send_stop;
+ begin
+ ir_signal = p_polarity;
+ #(p_period) ir_signal = ~p_polarity;
+ end
+ endtask
+
+endmodule
diff --git a/verilog/dv/common/firmware/int_reg_map.h b/verilog/dv/common/firmware/int_reg_map.h
index fa79ec1..4c56c49 100644
--- a/verilog/dv/common/firmware/int_reg_map.h
+++ b/verilog/dv/common/firmware/int_reg_map.h
@@ -90,3 +90,50 @@
#define reg_uart1_txfifo_stat (*(volatile uint32_t*)0x1001011C) // Reg-7
#define reg_uart1_rxfifo_stat (*(volatile uint32_t*)0x10010120) // Reg-8
+// AES Encription Register
+#define reg_aes_enc_ctrl (*(volatile uint32_t*)0x0C490080) // Reg-0
+
+#define reg_aes_enc_key_dw0 (*(volatile uint32_t*)0x0C490084) // Reg-1
+#define reg_aes_enc_key_dw1 (*(volatile uint32_t*)0x0C490088) // Reg-2
+#define reg_aes_enc_key_dw2 (*(volatile uint32_t*)0x0C49008C) // Reg-3
+#define reg_aes_enc_key_dw3 (*(volatile uint32_t*)0x0C490090) // Reg-4
+#define reg_aes_enc_key_bptr (*(volatile uint8_t*)0x0C490093) // Last Addr Location
+
+#define reg_aes_enc_text_in_dw0 (*(volatile uint32_t*)0x0C490094) // Reg-5
+#define reg_aes_enc_text_in_dw1 (*(volatile uint32_t*)0x0C490098) // Reg-6
+#define reg_aes_enc_text_in_dw2 (*(volatile uint32_t*)0x0C49009C) // Reg-7
+#define reg_aes_enc_text_in_dw3 (*(volatile uint32_t*)0x0C4900A0) // Reg-8
+#define reg_aes_enc_text_in_bptr (*(volatile uint8_t*)0x0C4900A3) // Last Addr Location
+
+#define reg_aes_enc_text_out_dw0 (*(volatile uint32_t*)0x0C4900A4) // Reg-9
+#define reg_aes_enc_text_out_dw1 (*(volatile uint32_t*)0x0C4900A8) // Reg-10
+#define reg_aes_enc_text_out_dw2 (*(volatile uint32_t*)0x0C4900AC) // Reg-11
+#define reg_aes_enc_text_out_dw3 (*(volatile uint32_t*)0x0C4900B0) // Reg-12
+#define reg_aes_enc_text_out_bptr (*(volatile uint8_t*)0x0C4900B3) // Last Addr Location
+
+// AES Decryption Register
+#define reg_aes_dec_ctrl (*(volatile uint32_t*)0x0C4900C0) // Reg-0
+#define reg_aes_dec_key_dw0 (*(volatile uint32_t*)0x0C4900C4) // Reg-1
+#define reg_aes_dec_key_dw1 (*(volatile uint32_t*)0x0C4900C8) // Reg-2
+#define reg_aes_dec_key_dw2 (*(volatile uint32_t*)0x0C4900CC) // Reg-3
+#define reg_aes_dec_key_dw3 (*(volatile uint32_t*)0x0C4900D0) // Reg-4
+#define reg_aes_dec_key_bptr (*(volatile uint8_t*)0x0C4900D3) // Last Addr Location
+
+#define reg_aes_dec_text_in_dw0 (*(volatile uint32_t*)0x0C4900D4) // Reg-5
+#define reg_aes_dec_text_in_dw1 (*(volatile uint32_t*)0x0C4900D8) // Reg-6
+#define reg_aes_dec_text_in_dw2 (*(volatile uint32_t*)0x0C4900DC) // Reg-7
+#define reg_aes_dec_text_in_dw3 (*(volatile uint32_t*)0x0C4900E0) // Reg-8
+#define reg_aes_dec_text_in_bptr (*(volatile uint8_t*)0x0C4900E3) // Last Addr Location
+
+#define reg_aes_dec_text_out_dw0 (*(volatile uint32_t*)0x0C4900E4) // Reg-9
+#define reg_aes_dec_text_out_dw1 (*(volatile uint32_t*)0x0C4900E8) // Reg-10
+#define reg_aes_dec_text_out_dw2 (*(volatile uint32_t*)0x0C4900EC) // Reg-11
+#define reg_aes_dec_text_out_dw3 (*(volatile uint32_t*)0x0C4900F0) // Reg-12
+#define reg_aes_dec_text_out_bptr (*(volatile uint8_t*)0x0C4900F3) // Last Addr Location
+
+// FPU Core
+#define reg_fpu_ctrl (*(volatile uint32_t*)0x0C490100) // Reg-0
+#define reg_fpu_din1 (*(volatile uint32_t*)0x0C490104) // Reg-1
+#define reg_fpu_din2 (*(volatile uint32_t*)0x0C490108) // Reg-2
+#define reg_fpu_res (*(volatile uint32_t*)0x0C49010C) // Reg-3
+
diff --git a/verilog/dv/uart_master_test1/Makefile b/verilog/dv/uart_master_test1/Makefile
new file mode 100644
index 0000000..12331ba
--- /dev/null
+++ b/verilog/dv/uart_master_test1/Makefile
@@ -0,0 +1,232 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+DESIGNS?=../../..
+CONFIG = caravel_user_project
+TOOLS?=/opt/riscv32i/
+
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/env.makefile
+########################################################
+#######################################################################
+## Global Environment Variables for local repo
+#######################################################################
+
+export PDK_PATH = $(PDK_ROOT)/sky130A
+export VIP_PATH = $(CORE_VERILOG_PATH)/dv/vip
+export FIRMWARE_PATH = $(CORE_VERILOG_PATH)/dv/firmware
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+export CARAVEL_VERILOG_PATH ?= $(CARAVEL_ROOT)/verilog
+export CORE_VERILOG_PATH ?= $(CARAVEL_ROOT)/mgmt_core_wrapper/verilog
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+
+export CARAVEL_PATH = $(CARAVEL_VERILOG_PATH)
+export VERILOG_PATH = $(CORE_VERILOG_PATH)
+
+#######################################################################
+## Compiler Information
+#######################################################################
+
+export TOOLS ?= /opt/riscv32i
+export GCC_PATH ?= $(TOOLS)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+
+
+
+
+
+
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/var.makefile
+########################################################
+
+CPU=vexriscv
+CPUFAMILY=riscv
+CPUFLAGS=-march=rv32i -mabi=ilp32 -D__vexriscv__
+CPUENDIANNESS=little
+CLANG=0
+
+
+######################################################
+# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+######################################################
+
+ifeq ($(CPU),picorv32)
+ LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+ SOURCE_FILES=$(FIRMWARE_PATH)/start.s
+ VERILOG_FILES=
+endif
+
+ifeq ($(CPU),ibex)
+ LINKER_SCRIPT=$(FIRMWARE_PATH)/link_ibex.ld
+ SOURCE_FILES=$(FIRMWARE_PATH)/crt0_ibex.S $(FIRMWARE_PATH)/simple_system_common.c
+# VERILOG_FILES=../ibex/*
+ VERILOG_FILES=
+endif
+
+ifeq ($(CPU),vexriscv)
+# LINKER_SCRIPT=$(FIRMWARE_PATH)/sections_vexriscv.lds
+# SOURCE_FILES=$(FIRMWARE_PATH)/start_caravel_vexriscv.s
+ LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+ SOURCE_FILES=$(FIRMWARE_PATH)/crt0_vex.S $(FIRMWARE_PATH)/isr.c
+ VERILOG_FILES=
+endif
+
+
+
+#####################################################
+#include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+######################################################
+
+export IVERILOG_DUMPER = fst
+
+# RTL/GL/GL_SDF
+SIM?=RTL
+DUMP?=OFF
+
+
+.SUFFIXES:
+
+
+all: ${BLOCKS:=.vcd} ${BLOCKS:=.lst}
+
+hex: ${BLOCKS:=.hex}
+
+#.SUFFIXES:
+
+##############################################################################
+# Comiple firmeware
+##############################################################################
+%.elf: %.c $(LINKER_SCRIPT) $(SOURCE_FILES)
+ ${GCC_PREFIX}-gcc -g \
+ -I$(FIRMWARE_PATH) \
+ -I$(VERILOG_PATH)/dv/generated \
+ -I$(VERILOG_PATH)/dv/ \
+ -I$(VERILOG_PATH)/common \
+ $(CPUFLAGS) \
+ -Wl,-Bstatic,-T,$(LINKER_SCRIPT),--strip-debug \
+ -ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $<
+
+%.lst: %.elf
+ ${GCC_PREFIX}-objdump -d -S $< > $@
+
+%.hex: %.elf
+ ${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -ie 's/@10/@00/g' $@
+
+%.bin: %.elf
+ ${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+
+##############################################################################
+# Runing the simulations
+##############################################################################
+
+%.vvp: %_tb.v %.hex
+
+## RTL
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+ -o $@ $<
+ else
+ iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+ -o $@ $<
+ endif
+endif
+
+##GL
+ifeq ($(SIM),GL)
+ ifeq ($(DUMP),OFF)
+ iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+ -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
+ else
+ iverilog -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+ -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
+ endif
+endif
+
+## GL+SDF
+ifeq ($(SIM),GL_SDF)
+ ifeq ($(CONFIG),caravel_user_project)
+ cvc64 +interp \
+ +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+ +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \
+ -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
+ -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $<
+ else
+ cvc64 +interp \
+ +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+ +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \
+ -f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \
+ -f $CARAVEL_PATH/gl/__user_project_wrapper.v $<
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+# twinwave: RTL-%.vcd GL-%.vcd
+# twinwave RTL-$@ * + GL-$@ *
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+
+# ---- Clean ----
+
+clean:
+ \rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe
+
+.PHONY: clean hex all
+
+
+
+
+
+
diff --git a/verilog/dv/uart_master_test1/run_verilog b/verilog/dv/uart_master_test1/run_verilog
new file mode 100644
index 0000000..5ffed3c
--- /dev/null
+++ b/verilog/dv/uart_master_test1/run_verilog
@@ -0,0 +1,20 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# //
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# // http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+
+#iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I /home/dinesha/workarea/pdk/sky130A -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog -I ../ -I../../../verilog/rtl -I../../../verilog/gl -I ../../../verilog wb_port_tb.v -o wb_port.vvp
+iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -DGL -I /home/dinesha/workarea/pdk/sky130A -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog -I ../ -I../../../verilog/rtl -I../../../verilog/gl -I ../../../verilog wb_port_tb.v -o wb_port.vvp
diff --git a/verilog/dv/uart_master_test1/uart_master_test1.c b/verilog/dv/uart_master_test1/uart_master_test1.c
new file mode 100644
index 0000000..991bdc5
--- /dev/null
+++ b/verilog/dv/uart_master_test1/uart_master_test1.c
@@ -0,0 +1,162 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+// User Project Slaves (0x3000_0000)
+
+
+#define GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP 0x1C00
+
+#define SC_SIM_OUTPORT (0xf0000000)
+
+/*
+ RiscV Hello World test.
+ - Wake up the Risc V
+ - Boot from SPI Flash
+ - Riscv Write Hello World to SDRAM,
+ - External Wishbone read back validation the data
+*/
+int i = 0;
+int clk = 0;
+int uart_cfg = 0;
+void main()
+{
+
+ //int bFail = 0;
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+
+ Input: 0000_0001_0000_1111 (0x1800) = GPIO_MODE_USER_STD_BIDIRECTIONAL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ //reg_spi_enable = 1;
+ //reg_wb_enable = 1;
+ // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ //reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ //reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // /* Apply configuration */
+ //reg_mprj_xfer = 1;
+ //while (reg_mprj_xfer == 1);
+
+ reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
+
+ // Flag start of the test
+ reg_mprj_datal = 0xAB600000;
+
+ //-----------------------------------------------------
+ // Start of User Functionality and take over the GPIO Pins
+ // --------------------------------------------------------------------
+ // User block decide on the GPIO function
+ // io[6] to 37 are set to default bio-direction using user_define.h file
+ //---------------------------------------------------------------------
+
+ //reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_35 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_34 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+ //reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+
+ // /* Apply configuration */
+ //reg_mprj_xfer = 1;
+ //while (reg_mprj_xfer == 1);
+
+ reg_la0_data = 0x000;
+ //reg_la0_data = 0x000;
+ //reg_la0_data |= 0x1; // bit[0] - Remove Software Reset
+ //reg_la0_data |= 0x1; // bit[1] - Enable Transmit Path
+ //reg_la0_data |= 0x2; // bit[2] - Enable Receive Path
+ //reg_la0_data |= 0x4; // bit[3] - Set 2 Stop Bit
+ //reg_la0_data |= 0x0; // bit[15:4] - 16x Baud Clock
+ //reg_la0_data |= 0x0; // bit[17:16] - Priority mode = 0
+ reg_la0_data = 0x001;
+ reg_la0_data = 0x00F;
+
+
+
+}
diff --git a/verilog/dv/uart_master_test1/uart_master_test1_tb.v b/verilog/dv/uart_master_test1/uart_master_test1_tb.v
new file mode 100644
index 0000000..fe63f38
--- /dev/null
+++ b/verilog/dv/uart_master_test1/uart_master_test1_tb.v
@@ -0,0 +1,287 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+`include "uart_agent.v"
+
+`define TB_HEX "uart_master_test1.hex"
+`define TB_TOP uart_master_test1_tb
+module `TB_TOP;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ wire [15:0] checkbits;
+
+//----------------------------------
+// Uart Configuration
+// ---------------------------------
+reg [1:0] uart_data_bit ;
+reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+reg uart_stick_parity ; // 1: force even parity
+reg uart_parity_en ; // parity enable
+reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+reg [7:0] uart_data ;
+reg [15:0] uart_divisor ; // divided by n * 16
+reg [15:0] uart_timeout ;// wait time limit
+
+reg [15:0] uart_rx_nu ;
+reg [15:0] uart_tx_nu ;
+reg [7:0] uart_write_data [0:39];
+reg uart_fifo_enable ; // fifo mode disable
+
+reg [31:0] read_data ;
+reg flag;
+reg test_fail ;
+reg [15:0] strap_in;
+
+
+ assign checkbits = mprj_io[31:16];
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(2, `TB_TOP);
+ $dumpvars(0, `TB_TOP.tb_master_uart);
+ $dumpvars(1, `TB_TOP.u_top.mprj.u_wb_host);
+ $dumpvars(0, `TB_TOP.u_top.mprj.u_wb_host.u_uart2wb);
+ $dumpvars(0, `TB_TOP.u_top.mprj.u_pinmux);
+ end
+ `endif
+
+ initial begin
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (400) begin
+ repeat (10000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ $display ("##########################################################");
+ `ifdef GL
+ $display ("Monitor: Timeout, %m (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, %m (RTL) Failed");
+ `endif
+ $display ("##########################################################");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+
+ strap_in = 0;
+ strap_in[`PSTRAP_UARTM_CFG] = 2'b11; // uart master config control - load from LA
+ apply_strap(strap_in);
+
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ uart_divisor = 15;// divided by n * 16
+ uart_timeout = 200;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
+ tb_master_uart.debug_mode = 0; // disable debug display
+
+ #200; // Wait for reset removal
+
+ // wait(checkbits == 16'h AB60);
+ // $display("Monitor: UART Master Test Started");
+
+ repeat (10000) @(posedge clock);
+ tb_master_uart.uart_init;
+ tb_master_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+ //$write ("\n(%t)Response:\n",$time);
+ // Wait for Initial Command Format from the uart master
+ flag = 0;
+ while(flag == 0)
+ begin
+ tb_master_uart.read_char(read_data,flag);
+ $write ("%c",read_data);
+ end
+
+
+
+ // Remove Wb Reset
+ uartm_reg_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ repeat (2) @(posedge clock);
+ #1;
+
+ $display("Monitor: Writing expected value");
+
+ test_fail = 0;
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
+
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Passed");
+ `else
+ $display("Monitor: %m (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Failed");
+ `else
+ $display("Monitor: %m (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ #100
+
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ //CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ //CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #100;
+ power1 <= 1'b1;
+ #100;
+ power2 <= 1'b1;
+ #100;
+ power3 <= 1'b1;
+ #100;
+ power4 <= 1'b1;
+ end
+
+ //always @(mprj_io) begin
+ // #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+ //end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire USER_VDD3V3 = power3;
+ wire USER_VDD1V8 = power4;
+ wire VSS = 1'b0;
+
+ caravel u_top (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (USER_VDD3V3),
+ .vdda2 (USER_VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (USER_VDD1V8),
+ .vccd2 (USER_VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME(`TB_HEX)
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+
+
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+ end
+`endif
+
+
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = mprj_io[7];
+assign mprj_io[6] = uart_rxd ;
+
+uart_agent tb_master_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
+
+
+`include "caravel_task.sv"
+`include "uart_master_tasks.sv"
+
+endmodule
+
+`default_nettype wire
diff --git a/verilog/dv/uart_master_test2/Makefile b/verilog/dv/uart_master_test2/Makefile
new file mode 100644
index 0000000..b333a87
--- /dev/null
+++ b/verilog/dv/uart_master_test2/Makefile
@@ -0,0 +1,207 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+DESIGNS?=../../..
+CONFIG = caravel_user_project
+TOOLS?=/opt/riscv32i/
+
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/env.makefile
+########################################################
+#######################################################################
+## Global Environment Variables for local repo
+#######################################################################
+
+export PDK_PATH = $(PDK_ROOT)/sky130A
+export VIP_PATH = $(CORE_VERILOG_PATH)/dv/vip
+export FIRMWARE_PATH = $(CORE_VERILOG_PATH)/dv/firmware
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+export CARAVEL_VERILOG_PATH ?= $(CARAVEL_ROOT)/verilog
+export CORE_VERILOG_PATH ?= $(CARAVEL_ROOT)/mgmt_core_wrapper/verilog
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+
+export CARAVEL_PATH = $(CARAVEL_VERILOG_PATH)
+export VERILOG_PATH = $(CORE_VERILOG_PATH)
+
+#######################################################################
+## Compiler Information
+#######################################################################
+
+export TOOLS ?= /opt/riscv32i
+export GCC_PATH ?= $(TOOLS)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+
+
+
+
+
+
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/var.makefile
+########################################################
+
+CPU=vexriscv
+CPUFAMILY=riscv
+CPUFLAGS=-march=rv32i -mabi=ilp32 -D__vexriscv__
+CPUENDIANNESS=little
+CLANG=0
+
+
+######################################################
+# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+######################################################
+
+ifeq ($(CPU),picorv32)
+ LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+ SOURCE_FILES=$(FIRMWARE_PATH)/start.s
+ VERILOG_FILES=
+endif
+
+ifeq ($(CPU),ibex)
+ LINKER_SCRIPT=$(FIRMWARE_PATH)/link_ibex.ld
+ SOURCE_FILES=$(FIRMWARE_PATH)/crt0_ibex.S $(FIRMWARE_PATH)/simple_system_common.c
+# VERILOG_FILES=../ibex/*
+ VERILOG_FILES=
+endif
+
+ifeq ($(CPU),vexriscv)
+# LINKER_SCRIPT=$(FIRMWARE_PATH)/sections_vexriscv.lds
+# SOURCE_FILES=$(FIRMWARE_PATH)/start_caravel_vexriscv.s
+ LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+ SOURCE_FILES=$(FIRMWARE_PATH)/crt0_vex.S $(FIRMWARE_PATH)/isr.c
+ VERILOG_FILES=
+endif
+
+
+
+#####################################################
+#include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+######################################################
+
+export IVERILOG_DUMPER = fst
+
+# RTL/GL/GL_SDF
+SIM?=RTL
+DUMP?=OFF
+
+
+.SUFFIXES:
+
+
+all: ${BLOCKS:=.vcd} ${BLOCKS:=.vvp}
+
+
+#.SUFFIXES:
+
+
+##############################################################################
+# Runing the simulations
+##############################################################################
+
+%.vvp: %_tb.v
+
+## RTL
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+ -o $@ $<
+ else
+ iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+ -o $@ $<
+ endif
+endif
+
+##GL
+ifeq ($(SIM),GL)
+ ifeq ($(DUMP),OFF)
+ iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+ -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
+ else
+ iverilog -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+ -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
+ endif
+endif
+
+## GL+SDF
+ifeq ($(SIM),GL_SDF)
+ ifeq ($(CONFIG),caravel_user_project)
+ cvc64 +interp \
+ +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+ +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \
+ -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
+ -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $<
+ else
+ cvc64 +interp \
+ +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+ +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \
+ -f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \
+ -f $CARAVEL_PATH/gl/__user_project_wrapper.v $<
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+# twinwave: RTL-%.vcd GL-%.vcd
+# twinwave RTL-$@ * + GL-$@ *
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+
+# ---- Clean ----
+
+clean:
+ \rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe
+
+.PHONY: clean hex all
+
+
+
+
+
+
diff --git a/verilog/dv/uart_master_test2/run_verilog b/verilog/dv/uart_master_test2/run_verilog
new file mode 100644
index 0000000..5ffed3c
--- /dev/null
+++ b/verilog/dv/uart_master_test2/run_verilog
@@ -0,0 +1,20 @@
+# //////////////////////////////////////////////////////////////////////////////
+# // SPDX-FileCopyrightText: 2021, Dinesh Annayya
+# //
+# // Licensed under the Apache License, Version 2.0 (the "License");
+# // you may not use this file except in compliance with the License.
+# // You may obtain a copy of the License at
+# //
+# // http://www.apache.org/licenses/LICENSE-2.0
+# //
+# // Unless required by applicable law or agreed to in writing, software
+# // distributed under the License is distributed on an "AS IS" BASIS,
+# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# // See the License for the specific language governing permissions and
+# // limitations under the License.
+# // SPDX-License-Identifier: Apache-2.0
+# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+# // //////////////////////////////////////////////////////////////////////////
+
+#iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I /home/dinesha/workarea/pdk/sky130A -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog -I ../ -I../../../verilog/rtl -I../../../verilog/gl -I ../../../verilog wb_port_tb.v -o wb_port.vvp
+iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -DGL -I /home/dinesha/workarea/pdk/sky130A -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl -I /home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog -I ../ -I../../../verilog/rtl -I../../../verilog/gl -I ../../../verilog wb_port_tb.v -o wb_port.vvp
diff --git a/verilog/dv/uart_master_test2/uart_master_test2_tb.v b/verilog/dv/uart_master_test2/uart_master_test2_tb.v
new file mode 100644
index 0000000..b757926
--- /dev/null
+++ b/verilog/dv/uart_master_test2/uart_master_test2_tb.v
@@ -0,0 +1,289 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+`include "uart_agent.v"
+
+`define TB_HEX "uart_master.hex"
+`define TB_TOP uart_master_test2
+module `TB_TOP;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ wire [15:0] checkbits;
+
+//----------------------------------
+// Uart Configuration
+// ---------------------------------
+reg [1:0] uart_data_bit ;
+reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+reg uart_stick_parity ; // 1: force even parity
+reg uart_parity_en ; // parity enable
+reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+reg [7:0] uart_data ;
+reg [15:0] uart_divisor ; // divided by n * 16
+reg [15:0] uart_timeout ;// wait time limit
+
+reg [15:0] uart_rx_nu ;
+reg [15:0] uart_tx_nu ;
+reg [7:0] uart_write_data [0:39];
+reg uart_fifo_enable ; // fifo mode disable
+
+reg [31:0] read_data ;
+reg flag;
+reg test_fail ;
+reg [15:0] strap_in;
+
+
+ assign checkbits = mprj_io[31:16];
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(2, `TB_TOP);
+ $dumpvars(0, `TB_TOP.tb_master_uart);
+ $dumpvars(0, `TB_TOP.u_top.mprj.u_wb_host.u_uart2wb);
+ $dumpvars(1, `TB_TOP.tb_master_uart);
+ $dumpvars(0, `TB_TOP.u_top.mprj.u_pinmux);
+ end
+ `endif
+
+ initial begin
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (400) begin
+ repeat (10000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ $display ("##########################################################");
+ `ifdef GL
+ $display ("Monitor: Timeout, %m (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, %m (RTL) Failed");
+ `endif
+ $display ("##########################################################");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+
+ strap_in = 0;
+ strap_in[`PSTRAP_UARTM_CFG] = 0; // uart master config control - load from LA
+ apply_strap(strap_in);
+
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ tb_set_uart_baud(50000000,288000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+ uart_timeout = 200;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
+ tb_master_uart.debug_mode = 0; // disable debug display
+
+ #200; // Wait for reset removal
+
+ // wait(checkbits == 16'h AB60);
+ // $display("Monitor: UART Master Test Started");
+
+ repeat (10000) @(posedge clock);
+ tb_master_uart.uart_init;
+ tb_master_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+ tb_master_uart.write_char(8'hA); // New line for auto detect
+ //$write ("\n(%t)Response:\n",$time);
+ // Wait for Initial Command Format from the uart master
+ flag = 0;
+ while(flag == 0)
+ begin
+ tb_master_uart.read_char(read_data,flag);
+ $write ("%c",read_data);
+ end
+
+
+
+ // Remove Wb Reset
+ uartm_reg_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ repeat (2) @(posedge clock);
+ #1;
+
+ $display("Monitor: Writing expected value");
+
+ test_fail = 0;
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
+
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Passed");
+ `else
+ $display("Monitor: %m (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Failed");
+ `else
+ $display("Monitor: %m (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ #100
+
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ //CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ //CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #100;
+ power1 <= 1'b1;
+ #100;
+ power2 <= 1'b1;
+ #100;
+ power3 <= 1'b1;
+ #100;
+ power4 <= 1'b1;
+ end
+
+ //always @(mprj_io) begin
+ // #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+ //end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire USER_VDD3V3 = power3;
+ wire USER_VDD1V8 = power4;
+ wire VSS = 1'b0;
+
+ caravel u_top (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (USER_VDD3V3),
+ .vdda2 (USER_VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (USER_VDD1V8),
+ .vccd2 (USER_VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+/*** No Caravel SPI needed **************
+ spiflash #(
+ .FILENAME("uart_master.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+************************/
+
+
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+ end
+`endif
+
+
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = mprj_io[7];
+assign mprj_io[6] = uart_rxd ;
+
+uart_agent tb_master_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
+
+
+`include "caravel_task.sv"
+`include "uart_master_tasks.sv"
+
+endmodule
+
+`default_nettype wire
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 2865bda..159635e 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -173,7 +173,7 @@
(strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[27:24] + 2 :
(strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4;
-assign skew_config[31:28] = 4'b0;
+assign skew_config[31:28] = CLK_SKEW1_RESET_VAL[31:28];
//----------------------------------------------------------
reg [3:0] cpu_clk_cfg,wbs_clk_cfg;
@@ -219,6 +219,24 @@
fork
begin
$display("##########################################################");
+ $display("Step-0,Monitor: Checking the chip signature :");
+ $display("###################################################");
+ test_id = 0;
+ test_step = 0;
+ // Remove Wb/PinMux Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,CHIP_SIGNATURE);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,CHIP_RELEASE_DATE);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,CHIP_REVISION);
+ if(test_fail == 1) begin
+ $display("ERROR: Step-0,Monitor: Checking the chip signature - FAILED");
+ end else begin
+ $display("STATUS: Step-0,Monitor: Checking the chip signature - PASSED");
+ $display("##########################################################");
+ end
+
+ $display("##########################################################");
$display("Step-1, Checking the Strap Loading");
test_id = 1;
for(i = 0; i < 16; i = i+1) begin
@@ -510,25 +528,6 @@
$display("##########################################################");
end
- $display("##########################################################");
- $display("Step-11,Monitor: Checking the chip signature :");
- $display("###################################################");
- test_id = 11;
- test_step = 14;
- // Remove Wb/PinMux Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
-
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,CHIP_SIGNATURE);
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,CHIP_RELEASE_DATE);
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,CHIP_REVISION);
- if(test_fail == 1) begin
- $display("ERROR: Step-11,Monitor: Checking the chip signature - FAILED");
- end else begin
- $display("STATUS: Step-11,Monitor: Checking the chip signature - PASSED");
-
- $display("##########################################################");
-
- end
end
begin
repeat (500000) @(posedge clock);
@@ -562,7 +561,7 @@
// UART Agent integration
// --------------------------
-assign uart_txd = io_out[7];
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7] : 1'b0;
//assign io_in[6] = uart_rxd ; // Assigned at top-level
uart_agent tb_master_uart(
@@ -668,7 +667,7 @@
input real exp_period;
begin
`ifdef GL
- force clock_mon = u_top.u_wb_host._09635_.Q;
+ force clock_mon = u_top.u_wb_host._10379_.Q;
`else
force clock_mon = u_top.u_wb_host.u_uart2wb.u_core.line_clk_16x;
`endif
@@ -678,7 +677,7 @@
endtask
-wire dbg_clk_mon = io_out[37];
+wire dbg_clk_mon = (io_oeb[37] == 1'b0) ? io_out[37]: 1'b0;
//assign dbg_clk_ref = (cfg_mon_sel == 4'b000) ? user_clock1 :
// (cfg_mon_sel == 4'b001) ? user_clock2 :
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
index b8909fa..c287d2a 100644
--- a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
+++ b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
@@ -155,22 +155,22 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name("user_cache_bypass.hex"),
diff --git a/verilog/dv/user_gpio/user_gpio_tb.v b/verilog/dv/user_gpio/user_gpio_tb.v
index 1e313c4..317e45f 100644
--- a/verilog/dv/user_gpio/user_gpio_tb.v
+++ b/verilog/dv/user_gpio/user_gpio_tb.v
@@ -99,11 +99,11 @@
reg [7:0] port_a_out;
wire [7:0] port_a_in = { 3'b0,
- io_out[4],
- io_out[3],
- io_out[2],
- io_out[1],
- io_out[0]
+ (io_oeb[4] == 1'b0) ? io_out[4]: 1'b0,
+ (io_oeb[3] == 1'b0) ? io_out[3]: 1'b0,
+ (io_oeb[2] == 1'b0) ? io_out[2]: 1'b0,
+ (io_oeb[1] == 1'b0) ? io_out[1]: 1'b0,
+ (io_oeb[0] == 1'b0) ? io_out[0]: 1'b0
};
@@ -112,7 +112,7 @@
io_in[2],
io_in[1],
io_in[0]
- } = (test_start) ? port_a_out[4:0]: 5'hZ;
+ } = (test_start) ? ((&io_oeb[4:0]) ? port_a_out[4:0]: 5'hZ) : 5'hZ;
/************* Port-B Mapping **********************************
@@ -127,14 +127,14 @@
* ********************************************************/
reg [7:0] port_b_out;
- wire [7:0] port_b_in = { io_out[12],
- io_out[11],
- io_out[21],
- io_out[20],
- io_out[19],
- io_out[18],
- io_out[17],
- io_out[16]
+ wire [7:0] port_b_in = { (io_oeb[12]== 1'b0)? io_out[12] : 1'b0,
+ (io_oeb[11]== 1'b0)? io_out[11] : 1'b0,
+ (io_oeb[21]== 1'b0)? io_out[21] : 1'b0,
+ (io_oeb[20]== 1'b0)? io_out[20] : 1'b0,
+ (io_oeb[19]== 1'b0)? io_out[19] : 1'b0,
+ (io_oeb[18]== 1'b0)? io_out[18] : 1'b0,
+ (io_oeb[17]== 1'b0)? io_out[17] : 1'b0,
+ (io_oeb[16]== 1'b0)? io_out[16] : 1'b0
};
assign { io_in[12],
@@ -159,13 +159,13 @@
reg [7:0] port_c_out;
wire [7:0] port_c_in = { 1'b0,
- io_out[5],
- io_out[27],
- io_out[26],
- io_out[25],
- io_out[24],
- io_out[23],
- io_out[22]
+ (io_oeb[5] == 1'b0) ? io_out[5] : 1'b0,
+ (io_oeb[27] == 1'b0) ? io_out[27] : 1'b0,
+ (io_oeb[26] == 1'b0) ? io_out[26] : 1'b0,
+ (io_oeb[25] == 1'b0) ? io_out[25] : 1'b0,
+ (io_oeb[24] == 1'b0) ? io_out[24] : 1'b0,
+ (io_oeb[23] == 1'b0) ? io_out[23] : 1'b0,
+ (io_oeb[22] == 1'b0) ? io_out[22] : 1'b0
};
assign { io_in[5],
io_in[27],
@@ -189,14 +189,14 @@
* ********************************************************/
reg [7:0] port_d_out;
- wire [7:0] port_d_in = { io_out[15],
- io_out[14],
- io_out[13],
- io_out[10],
- io_out[9],
- io_out[8],
- io_out[7],
- io_out[6]
+ wire [7:0] port_d_in = { (io_oeb[15]== 1'b0) ? io_out[15] : 1'b0,
+ (io_oeb[14]== 1'b0) ? io_out[14] : 1'b0,
+ (io_oeb[13]== 1'b0) ? io_out[13] : 1'b0,
+ (io_oeb[10]== 1'b0) ? io_out[10] : 1'b0,
+ (io_oeb[9] == 1'b0) ? io_out[9] : 1'b0,
+ (io_oeb[8] == 1'b0) ? io_out[8] : 1'b0,
+ (io_oeb[7] == 1'b0) ? io_out[7] : 1'b0,
+ (io_oeb[6] == 1'b0) ? io_out[6] : 1'b0
};
assign { io_in[15],
diff --git a/verilog/dv/user_ir_rx/Makefile b/verilog/dv/user_ir_rx/Makefile
new file mode 100644
index 0000000..32755e0
--- /dev/null
+++ b/verilog/dv/user_ir_rx/Makefile
@@ -0,0 +1,84 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_ir_rx
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_ir_rx/user_ir_rx_tb.v b/verilog/dv/user_ir_rx/user_ir_rx_tb.v
new file mode 100644
index 0000000..d04053f
--- /dev/null
+++ b/verilog/dv/user_ir_rx/user_ir_rx_tb.v
@@ -0,0 +1,160 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+/********************************************************************
+ Standalone IR Receiver validation Test bench
+
+ Author(s):
+ - Dinesh Annayya, dinesh.annayya@gmail.com
+ Revision :
+ - 0.1 - 16th Feb 2021, Dinesh A
+*********************************************************************/
+
+`default_nettype wire
+
+`timescale 1 ns/1 ps
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+`include "user_params.svh"
+`include "bfm_ir.v"
+
+`define TB_TOP user_ir_rx_tb
+
+module `TB_TOP;
+parameter real CLK1_PERIOD = 25; // 40Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
+
+integer i;
+reg [7:0] cmd_addr;
+reg [7:0] cmd_data;
+
+
+`include "user_tasks.sv"
+
+
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(1, `TB_TOP);
+ $dumpvars(1, `TB_TOP.u_top);
+ //$dumpvars(0, `TB_TOP.u_top.u_pll);
+ $dumpvars(0, `TB_TOP.u_top.u_wb_host);
+ //$dumpvars(0, `TB_TOP.u_top.u_intercon);
+ //$dumpvars(1, `TB_TOP.u_top.u_intercon);
+ $dumpvars(0, `TB_TOP.u_top.u_pinmux);
+ $dumpvars(0, `TB_TOP.u_top.u_peri);
+ $dumpvars(0, `TB_TOP.u_bfm_ir);
+ end
+ `endif
+
+initial
+begin
+
+ init();
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Basic Test Started");
+
+ repeat (2) @(posedge clock);
+
+ test_fail=0;
+ // Normal tick period: 562.5µs = 562500ns
+ //Protocol tick period divided by 10 for simulation speed-up, 10x slow Tick Period = 56250ns
+ //Protocol tick period divided by 100 for simulation speed-up, 100x slow Tick Period = 5625ns
+
+ u_bfm_ir.init(0, 5625); //Protocol tick period divided by 100 for simulation speed-up
+
+ // Configuration of IR receiver
+ // Typical Oversampling is 8 time of Tick period = 562500/8 = 70312.5ns
+
+ // Protocol tick period divided by 10 for simulation speed-up
+ // with 10x slow speed up = 56250/8= 7031.25ns
+ // With 25ns clock period , Tick = (Clock Period * Divider) / Multiplier
+ // Tick = 25ns * 0x6DDD / 0x64 = 25ns * 28125 / 100 = 7031.25ns
+
+ // Protocol tick period divided by 100 for simulation speed-up
+ // with 100x slow speed up = 5625/8= 703.125ns
+ // With 25ns clock period , Tick = (Clock Period * Divider) / Multiplier
+ // Tick = 25ns * 0x6DDD / 0x3E8 = 25ns * 28125 / 1000 = 703.125ns
+
+ wb_user_core_write(`ADDR_SPACE_IR+`IR_CFG_MULTIPLIER,32'h000003E8);
+ wb_user_core_write(`ADDR_SPACE_IR+`IR_CFG_DIVIDER,32'h00006DDD);
+ wb_user_core_write(`ADDR_SPACE_IR+`IR_CFG_CMD,32'hA5000000);
+
+
+ repeat (100) @(posedge clock);
+ fork
+ begin
+ for(i =0; i < 2; i = i+1) begin
+ cmd_addr = $random%256;
+ cmd_data = $random%256;
+ u_bfm_ir.send_nec(cmd_addr, cmd_data);
+ read_data = 0;
+ while(read_data[3:0] == 'h0) begin
+ wb_user_core_read(`ADDR_SPACE_IR+`IR_CFG_CMD,read_data);
+ end
+ wb_user_core_read(`ADDR_SPACE_IR+`IR_CFG_RX_DATA,read_data);
+ if(read_data[15:8] != cmd_addr && read_data[7:0] != cmd_data)
+ begin
+ $display("ERROR : Exp: [%x] -> [%x] Rxd [%x] -> [%x]",cmd_addr,cmd_data,read_data[15:8],read_data[7:0]);
+ test_fail = 1;
+ end
+ end
+ end
+ begin
+ repeat (1000000) @(posedge clock);
+ test_fail = 1;
+ end
+ join_any
+ disable fork; //disable pending fork activity
+
+ repeat (100) @(posedge clock);
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Passed");
+ `else
+ $display("Monitor: %m (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Failed");
+ `else
+ $display("Monitor: %m (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ #100
+ $finish;
+end
+
+wire ir_rx;
+
+assign io_in[12] = (io_oeb[12] == 1'b1) ? ir_rx : 1'b0;
+
+ bfm_ir u_bfm_ir(
+ .ir_signal(ir_rx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/user_ir_tx/Makefile b/verilog/dv/user_ir_tx/Makefile
new file mode 100644
index 0000000..0406adc
--- /dev/null
+++ b/verilog/dv/user_ir_tx/Makefile
@@ -0,0 +1,84 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_ir_tx
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_ir_tx/user_ir_tx_tb.v b/verilog/dv/user_ir_tx/user_ir_tx_tb.v
new file mode 100644
index 0000000..ce0c5a5
--- /dev/null
+++ b/verilog/dv/user_ir_tx/user_ir_tx_tb.v
@@ -0,0 +1,166 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+/********************************************************************
+ Standalone IR Receiver validation Test bench
+
+ Test case: IR Transmitter io_out[15] is loop back to IO Reciver io_in[12]
+
+ Author(s):
+ - Dinesh Annayya, dinesh.annayya@gmail.com
+ Revision :
+ - 0.1 - 13 Dec 2022, Dinesh A
+*********************************************************************/
+
+`default_nettype wire
+
+`timescale 1 ns/1 ps
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "user_params.svh"
+
+`define TB_TOP user_ir_tx_tb
+
+module `TB_TOP;
+parameter real CLK1_PERIOD = 25; // 40Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
+
+integer i;
+reg [7:0] cmd_addr;
+reg [7:0] cmd_data;
+
+
+`include "user_tasks.sv"
+
+
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(1, `TB_TOP);
+ $dumpvars(1, `TB_TOP.u_top);
+ //$dumpvars(0, `TB_TOP.u_top.u_pll);
+ $dumpvars(0, `TB_TOP.u_top.u_wb_host);
+ //$dumpvars(0, `TB_TOP.u_top.u_intercon);
+ //$dumpvars(1, `TB_TOP.u_top.u_intercon);
+ $dumpvars(0, `TB_TOP.u_top.u_pinmux);
+ $dumpvars(0, `TB_TOP.u_top.u_peri);
+ end
+ `endif
+
+initial
+begin
+
+ init();
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Basic Test Started");
+
+ repeat (2) @(posedge clock);
+
+ test_fail=0;
+
+ // Normal tick period: 562.5µs = 562500ns
+ //Protocol tick period divided by 10 for simulation speed-up, 10x slow Tick Period = 56250ns
+ //Protocol tick period divided by 100 for simulation speed-up, 100x slow Tick Period = 5625ns
+
+
+ // Configuration of IR receiver
+ // Typical Oversampling is 8 time of Tick period = 562500/8 = 70312.5ns
+
+ // Protocol tick period divided by 10 for simulation speed-up
+ // with 10x slow speed up = 56250/8= 7031.25ns
+ // With 25ns clock period , Tick = (Clock Period * Divider) / Multiplier
+ // Tick = 25ns * 0x6DDD / 0x64 = 25ns * 28125 / 100 = 7031.25ns
+
+ // Protocol tick period divided by 100 for simulation speed-up
+ // with 100x slow speed up = 5625/8= 703.125ns
+ // With 25ns clock period , Tick = (Clock Period * Divider) / Multiplier
+ // Tick = 25ns * 0x6DDD / 0x3E8 = 25ns * 28125 / 1000 = 703.125ns
+
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100);
+ wb_user_core_write(`ADDR_SPACE_IR+`IR_CFG_MULTIPLIER,32'h000003E8);
+ wb_user_core_write(`ADDR_SPACE_IR+`IR_CFG_DIVIDER,32'h00006DDD);
+ wb_user_core_write(`ADDR_SPACE_IR+`IR_CFG_CMD,32'hE4100000); // Enable Both Tx/RX Enable
+
+ // Enable GPIO IR TX at bit [15]
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h2_0000);
+
+ repeat (100) @(posedge clock);
+ fork
+ begin
+ for(i =0; i < 2; i = i+1) begin
+ // Setp-1: Check the TX FIFO is not full
+ read_data[7:4] = 4'h8;
+ while(read_data[7:4] == 'h8) begin
+ wb_user_core_read(`ADDR_SPACE_IR+`IR_CFG_CMD,read_data);
+ end
+ cmd_addr = $random%256;
+ cmd_data = $random%256;
+ wb_user_core_write(`ADDR_SPACE_IR+`IR_CFG_TX_DATA,{16'h0,cmd_addr[7:0],cmd_data[7:0]});
+
+ // Setp-2: Check the RX FIFO is not empty
+ read_data = 0;
+ while(read_data[3:0] == 'h0) begin
+ wb_user_core_read(`ADDR_SPACE_IR+`IR_CFG_CMD,read_data);
+ end
+ wb_user_core_read(`ADDR_SPACE_IR+`IR_CFG_RX_DATA,read_data);
+ if(read_data[15:8] != cmd_addr && read_data[7:0] != cmd_data)
+ begin
+ $display("ERROR : Exp: [%x] -> [%x] Rxd [%x] -> [%x]",cmd_addr,cmd_data,read_data[15:8],read_data[7:0]);
+ test_fail = 1;
+ end
+ end
+ end
+ begin
+ repeat (1000000) @(posedge clock);
+ test_fail = 1;
+ end
+ join_any
+ disable fork; //disable pending fork activity
+
+ repeat (100) @(posedge clock);
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Passed");
+ `else
+ $display("Monitor: %m (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Failed");
+ `else
+ $display("Monitor: %m (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ #100
+ $finish;
+end
+
+// Look back the IR Tx from Port [15] to PORT[12]
+wire ir_tx = (io_oeb[15] == 1'b0) ? io_out[15] : 1'b0;;
+assign io_in[12] = (io_oeb[12] == 1'b1) ? ir_tx : 1'b0;
+
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v
index 3c425ce..a5297b0 100644
--- a/verilog/dv/user_pwm/user_pwm_tb.v
+++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -765,12 +765,12 @@
$finish;
end
-wire [5:0] pwm_wfm = {io_out[19],
- io_out[18],
- io_out[17],
- io_out[14],
- io_out[13],
- io_out[9]};
+wire [5:0] pwm_wfm = {(io_oeb[19] == 1'b0) ? io_out[19]: 1'b0 ,
+ (io_oeb[18] == 1'b0) ? io_out[18]: 1'b0 ,
+ (io_oeb[17] == 1'b0) ? io_out[17]: 1'b0 ,
+ (io_oeb[14] == 1'b0) ? io_out[14]: 1'b0 ,
+ (io_oeb[13] == 1'b0) ? io_out[13]: 1'b0 ,
+ (io_oeb[9] == 1'b0) ? io_out[9] : 1'b0 };
wire pwm0 = pwm_wfm[0];
wire pwm1 = pwm_wfm[1];
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v
index 9801bdd..66369a2 100644
--- a/verilog/dv/user_qspi/user_qspi_tb.v
+++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -1141,22 +1141,22 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quad flash
@@ -1176,7 +1176,7 @@
);
- wire spiram_csb = io_out[31];
+ wire spiram_csb = (io_oeb[31]== 1'b0) ? io_out[31] : 1'b0;
is62wvs1288 #(.mem_file_name("flash1.hex"))
u_sfram (
diff --git a/verilog/dv/user_random/Makefile b/verilog/dv/user_random/Makefile
new file mode 100644
index 0000000..f96b0fe
--- /dev/null
+++ b/verilog/dv/user_random/Makefile
@@ -0,0 +1,84 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_random
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_random/user_random_tb.v b/verilog/dv/user_random/user_random_tb.v
new file mode 100644
index 0000000..665526a
--- /dev/null
+++ b/verilog/dv/user_random/user_random_tb.v
@@ -0,0 +1,126 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+/********************************************************************
+ Standalone Random Generator validation Test bench
+PseudoRandom generator Test:
+ - Read 32 randoms values
+ - Check that each value is non-equal to 0x00000000
+ - Check that each value is non-equal to 0xFFFFFFFF
+ - Check that each value is non-equal to the previous value
+
+ Author(s):
+ - Dinesh Annayya, dinesh.annayya@gmail.com
+ Revision :
+ - 0.1 - 16th Feb 2021, Dinesh A
+*********************************************************************/
+
+`default_nettype wire
+
+`timescale 1 ns/1 ps
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+`include "user_params.svh"
+
+`define TB_TOP user_random_tb
+
+module `TB_TOP;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
+
+integer i;
+reg [31:0] pre_random;
+
+`include "user_tasks.sv"
+
+
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(1, `TB_TOP);
+ $dumpvars(1, `TB_TOP.u_top);
+ //$dumpvars(0, `TB_TOP.u_top.u_pll);
+ $dumpvars(0, `TB_TOP.u_top.u_wb_host);
+ //$dumpvars(0, `TB_TOP.u_top.u_intercon);
+ //$dumpvars(1, `TB_TOP.u_top.u_intercon);
+ $dumpvars(0, `TB_TOP.u_top.u_pinmux);
+ $dumpvars(0, `TB_TOP.u_top.u_rp_south);
+ end
+ `endif
+
+initial
+begin
+
+ init();
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Basic Test Started");
+
+ repeat (2) @(posedge clock);
+
+ test_fail=0;
+ pre_random = 0;
+ fork
+ begin
+ for(i =0; i < 100; i = i+1) begin
+ wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_RANDOM_NO,read_data);
+ if(read_data == 32'h0) begin
+ test_fail = 1;
+ $display("ERROR: RANDOM Number Is Zero");
+ end else if(read_data == 32'hFFFF_FFFF) begin
+ test_fail = 1;
+ $display("ERROR: RANDOM Number Is All One");
+ end else if(read_data == pre_random) begin
+ test_fail = 1;
+ $display("ERROR: RANDOM Number is same as previous one");
+ end
+ pre_random = read_data;
+ end
+ end
+ begin
+ repeat (50000) @(posedge clock);
+ test_fail = 1;
+ end
+ join_any
+ disable fork; //disable pending fork activity
+
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Passed");
+ `else
+ $display("Monitor: %m (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Failed");
+ `else
+ $display("Monitor: %m (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ #100
+ $finish;
+end
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 0901b82..5a594c2 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -72,7 +72,7 @@
`default_nettype wire
-`timescale 1 ns / 1 ns
+`timescale 1 ns / 10 ps
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
@@ -92,7 +92,10 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(3, `TB_TOP);
+ $dumpvars(1, `TB_TOP);
+ $dumpvars(1, `TB_TOP.u_top.u_wb_host);
+ $dumpvars(1, `TB_TOP.u_top.u_pinmux);
+ $dumpvars(1, `TB_TOP.u_top);
end
`endif
diff --git a/verilog/dv/user_rtc/Makefile b/verilog/dv/user_rtc/Makefile
new file mode 100755
index 0000000..f3485a3
--- /dev/null
+++ b/verilog/dv/user_rtc/Makefile
@@ -0,0 +1,85 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_rtc
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ iverilog-vpi pli_rtc.c
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp -M. -m pli_rtc $<
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.vpi *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_rtc/pli_rtc.c b/verilog/dv/user_rtc/pli_rtc.c
new file mode 100644
index 0000000..461e40d
--- /dev/null
+++ b/verilog/dv/user_rtc/pli_rtc.c
@@ -0,0 +1,295 @@
+#include <stdlib.h> /* ANSI C standard library */
+#include <stdio.h> /* ANSI C standard input/output library */
+#include <time.h>
+#include <stdarg.h> /* ANSI C standard arguments library */
+#include "vpi_user.h" /* IEEE 1364 PLI VPI routine library */
+
+#define CMD_RTC_INIT 0
+#define CMD_RTC_NEXT_SECOND 1
+#define CMD_RTC_NEXT_DATE 2
+
+/* prototypes of PLI application routine names */
+PLI_INT32 PLIbook_RtcSizetf(PLI_BYTE8 *user_data);
+PLI_INT32 PLIbook_RtcCalltf(PLI_BYTE8 *user_data);
+PLI_INT32 PLIbook_RtcCompiletf(PLI_BYTE8 *user_data);
+PLI_INT32 PLIbook_RtcStartOfSim(s_cb_data *callback_data);
+
+ /* tm structure */
+ /* struct tm {
+ int tm_sec; // seconds, range 0 to 59
+ int tm_min; // minutes, range 0 to 59
+ int tm_hour; // hours, range 0 to 23
+ int tm_mday; // day of the month, range 1 to 31
+ int tm_mon; // month, range 0 to 11
+ int tm_year; // The number of years since 1900
+ int tm_wday; // day of the week, range 0 to 6
+ int tm_yday; // day in the year, range 0 to 365
+ int tm_isdst; // daylight saving time
+ }; */
+struct tm tm = {0};
+
+/*******************************************
+* Sizetf application
+* *****************************************/
+PLI_INT32 PLIbook_RtcSizetf(PLI_BYTE8 *user_data)
+{
+ return(32); /* $rtc returns 32-bit values */
+}
+
+/*********************************************
+* compiletf application to verify valid systf args.
+* *************************************************/
+PLI_INT32 PLIbook_RtcCompiletf(PLI_BYTE8 *user_data)
+{
+ s_vpi_value value_s;
+ vpiHandle systf_handle, arg_itr, arg_handle;
+ PLI_INT32 tfarg_type;
+ PLI_INT32 cmd;
+
+ int err_flag = 0;
+ do { /* group all tests, so can break out of group on error */
+ systf_handle = vpi_handle(vpiSysTfCall, NULL);
+ arg_itr = vpi_iterate(vpiArgument, systf_handle);
+ if (arg_itr == NULL) {
+ vpi_printf("ERROR: $c_rtc requires 7 arguments; has none\n");
+ err_flag = 1;
+ break;
+ }
+ arg_handle = vpi_scan(arg_itr);
+ tfarg_type = vpi_get(vpiType, arg_handle);
+ if ( (tfarg_type != vpiReg) &&
+ (tfarg_type != vpiIntegerVar) &&
+ (tfarg_type != vpiConstant) ) {
+ vpi_printf("ERROR: $c_rtc arg1 must be number, variable or net\n");
+ err_flag = 1;
+ break;
+ }
+ value_s.format = vpiIntVal;
+ vpi_get_value(arg_handle, &value_s);
+ cmd = value_s.value.integer;
+
+ // RTC Init has 7 Parameter
+ if(cmd == CMD_RTC_INIT) {
+ arg_handle = vpi_scan(arg_itr);
+ tfarg_type = vpi_get(vpiType, arg_handle);
+ if ( (tfarg_type != vpiReg) &&
+ (tfarg_type != vpiIntegerVar) &&
+ (tfarg_type != vpiConstant) ) {
+ vpi_printf("ERROR: $c_rtc arg2 must be number, variable or net\n");
+ err_flag = 1;
+ break;
+ }
+ arg_handle = vpi_scan(arg_itr);
+ tfarg_type = vpi_get(vpiType, arg_handle);
+ if ( (tfarg_type != vpiReg) &&
+ (tfarg_type != vpiIntegerVar) &&
+ (tfarg_type != vpiConstant) ) {
+ vpi_printf("ERROR: $c_rtc arg3 must be number, variable or net\n");
+ err_flag = 1;
+ break;
+ }
+ arg_handle = vpi_scan(arg_itr);
+ tfarg_type = vpi_get(vpiType, arg_handle);
+ if ( (tfarg_type != vpiReg) &&
+ (tfarg_type != vpiIntegerVar) &&
+ (tfarg_type != vpiConstant) ) {
+ vpi_printf("ERROR: $c_rtc arg4 must be number, variable or net\n");
+ err_flag = 1;
+ break;
+ }
+ arg_handle = vpi_scan(arg_itr);
+ tfarg_type = vpi_get(vpiType, arg_handle);
+ if ( (tfarg_type != vpiReg) &&
+ (tfarg_type != vpiIntegerVar) &&
+ (tfarg_type != vpiConstant) ) {
+ vpi_printf("ERROR: $c_rtc arg5 must be number, variable or net\n");
+ err_flag = 1;
+ break;
+ }
+ arg_handle = vpi_scan(arg_itr);
+ tfarg_type = vpi_get(vpiType, arg_handle);
+ if ( (tfarg_type != vpiReg) &&
+ (tfarg_type != vpiIntegerVar) &&
+ (tfarg_type != vpiConstant) ) {
+ vpi_printf("ERROR: $c_rtc arg6 must be number, variable or net\n");
+ err_flag = 1;
+ break;
+ }
+ arg_handle = vpi_scan(arg_itr);
+ tfarg_type = vpi_get(vpiType, arg_handle);
+ if ( (tfarg_type != vpiReg) &&
+ (tfarg_type != vpiIntegerVar) &&
+ (tfarg_type != vpiConstant) ) {
+ vpi_printf("ERROR: $c_rtc arg7 must be number, variable or net\n");
+ err_flag = 1;
+ break;
+ }
+
+ arg_handle = vpi_scan(arg_itr);
+ if (arg_handle != NULL) {
+ vpi_printf("ERROR: $c_rtc requires 7 arguments; has too many\n");
+ vpi_free_object(arg_itr);
+ err_flag = 1;
+ break;
+ }
+ } else { // CMD_RTC_NEXT_SECOND & CMD_RTC_NEXT_DATE has only 1 arguments
+
+ arg_handle = vpi_scan(arg_itr);
+ if (arg_handle != NULL) {
+ vpi_printf("ERROR: $c_rtc requires 1 arguments; has too many\n");
+ vpi_free_object(arg_itr);
+ err_flag = 1;
+ break;
+ }
+ }
+ } while (0 == 1); /* end of test group; only executed once */
+ if (err_flag) {
+ vpi_control(vpiFinish, 1); /* abort simulation */
+ }
+ return(0);
+}
+
+/******************************************************************
+* calltf to calculate floating point addr
+* ******************************************************************/
+#include <stdio.h>
+#include <time.h>
+#include <stdlib.h>
+
+PLI_INT32 PLIbook_RtcCalltf(PLI_BYTE8 *user_data)
+{
+ s_vpi_value value_s;
+ vpiHandle systf_handle, arg_itr, arg_handle;
+ PLI_INT32 cmd,year, month, date, hour,minute,second;
+ float result;
+ systf_handle = vpi_handle(vpiSysTfCall, NULL);
+ arg_itr = vpi_iterate(vpiArgument, systf_handle);
+ if (arg_itr == NULL) {
+ vpi_printf("ERROR: $c_rtc failed to obtain systf arg handles\n");
+ return(0);
+ }
+ /* read cmd from systf arg 1 (compiletf has already verified) */
+ arg_handle = vpi_scan(arg_itr);
+ value_s.format = vpiIntVal;
+ vpi_get_value(arg_handle, &value_s);
+ cmd = value_s.value.integer;
+
+
+ if(cmd == CMD_RTC_INIT) {
+ /* read input1 from systf arg 6 (compiletf has already verified) */
+ arg_handle = vpi_scan(arg_itr);
+ vpi_get_value(arg_handle, &value_s);
+ year = value_s.value.integer;
+
+ /* read input2 from systf arg 6 (compiletf has already verified) */
+ arg_handle = vpi_scan(arg_itr);
+ vpi_get_value(arg_handle, &value_s);
+ month = value_s.value.integer;
+
+ /* read input2 from systf arg 6 (compiletf has already verified) */
+ arg_handle = vpi_scan(arg_itr);
+ vpi_get_value(arg_handle, &value_s);
+ date = value_s.value.integer;
+
+ /* read input3 from systf arg 6 (compiletf has already verified) */
+ arg_handle = vpi_scan(arg_itr);
+ vpi_get_value(arg_handle, &value_s);
+ hour = value_s.value.integer;
+
+ /* read input4 from systf arg 6 (compiletf has already verified) */
+ arg_handle = vpi_scan(arg_itr);
+ vpi_get_value(arg_handle, &value_s);
+ minute = value_s.value.integer;
+
+ /* read input5 from systf arg 6 (compiletf has already verified) */
+ arg_handle = vpi_scan(arg_itr);
+ vpi_get_value(arg_handle, &value_s);
+ second = value_s.value.integer;
+
+ // initialize the Structure
+ tm.tm_year = year-1900;
+ tm.tm_mon = month-1; /* C Month start from 0 to 11 and RTL 1 to 12 */
+ tm.tm_mday = date;
+ tm.tm_hour = hour;
+ tm.tm_min = minute;
+ tm.tm_sec = second;
+ }
+
+ // vpi_printf("c_func: year: %d; month: %d; day: %d;hour: %d; minute: %d; second: %d;week day: %d; year day: %d\n",
+ // tm.tm_year + 1900, tm.tm_mon, tm.tm_mday,
+ // tm.tm_hour, tm.tm_min, tm.tm_sec,
+ // tm.tm_wday, tm.tm_yday);
+
+ if(cmd == CMD_RTC_NEXT_SECOND)
+ tm.tm_sec = tm.tm_sec + 1;
+ else if(cmd == CMD_RTC_NEXT_DATE)
+ tm.tm_mday = tm.tm_mday + 1;
+ mktime(&tm);
+
+ //vpi_printf("c_func: year: %d; month: %d; day: %d;hour: %d; minute: %d; second: %d;week day: %d; year day: %d\n",
+ // tm.tm_year + 1900, tm.tm_mon, tm.tm_mday,
+ // tm.tm_hour, tm.tm_min, tm.tm_sec,
+ // tm.tm_wday, tm.tm_yday);
+
+ char str[80];
+ if(cmd == CMD_RTC_NEXT_SECOND)
+ sprintf(str,"%02d%02d%02d%02d",tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec);
+ else if(cmd == CMD_RTC_NEXT_DATE)
+ sprintf(str,"%04d%02d%02d",tm.tm_year+1900,tm.tm_mon+1,tm.tm_mday);
+
+ vpi_printf("c_func: year: %d; month: %d; day: %d;hour: %d; minute: %d; second: %d;week day: %d; year day: %d\n",
+ tm.tm_year + 1900, tm.tm_mon+1, tm.tm_mday,
+ tm.tm_hour, tm.tm_min, tm.tm_sec,
+ tm.tm_wday, tm.tm_yday);
+
+ ///* write result to simulation as return value $fpu_add */
+ int c = (int)strtol(str, NULL, 16);
+
+ value_s.value.integer = (PLI_INT32)c;
+ vpi_put_value(systf_handle, &value_s, NULL, vpiNoDelay);
+ return(0);
+}
+
+
+/**
+* Start-of-simulation application
+****/
+PLI_INT32 PLIbook_RtcStartOfSim(s_cb_data *callback_data)
+{
+ vpi_printf("\n$c_rtc PLI application is being used.\n\n");
+ return(0);
+}
+
+/**********************************************************
+ $fpu_add Registration Data
+(add this function name to the vlog_startup_routines array)
+***********************************************************/
+void PLIbook_fpu_add_register()
+{
+ s_vpi_systf_data tf_data;
+ s_cb_data cb_data_s;
+ vpiHandle callback_handle;
+
+ tf_data.type = vpiSysFunc;
+ tf_data.sysfunctype = vpiSysFuncSized;
+ tf_data.tfname = "$c_rtc";
+ tf_data.calltf = PLIbook_RtcCalltf;
+ tf_data.compiletf = PLIbook_RtcCompiletf;
+ tf_data.sizetf = PLIbook_RtcSizetf;
+ tf_data.user_data = NULL;
+ vpi_register_systf(&tf_data);
+ cb_data_s.reason = cbStartOfSimulation;
+ cb_data_s.cb_rtn = PLIbook_RtcStartOfSim;
+ cb_data_s.obj = NULL;
+ cb_data_s.time = NULL;
+ cb_data_s.value = NULL;
+ cb_data_s.user_data = NULL;
+ callback_handle = vpi_register_cb(&cb_data_s);
+ vpi_free_object(callback_handle); /* don’t need callback handle */
+}
+
+void (*vlog_startup_routines[])() = {
+ PLIbook_fpu_add_register,
+ 0
+};
+
diff --git a/verilog/dv/user_rtc/user_rtc_tb.v b/verilog/dv/user_rtc/user_rtc_tb.v
new file mode 100644
index 0000000..d53aefe
--- /dev/null
+++ b/verilog/dv/user_rtc/user_rtc_tb.v
@@ -0,0 +1,317 @@
+/*********************************************************************************
+ SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+ SPDX-License-Identifier: Apache-2.0
+ SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
+
+***********************************************************************************/
+/**********************************************************************************
+
+ RTC Test Bench
+
+
+ Author(s):
+ - Dinesh Annayya, dinesh.annayya@gmail.com
+
+ Revision :
+ 0.0 - Nov 16, 2022
+ Initial Version
+ 0.1 - Nov 21, 2022
+ A.Sys-clk and RTC clock domain are seperated.
+ B.Register are moved to seperate module
+
+************************************************************************************/
+/************************************************************************************
+ Copyright (C) 2000-2002
+ Dinesh Annayya <dinesh.annayya@gmail.com>
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
+ OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+
+************************************************************************************/
+
+`timescale 1 ns / 1 ps
+
+
+
+`define CMD_C_INIT 4'h0 // Initialize the C PLI Timer
+`define CMD_C_NEXT_TIME 4'h1 // Get Next Second Value
+`define CMD_C_NEXT_DATE 4'h2 // Het Next Date value
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+
+`define TB_TOP user_rtc_tb
+
+module `TB_TOP;
+
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
+
+parameter RTC_PERIOD = 30518; // 32768 Hz
+
+`include "user_tasks.sv"
+
+reg rtc_clk;
+reg rst_n;
+reg [15:0] error_cnt;
+
+//---------------------
+// Register I/F
+wire trig_s = u_top.u_peri.inc_time_s;
+wire trig_d = u_top.u_peri.inc_date_d;
+
+
+// Wishbone Interface
+
+always #(RTC_PERIOD/2) rtc_clk = ~rtc_clk;
+
+assign io_in[11] = rtc_clk;
+
+ initial begin
+ test_fail = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ rtc_clk = 0;
+ error_cnt = 0;
+ end
+
+initial
+ begin
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
+
+ $display("\n\n");
+ $display("*****************************************************");
+ $display("* RTC Test bench ...");
+ $display("*****************************************************");
+ $display("\n");
+
+
+ normal_test;
+ fast_test1;
+ fast_test2;
+
+ repeat(1000) @(posedge clock);
+
+ if(error_cnt > 0) test_fail = 1;
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Passed");
+ `else
+ $display("Monitor: %m (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Failed");
+ `else
+ $display("Monitor: %m (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ repeat(10) @(posedge clock);
+ $finish;
+end
+
+`ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(0, `TB_TOP);
+ end
+`endif
+
+
+
+wire [7:0] rtl_time = {1'b0, u_top.u_peri.u_rtc.time_ts,u_top.u_peri.u_rtc.time_s};
+wire [7:0] rtl_minute = {1'b0, u_top.u_peri.u_rtc.time_tm,u_top.u_peri.u_rtc.time_m};
+wire [7:0] rtl_hour = {1'b0, u_top.u_peri.u_rtc.time_th,u_top.u_peri.u_rtc.time_h};
+wire [7:0] rtl_dow = {5'b0, u_top.u_peri.u_rtc.time_dow};
+
+wire [7:0] rtl_date = {2'b0,u_top.u_peri.u_rtc.date_td,u_top.u_peri.u_rtc.date_d};
+wire [7:0] rtl_month = {2'b0,u_top.u_peri.u_rtc.date_tm,u_top.u_peri.u_rtc.date_m};
+wire [15:0] rtl_year = {u_top.u_peri.u_rtc.date_tc,u_top.u_peri.u_rtc.date_c,u_top.u_peri.u_rtc.date_ty,u_top.u_peri.u_rtc.date_y};
+wire [7:0] rtl_cent = {u_top.u_peri.u_rtc.date_tc,u_top.u_peri.u_rtc.date_c};
+
+//---------------------------
+// Normal Test Without any Over-ride
+task normal_test;
+reg [31:0] exp_time;
+reg [31:0] cfg_time;
+reg [31:0] cfg_date;
+integer i;
+begin
+ //initialize the Timer Structure in C-PLI
+ $c_rtc(`CMD_C_INIT,2022,10,19,0,0,0);
+ init();
+
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_TIME,{8'h01,8'h0,8'h0,8'h0});
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_DATE,{16'h2022,8'h10,8'h19});
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b01});
+
+ for(i=0; i < 10; i = i+1) begin
+ repeat(1) @(negedge trig_s);
+ exp_time = $c_rtc(1);
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b10});
+ wb_user_core_read(`ADDR_SPACE_RTC+`RTC_TIME,cfg_time);
+ wb_user_core_read(`ADDR_SPACE_RTC+`RTC_DATE,cfg_date);
+
+ if(exp_time == {cfg_date[7:0],cfg_time[23:0]}) begin
+ $display("STATUS: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+ exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],cfg_date[7:0],cfg_time[23:16],cfg_time[15:8],cfg_time[7:0]);
+ end else begin
+ error_cnt = error_cnt+1;
+ $display("ERROR: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+ exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],cfg_date[7:0],cfg_time[23:16],cfg_time[15:8],cfg_time[7:0]);
+ repeat(10) @(posedge clock);
+ $finish;
+ end
+ end
+ if(error_cnt > 0)
+ $display("STATUS: Normal Test[Day, Hour,Minute,Second] without Over-ride Failed");
+ else
+ $display("STATUS: Normal Test[Day, Hour, Minute,Second] without Over-ride Passed");
+
+
+end
+endtask
+
+//------------------------------------------------------
+// Fast Time Test With Over-ride fast_sim_time=1
+//------------------------------------------------------
+task fast_test1;
+reg [31:0] exp_time;
+integer i;
+begin
+ //initialize the Timer Structure in C-PLI
+ $c_rtc(`CMD_C_INIT,2022,10,19,0,0,0);
+
+ init();
+
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_TIME,{8'h01,8'h0,8'h0,8'h0});
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_DATE,{16'h2022,8'h10,8'h19});
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b01});
+
+ fork
+ begin
+ //fast_sim_time=1;
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b01,14'h400});
+ end
+ begin
+ for(i=0; i < (65536*10); i = i+1) begin
+ repeat(1) @(negedge trig_s);
+ exp_time = $c_rtc(`CMD_C_NEXT_TIME);
+ if(exp_time == {rtl_date,rtl_hour,rtl_minute,rtl_time}) begin
+ $display("STATUS: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Year:%04x Month: %02x Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+ exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],rtl_year,rtl_month,rtl_date,rtl_hour,rtl_minute,rtl_time);
+ end else begin
+ error_cnt = error_cnt+1;
+ $display("ERROR: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Year:%04x Month: %02x Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+ exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],rtl_year,rtl_month,rtl_date,rtl_hour,rtl_minute,rtl_time);
+ repeat(10) @(posedge clock);
+ $finish;
+ end
+ end
+ end
+ join
+
+ //fast_sim_time=0;
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b00,14'h400});
+
+ if(error_cnt > 0)
+ $display("STATUS: Fast Test1 with (Fast Time) Over-ride Failed");
+ else
+ $display("STATUS: Fast Test1 with (Fast Time) Over-ride Passed");
+end
+endtask
+
+//------------------------------------------------------
+// Fast Time Test With Over-ride fast_sim_date=1
+//------------------------------------------------------
+task fast_test2;
+reg [31:0] exp_date;
+integer i;
+begin
+ //initialize the Timer Structure in C-PLI
+ $c_rtc(`CMD_C_INIT,2022,10,19,0,0,0);
+
+ init();
+
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_TIME,{8'h01,8'h0,8'h0,8'h0});
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_DATE,{16'h2022,8'h10,8'h19});
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b01});
+
+ fork
+ begin
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b10,14'h400});
+ repeat(1) @(posedge clock);
+ end
+ begin
+ for(i=0; i < (65536*10); i = i+1) begin
+ repeat(1) @(negedge trig_d);
+ exp_date = $c_rtc(`CMD_C_NEXT_DATE);
+ if(exp_date == {rtl_year,rtl_month,rtl_date}) begin
+ $display("STATUS: Exp: [Year: %04x Month: %02x Date: %02x] RTL: [Year:%04x Month: %02x Day: %02x]",
+ exp_date[31:16],exp_date[15:8],exp_date[7:0],rtl_year,rtl_month,rtl_date);
+ end else begin
+ error_cnt = error_cnt+1;
+ $display("ERROR: Exp: [Year: %04x Month: %02x Date: %02x] RTL: [Year:%04x Month: %02x Day: %02x]",
+ exp_date[31:16],exp_date[15:8],exp_date[7:0],rtl_year,rtl_month,rtl_date);
+ repeat(10) @(posedge clock);
+ $finish;
+ end
+ end
+ end
+ join
+
+ wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b00,14'h0});
+
+ if(error_cnt > 0)
+ $display("STATUS: Fast Test2 with (Fast Date) Over-ride Failed");
+ else
+ $display("STATUS: Fast Test2 with (Fast Date) Over-ride Passed");
+end
+endtask
+
+
+
+
+
+
+
+endmodule
+
+
diff --git a/verilog/dv/user_sram_exec/user_sram_exec_tb.v b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
index 6e2bcf4..a3c05ad 100644
--- a/verilog/dv/user_sram_exec/user_sram_exec_tb.v
+++ b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
@@ -168,22 +168,22 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
index 1650d50..2977fa7 100644
--- a/verilog/dv/user_sspi/user_sspi_tb.v
+++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -383,15 +383,15 @@
// user core using the gpio pads
// ----------------------------------------------------
wire flash_io1;
- wire flash_clk = io_out[21];
- tri #1 flash_io0 = io_out[20];
- assign io_in[19] = flash_io1;
+ wire flash_clk = (io_oeb[21] == 1'b0) ? io_out[21] : 1'b0;
+ tri #1 flash_io0 = (io_oeb[20] == 1'b0) ? io_out[20] : 1'b0;
+ assign io_in[19] = (io_oeb[19] == 1'b1) ? flash_io1 : 1'b0;
tri #1 flash_io2 = 1'b1;
tri #1 flash_io3 = 1'b1;
- wire spiram_csb0 = io_out[18];
+ wire spiram_csb0 = (io_oeb[18] == 1'b0) ? io_out[18] : 1'b0;
is62wvs1288 #(.mem_file_name("flash0.hex"))
u_sfram_0 (
// Data Inputs/Outputs
@@ -404,7 +404,7 @@
.io3 (flash_io3)
);
- wire spiram_csb1 = io_out[17];
+ wire spiram_csb1 = (io_oeb[17] == 1'b0) ? io_out[17] : 1'b0;
is62wvs1288 #(.mem_file_name("flash1.hex"))
u_sfram_1 (
// Data Inputs/Outputs
@@ -417,7 +417,7 @@
.io3 (flash_io3)
);
- wire spiram_csb2 = io_out[14];
+ wire spiram_csb2 = (io_oeb[14] == 1'b0) ? io_out[14] : 1'b0;
is62wvs1288 #(.mem_file_name("flash2.hex"))
u_sfram_2 (
// Data Inputs/Outputs
@@ -430,7 +430,7 @@
.io3 (flash_io3)
);
- wire spiram_csb3 = io_out[13];
+ wire spiram_csb3 = (io_oeb[13] == 1'b0) ? io_out[13] : 1'b0;
is62wvs1288 #(.mem_file_name("flash3.hex"))
u_sfram_3 (
// Data Inputs/Outputs
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 935aa9e..77f5197 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -246,23 +246,22 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
-
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -288,8 +287,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[7];
-assign io_in[6] = uart_rxd ;
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7] : 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart_rxd : 1'b0;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v
index 2d1c2b2..bbcb183 100644
--- a/verilog/dv/user_uart1/user_uart1_tb.v
+++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -247,23 +247,22 @@
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[28];
- wire flash_csb = io_out[29];
+ wire flash_clk = (io_oeb[28] == 1'b0) ? io_out[28]: 1'b0;
+ wire flash_csb = (io_oeb[29] == 1'b0) ? io_out[29]: 1'b0;
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[33] = flash_io0;
- assign io_in[34] = flash_io1;
- assign io_in[35] = flash_io2;
- assign io_in[36] = flash_io3;
-
+ assign io_in[33] = (io_oeb[33] == 1'b1) ? flash_io0: 1'b0;
+ assign io_in[34] = (io_oeb[34] == 1'b1) ? flash_io1: 1'b0;
+ assign io_in[35] = (io_oeb[35] == 1'b1) ? flash_io2: 1'b0;
+ assign io_in[36] = (io_oeb[36] == 1'b1) ? flash_io3: 1'b0;
// Quard flash
s25fl256s #(.mem_file_name(`TB_HEX),
@@ -289,8 +288,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[10];
-assign io_in[8] = uart_rxd ;
+assign uart_txd = (io_oeb[10] == 1'b0) ? io_out[10]: 1'b0;
+assign io_in[8] = (io_oeb[8] == 1'b1) ? uart_rxd : 1'b0;
uart_agent tb_uart(
.mclk (clock ),
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 57d6802..b6134c0 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -210,8 +210,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[7];
-assign io_in[6] = uart_rxd ;
+assign uart_txd = (io_oeb[7] == 1'b0) ? io_out[7] : 1'b0;
+assign io_in[6] = (io_oeb[6] == 1'b1) ? uart_rxd : 1'b0;
uart_agent tb_master_uart(
.mclk (clock ),
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index aa9d785..45c203c 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index 9693486..4b29c06 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -18,6 +18,13 @@
$(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v
$(USER_PROJECT_VERILOG)/gl/wb_interconnect.v
+
+$(USER_PROJECT_VERILOG)/gl/bus_rep_south.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_north.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_east.v
+$(USER_PROJECT_VERILOG)/gl/bus_rep_west.v
+$(USER_PROJECT_VERILOG)/gl/peri_top.v
+
-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
-v $(USER_PROJECT_VERILOG)/rtl/dac/src/dac_top.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 3010d19..e858396 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -13,6 +13,7 @@
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/semaphore_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/strap_ctrl.sv
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_rst_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pseudorandom.sv
-v $(USER_PROJECT_VERILOG)/rtl/gpio/src/gpio_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/gpio/src/gpio_dglicth.sv
-v $(USER_PROJECT_VERILOG)/rtl/gpio/src/gpio_intr.sv
@@ -145,5 +146,28 @@
-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv
-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv
-
-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_south.sv
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_north.sv
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_east.sv
+-v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_west.sv
+
+-v $(USER_PROJECT_VERILOG)/rtl/peripheral/src/peri_top.sv
+
+$(USER_PROJECT_VERILOG)/rtl/rtc/verilog/rtl/core/rtc_top.sv
+$(USER_PROJECT_VERILOG)/rtl/rtc/verilog/rtl/core/rtc_core.sv
+$(USER_PROJECT_VERILOG)/rtl/rtc/verilog/rtl/core/rtc_reg.sv
+
+-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo_occ.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/prescaler.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/metastability_filter.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_filter.sv
+
+$(USER_PROJECT_VERILOG)/rtl/nec_ir/src/nec_ir_rx.sv
+$(USER_PROJECT_VERILOG)/rtl/nec_ir/src/nec_ir_frame_decoder.sv
+$(USER_PROJECT_VERILOG)/rtl/nec_ir/src/nec_ir_event_catcher.sv
+$(USER_PROJECT_VERILOG)/rtl/nec_ir/src/nec_ir_regs.sv
+$(USER_PROJECT_VERILOG)/rtl/nec_ir/src/nec_div8.sv
+$(USER_PROJECT_VERILOG)/rtl/nec_ir/src/nec_ir_tx.sv
+$(USER_PROJECT_VERILOG)/rtl/nec_ir/src/nec_ir_top.sv
+
diff --git a/verilog/rtl/bus_rep/bus_rep_east.sv b/verilog/rtl/bus_rep/bus_rep_east.sv
new file mode 100644
index 0000000..6e7626d
--- /dev/null
+++ b/verilog/rtl/bus_rep/bus_rep_east.sv
@@ -0,0 +1,52 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+// Bus Repater //
+//////////////////////////////////////////////////////////////////////
+module bus_rep_east #(
+ parameter BUS_REP_WD = 7
+ ) (
+`ifdef USE_POWER_PINS
+ input logic vccd1, // User area 1 1.8V supply
+ input logic vssd1, // User area 1 digital ground
+`endif
+ // Bus repeaters
+ input [BUS_REP_WD-1:0] ch_in,
+ output [BUS_REP_WD-1:0] ch_out
+ );
+
+// channel repeater
+
+`ifndef SYNTHESIS
+
+assign ch_out = ch_in;
+
+`else
+
+ genvar i;
+ generate
+ for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp
+ sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i]));
+ end
+ endgenerate
+
+`endif
+
+
+endmodule
+
diff --git a/verilog/rtl/bus_rep/bus_rep_north.sv b/verilog/rtl/bus_rep/bus_rep_north.sv
new file mode 100644
index 0000000..cbc3f24
--- /dev/null
+++ b/verilog/rtl/bus_rep/bus_rep_north.sv
@@ -0,0 +1,59 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+// Bus Repater //
+//////////////////////////////////////////////////////////////////////
+module bus_rep_north #(
+ parameter BUS_REP_WD = 7,
+ parameter BUS_BUF_WD = 42
+ ) (
+`ifdef USE_POWER_PINS
+ input logic vccd1, // User area 1 1.8V supply
+ input logic vssd1, // User area 1 digital ground
+`endif
+ // Bus repeaters
+ input [BUS_REP_WD-1:0] ch_in,
+ output [BUS_REP_WD-1:0] ch_out,
+ // Bus Buffering
+ input [BUS_BUF_WD-1:0] buf_in,
+ output [BUS_BUF_WD-1:0] buf_out
+ );
+
+// channel repeater
+
+`ifndef SYNTHESIS
+
+assign ch_out = ch_in;
+assign buf_out = buf_in;
+
+`else
+
+ genvar i;
+ generate
+ for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp
+ sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i]));
+ end
+ endgenerate
+
+assign buf_out = buf_in;
+
+`endif
+
+
+endmodule
+
diff --git a/verilog/rtl/bus_rep/bus_rep_south.sv b/verilog/rtl/bus_rep/bus_rep_south.sv
new file mode 100644
index 0000000..ea877be
--- /dev/null
+++ b/verilog/rtl/bus_rep/bus_rep_south.sv
@@ -0,0 +1,52 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+// Bus Repater //
+//////////////////////////////////////////////////////////////////////
+module bus_rep_south #(
+ parameter BUS_REP_WD = 7
+ ) (
+`ifdef USE_POWER_PINS
+ input logic vccd1, // User area 1 1.8V supply
+ input logic vssd1, // User area 1 digital ground
+`endif
+ // Bus repeaters
+ input [BUS_REP_WD-1:0] ch_in,
+ output [BUS_REP_WD-1:0] ch_out
+ );
+
+// channel repeater
+
+`ifndef SYNTHESIS
+
+assign ch_out = ch_in;
+
+`else
+
+ genvar i;
+ generate
+ for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp
+ sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i]));
+ end
+ endgenerate
+
+`endif
+
+
+endmodule
+
diff --git a/verilog/rtl/bus_rep/bus_rep_west.sv b/verilog/rtl/bus_rep/bus_rep_west.sv
new file mode 100644
index 0000000..f02c930
--- /dev/null
+++ b/verilog/rtl/bus_rep/bus_rep_west.sv
@@ -0,0 +1,52 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+// Bus Repater //
+//////////////////////////////////////////////////////////////////////
+module bus_rep_west #(
+ parameter BUS_REP_WD = 7
+ ) (
+`ifdef USE_POWER_PINS
+ input logic vccd1, // User area 1 1.8V supply
+ input logic vssd1, // User area 1 digital ground
+`endif
+ // Bus repeaters
+ input [BUS_REP_WD-1:0] ch_in,
+ output [BUS_REP_WD-1:0] ch_out
+ );
+
+// channel repeater
+
+`ifndef SYNTHESIS
+
+assign ch_out = ch_in;
+
+`else
+
+ genvar i;
+ generate
+ for (i = 0; i < BUS_REP_WD; i = i + 1) begin : u_rp
+ sky130_fd_sc_hd__clkbuf_4 u_buf ( .A(ch_in[i]), .X(ch_out[i]));
+ end
+ endgenerate
+
+`endif
+
+
+endmodule
+
diff --git a/verilog/rtl/bus_repeater.sv b/verilog/rtl/bus_repeater.sv
new file mode 100644
index 0000000..41fc3f4
--- /dev/null
+++ b/verilog/rtl/bus_repeater.sv
@@ -0,0 +1,960 @@
+/*********************************************
+ Bus Repeater SOUTH
+**********************************************/
+wire wb_clk_i_rp;
+wire wb_rst_i_rp ;
+wire wbs_cyc_i_rp ;
+wire wbs_stb_i_rp ;
+wire wbs_we_i_rp ;
+wire [3:0] wbs_sel_i_rp;
+wire [31:0] wbs_adr_i_rp;
+wire [31:0] wbs_dat_i_rp;
+
+wire wbs_ack_int_o ;
+wire [31:0] wbs_dat_int_o;
+
+wire [17:0] la_data_in_rp;
+
+wire [252:0] ch_in_south = {
+ user_clock2,
+ la_data_out_int[127],
+ la_data_out_int[126],
+ la_data_out_int[125],
+ la_data_out_int[124],
+ la_data_out_int[123],
+ la_data_out_int[122],
+ la_data_out_int[121],
+ la_data_out_int[120],
+ la_data_out_int[119],
+ la_data_out_int[118],
+ la_data_out_int[117],
+ la_data_out_int[116],
+ la_data_out_int[115],
+ la_data_out_int[114],
+ la_data_out_int[113],
+ la_data_out_int[112],
+ la_data_out_int[111],
+ la_data_out_int[110],
+ la_data_out_int[109],
+ la_data_out_int[108],
+ la_data_out_int[107],
+ la_data_out_int[106],
+ la_data_out_int[105],
+ la_data_out_int[104],
+ la_data_out_int[103],
+ la_data_out_int[102],
+ la_data_out_int[101],
+ la_data_out_int[100],
+ la_data_out_int[99],
+ la_data_out_int[98],
+ la_data_out_int[97],
+ la_data_out_int[96],
+ la_data_out_int[95],
+ la_data_out_int[94],
+ la_data_out_int[93],
+ la_data_out_int[92],
+ la_data_out_int[91],
+ la_data_out_int[90],
+ la_data_out_int[89],
+ la_data_out_int[88],
+ la_data_out_int[87],
+ la_data_out_int[86],
+ la_data_out_int[85],
+ la_data_out_int[84],
+ la_data_out_int[83],
+ la_data_out_int[82],
+ la_data_out_int[81],
+ la_data_out_int[80],
+ la_data_out_int[79],
+ la_data_out_int[78],
+ la_data_out_int[77],
+ la_data_out_int[76],
+ la_data_out_int[75],
+ la_data_out_int[74],
+ la_data_out_int[73],
+ la_data_out_int[72],
+ la_data_out_int[71],
+ la_data_out_int[70],
+ la_data_out_int[69],
+ la_data_out_int[68],
+ la_data_out_int[67],
+ la_data_out_int[66],
+ la_data_out_int[65],
+ la_data_out_int[64],
+ la_data_out_int[63],
+ la_data_out_int[62],
+ la_data_out_int[61],
+ la_data_out_int[60],
+ la_data_out_int[59],
+ la_data_out_int[58],
+ la_data_out_int[57],
+ la_data_out_int[56],
+ la_data_out_int[55],
+ la_data_out_int[54],
+ la_data_out_int[53],
+ la_data_out_int[52],
+ la_data_out_int[51],
+ la_data_out_int[50],
+ la_data_out_int[49],
+ la_data_out_int[48],
+ la_data_out_int[47],
+ la_data_out_int[46],
+ la_data_out_int[45],
+ la_data_out_int[44],
+ la_data_out_int[43],
+ la_data_out_int[42],
+ la_data_out_int[41],
+ la_data_out_int[40],
+ la_data_out_int[39],
+ la_data_out_int[38],
+ la_data_out_int[37],
+ la_data_out_int[36],
+ la_data_out_int[35],
+ la_data_out_int[34],
+ la_data_out_int[33],
+ la_data_out_int[32],
+ la_data_out_int[31],
+ la_data_out_int[30],
+ la_data_out_int[29],
+ la_data_out_int[28],
+ la_data_out_int[27],
+ la_data_out_int[26],
+ la_data_out_int[25],
+ la_data_out_int[24],
+ la_data_out_int[23],
+ la_data_out_int[22],
+ la_data_out_int[21],
+ la_data_out_int[20],
+ la_data_out_int[19],
+ la_data_out_int[18],
+ la_data_out_int[17],
+ la_data_in[17],
+ la_data_out_int[16],
+ la_data_in[16],
+ la_data_out_int[15],
+ la_data_in[15],
+ la_data_out_int[14],
+ la_data_in[14],
+ la_data_out_int[13],
+ la_data_in[13],
+ la_data_out_int[12],
+ la_data_in[12],
+ la_data_out_int[11],
+ la_data_in[11],
+ la_data_out_int[10],
+ la_data_in[10],
+ la_data_out_int[9],
+ la_data_in[9],
+ la_data_out_int[8],
+ la_data_in[8],
+ la_data_out_int[7],
+ la_data_in[7],
+ la_data_out_int[6],
+ la_data_in[6],
+ la_data_out_int[5],
+ la_data_in[5],
+ la_data_out_int[4],
+ la_data_in[4],
+ la_data_out_int[3],
+ la_data_in[3],
+ la_data_out_int[2],
+ la_data_in[2],
+ la_data_out_int[1],
+ la_data_in[1],
+ la_data_out_int[0],
+ la_data_in[0],
+
+ wbs_dat_int_o[31] , // 105
+ wbs_dat_i[31] ,
+ wbs_adr_i[31] ,
+ wbs_dat_int_o[30] ,
+ wbs_dat_i[30] ,
+ wbs_adr_i[30] ,
+ wbs_dat_int_o[29] ,
+ wbs_dat_i[29] ,
+ wbs_adr_i[29] ,
+ wbs_dat_int_o[28] ,
+ wbs_dat_i[28] ,
+ wbs_adr_i[28] ,
+ wbs_dat_int_o[27] ,
+ wbs_dat_i[27] ,
+ wbs_adr_i[27] ,
+ wbs_dat_int_o[26] ,
+ wbs_dat_i[26] ,
+ wbs_adr_i[26] ,
+ wbs_dat_int_o[25] ,
+ wbs_dat_i[25] ,
+ wbs_adr_i[25] ,
+ wbs_dat_int_o[24] ,
+ wbs_dat_i[24] ,
+ wbs_adr_i[24] ,
+ wbs_dat_int_o[23] ,
+ wbs_dat_i[23] ,
+ wbs_adr_i[23] ,
+ wbs_dat_int_o[22] ,
+ wbs_dat_i[22] ,
+ wbs_adr_i[22] ,
+ wbs_dat_int_o[21] ,
+ wbs_dat_i[21] ,
+ wbs_adr_i[21] ,
+ wbs_dat_int_o[20] ,
+ wbs_dat_i[20] ,
+ wbs_adr_i[20] ,
+ wbs_dat_int_o[19] ,
+ wbs_dat_i[19] ,
+ wbs_adr_i[19] ,
+ wbs_dat_int_o[18] ,
+ wbs_dat_i[18] ,
+ wbs_adr_i[18] ,
+ wbs_dat_int_o[17] ,
+ wbs_dat_i[17] ,
+ wbs_adr_i[17] ,
+ wbs_dat_int_o[16] ,
+ wbs_dat_i[16] ,
+ wbs_adr_i[16] ,
+ wbs_dat_int_o[15] ,
+ wbs_dat_i[15] ,
+ wbs_adr_i[15] ,
+ wbs_dat_int_o[14] ,
+ wbs_dat_i[14] ,
+ wbs_adr_i[14] ,
+ wbs_dat_int_o[13] ,
+ wbs_dat_i[13] ,
+ wbs_adr_i[13] ,
+ wbs_dat_int_o[12] ,
+ wbs_dat_i[12] ,
+ wbs_adr_i[12] ,
+ wbs_dat_int_o[11] ,
+ wbs_dat_i[11] ,
+ wbs_adr_i[11] ,
+ wbs_dat_int_o[10] ,
+ wbs_dat_i[10] ,
+ wbs_adr_i[10] ,
+ wbs_dat_int_o[9] ,
+ wbs_dat_i[9] ,
+ wbs_adr_i[9] ,
+ wbs_dat_int_o[8] , // 36
+ wbs_dat_i[8] ,
+ wbs_adr_i[8] ,
+ wbs_dat_int_o[7] , // 33
+ wbs_dat_i[7] ,
+ wbs_adr_i[7] ,
+ wbs_dat_int_o[6] , // 30
+ wbs_dat_i[6] ,
+ wbs_adr_i[6] ,
+ wbs_dat_int_o[5] , // 27
+ wbs_dat_i[5] ,
+ wbs_adr_i[5] ,
+ wbs_dat_int_o[4] , // 24
+ wbs_dat_i[4] ,
+ wbs_adr_i[4] ,
+ wbs_sel_i[3] ,
+ wbs_dat_int_o[3] , // 20
+ wbs_dat_i[3] ,
+ wbs_adr_i[3] ,
+ wbs_sel_i[2] ,
+ wbs_dat_int_o[2] , // 16
+ wbs_dat_i[2] ,
+ wbs_adr_i[2] ,
+ wbs_sel_i[1] ,
+ wbs_dat_int_o[1] , // 12
+ wbs_dat_i[1] ,
+ wbs_adr_i[1] ,
+ wbs_sel_i[0] ,
+ wbs_dat_int_o[0] , // 8
+ wbs_dat_i[0] ,
+ wbs_adr_i[0] ,
+ wbs_we_i ,
+ wbs_stb_i ,
+ wbs_cyc_i ,
+ wbs_ack_int_o ,
+ wb_rst_i ,
+ wb_clk_i
+ };
+wire [252:0] ch_out_south ;
+assign {
+ user_clock2_rp ,
+ la_data_out[127],
+ la_data_out[126],
+ la_data_out[125],
+ la_data_out[124],
+ la_data_out[123],
+ la_data_out[122],
+ la_data_out[121],
+ la_data_out[120],
+ la_data_out[119],
+ la_data_out[118],
+ la_data_out[117],
+ la_data_out[116],
+ la_data_out[115],
+ la_data_out[114],
+ la_data_out[113],
+ la_data_out[112],
+ la_data_out[111],
+ la_data_out[110],
+ la_data_out[109],
+ la_data_out[108],
+ la_data_out[107],
+ la_data_out[106],
+ la_data_out[105],
+ la_data_out[104],
+ la_data_out[103],
+ la_data_out[102],
+ la_data_out[101],
+ la_data_out[100],
+ la_data_out[99],
+ la_data_out[98],
+ la_data_out[97],
+ la_data_out[96],
+ la_data_out[95],
+ la_data_out[94],
+ la_data_out[93],
+ la_data_out[92],
+ la_data_out[91],
+ la_data_out[90],
+ la_data_out[89],
+ la_data_out[88],
+ la_data_out[87],
+ la_data_out[86],
+ la_data_out[85],
+ la_data_out[84],
+ la_data_out[83],
+ la_data_out[82],
+ la_data_out[81],
+ la_data_out[80],
+ la_data_out[79],
+ la_data_out[78],
+ la_data_out[77],
+ la_data_out[76],
+ la_data_out[75],
+ la_data_out[74],
+ la_data_out[73],
+ la_data_out[72],
+ la_data_out[71],
+ la_data_out[70],
+ la_data_out[69],
+ la_data_out[68],
+ la_data_out[67],
+ la_data_out[66],
+ la_data_out[65],
+ la_data_out[64],
+ la_data_out[63],
+ la_data_out[62],
+ la_data_out[61],
+ la_data_out[60],
+ la_data_out[59],
+ la_data_out[58],
+ la_data_out[57],
+ la_data_out[56],
+ la_data_out[55],
+ la_data_out[54],
+ la_data_out[53],
+ la_data_out[52],
+ la_data_out[51],
+ la_data_out[50],
+ la_data_out[49],
+ la_data_out[48],
+ la_data_out[47],
+ la_data_out[46],
+ la_data_out[45],
+ la_data_out[44],
+ la_data_out[43],
+ la_data_out[42],
+ la_data_out[41],
+ la_data_out[40],
+ la_data_out[39],
+ la_data_out[38],
+ la_data_out[37],
+ la_data_out[36],
+ la_data_out[35],
+ la_data_out[34],
+ la_data_out[33],
+ la_data_out[32],
+ la_data_out[31],
+ la_data_out[30],
+ la_data_out[29],
+ la_data_out[28],
+ la_data_out[27],
+ la_data_out[26],
+ la_data_out[25],
+ la_data_out[24],
+ la_data_out[23],
+ la_data_out[22],
+ la_data_out[21],
+ la_data_out[20],
+ la_data_out[19],
+ la_data_out[18],
+ la_data_out[17],
+ la_data_in_rp[17],
+ la_data_out[16],
+ la_data_in_rp[16],
+ la_data_out[15],
+ la_data_in_rp[15],
+ la_data_out[14],
+ la_data_in_rp[14],
+ la_data_out[13],
+ la_data_in_rp[13],
+ la_data_out[12],
+ la_data_in_rp[12],
+ la_data_out[11],
+ la_data_in_rp[11],
+ la_data_out[10],
+ la_data_in_rp[10],
+ la_data_out[9],
+ la_data_in_rp[9],
+ la_data_out[8],
+ la_data_in_rp[8],
+ la_data_out[7],
+ la_data_in_rp[7],
+ la_data_out[6],
+ la_data_in_rp[6],
+ la_data_out[5],
+ la_data_in_rp[5],
+ la_data_out[4],
+ la_data_in_rp[4],
+ la_data_out[3],
+ la_data_in_rp[3],
+ la_data_out[2],
+ la_data_in_rp[2],
+ la_data_out[1],
+ la_data_in_rp[1],
+ la_data_out[0],
+ la_data_in_rp[0],
+
+ wbs_dat_o[31] ,
+ wbs_dat_i_rp[31],
+ wbs_adr_i_rp[31],
+ wbs_dat_o[30] ,
+ wbs_dat_i_rp[30],
+ wbs_adr_i_rp[30],
+ wbs_dat_o[29] ,
+ wbs_dat_i_rp[29],
+ wbs_adr_i_rp[29],
+ wbs_dat_o[28] ,
+ wbs_dat_i_rp[28],
+ wbs_adr_i_rp[28],
+ wbs_dat_o[27] ,
+ wbs_dat_i_rp[27],
+ wbs_adr_i_rp[27],
+ wbs_dat_o[26] ,
+ wbs_dat_i_rp[26],
+ wbs_adr_i_rp[26],
+ wbs_dat_o[25] ,
+ wbs_dat_i_rp[25],
+ wbs_adr_i_rp[25],
+ wbs_dat_o[24] ,
+ wbs_dat_i_rp[24],
+ wbs_adr_i_rp[24],
+ wbs_dat_o[23] ,
+ wbs_dat_i_rp[23],
+ wbs_adr_i_rp[23],
+ wbs_dat_o[22] ,
+ wbs_dat_i_rp[22],
+ wbs_adr_i_rp[22],
+ wbs_dat_o[21] ,
+ wbs_dat_i_rp[21],
+ wbs_adr_i_rp[21],
+ wbs_dat_o[20] ,
+ wbs_dat_i_rp[20],
+ wbs_adr_i_rp[20],
+ wbs_dat_o[19] ,
+ wbs_dat_i_rp[19],
+ wbs_adr_i_rp[19],
+ wbs_dat_o[18] ,
+ wbs_dat_i_rp[18],
+ wbs_adr_i_rp[18],
+ wbs_dat_o[17] ,
+ wbs_dat_i_rp[17],
+ wbs_adr_i_rp[17],
+ wbs_dat_o[16] ,
+ wbs_dat_i_rp[16],
+ wbs_adr_i_rp[16],
+ wbs_dat_o[15] ,
+ wbs_dat_i_rp[15],
+ wbs_adr_i_rp[15],
+ wbs_dat_o[14] ,
+ wbs_dat_i_rp[14],
+ wbs_adr_i_rp[14],
+ wbs_dat_o[13] ,
+ wbs_dat_i_rp[13],
+ wbs_adr_i_rp[13],
+ wbs_dat_o[12] ,
+ wbs_dat_i_rp[12],
+ wbs_adr_i_rp[12],
+ wbs_dat_o[11] ,
+ wbs_dat_i_rp[11],
+ wbs_adr_i_rp[11],
+ wbs_dat_o[10] ,
+ wbs_dat_i_rp[10],
+ wbs_adr_i_rp[10],
+ wbs_dat_o[9] ,
+ wbs_dat_i_rp[9],
+ wbs_adr_i_rp[9],
+ wbs_dat_o[8] ,
+ wbs_dat_i_rp[8],
+ wbs_adr_i_rp[8],
+ wbs_dat_o[7] ,
+ wbs_dat_i_rp[7],
+ wbs_adr_i_rp[7],
+ wbs_dat_o[6] ,
+ wbs_dat_i_rp[6],
+ wbs_adr_i_rp[6],
+ wbs_dat_o[5] ,
+ wbs_dat_i_rp[5],
+ wbs_adr_i_rp[5],
+ wbs_dat_o[4] ,
+ wbs_dat_i_rp[4],
+ wbs_adr_i_rp[4],
+
+ wbs_sel_i_rp[3] ,
+ wbs_dat_o[3] ,
+ wbs_dat_i_rp[3] ,
+ wbs_adr_i_rp[3] ,
+ wbs_sel_i_rp[2] ,
+ wbs_dat_o[2] ,
+ wbs_dat_i_rp[2] ,
+ wbs_adr_i_rp[2] ,
+ wbs_sel_i_rp[1] ,
+ wbs_dat_o[1] ,
+ wbs_dat_i_rp[1] ,
+ wbs_adr_i_rp[1] ,
+ wbs_sel_i_rp[0] ,
+ wbs_dat_o[0] ,
+ wbs_dat_i_rp[0] ,
+ wbs_adr_i_rp[0] ,
+ wbs_we_i_rp ,
+ wbs_stb_i_rp ,
+ wbs_cyc_i_rp ,
+ wbs_ack_o ,
+ wb_rst_i_rp ,
+ wb_clk_i_rp
+ } = ch_out_south;
+
+bus_rep_south #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(253)
+`endif
+ ) u_rp_south(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
+`endif
+ .ch_in (ch_in_south),
+ .ch_out (ch_out_south)
+ );
+
+
+/*********************************************
+ Bus Repeater WEST
+**********************************************/
+
+wire [41:0] ch_in_west = {
+ io_oeb_rp1[37],
+ io_out_rp1[37],
+ io_in[37],
+ io_oeb_rp1[36],
+ io_out_rp1[36],
+ io_in[36],
+ io_oeb_rp1[35],
+ io_out_rp1[35],
+ io_in[35],
+ io_oeb_rp1[34],
+ io_out_rp1[34],
+ io_in[34],
+ io_oeb_rp1[33],
+ io_out_rp1[33],
+ io_in[33],
+ io_oeb_rp1[32],
+ io_out_rp1[32],
+ io_in[32],
+ io_oeb_rp1[31],
+ io_out_rp1[31],
+ io_in[31],
+ io_oeb_rp1[30],
+ io_out_rp1[30],
+ io_in[30],
+ io_oeb_rp1[29],
+ io_out_rp1[29],
+ io_in[29],
+ io_oeb_rp1[28],
+ io_out_rp1[28],
+ io_in[28],
+ io_oeb_rp1[27],
+ io_out_rp1[27],
+ io_in[27],
+ io_oeb_rp1[26],
+ io_out_rp1[26],
+ io_in[26],
+ io_oeb_rp1[25],
+ io_out_rp1[25],
+ io_in[25],
+ io_oeb_rp1[24],
+ io_out_rp1[24],
+ io_in[24]
+ };
+
+wire [41:0] ch_out_west ;
+assign {
+ io_oeb[37],
+ io_out[37],
+ io_in_rp1[37],
+ io_oeb[36],
+ io_out[36],
+ io_in_rp1[36],
+ io_oeb[35],
+ io_out[35],
+ io_in_rp1[35],
+ io_oeb[34],
+ io_out[34],
+ io_in_rp1[34],
+ io_oeb[33],
+ io_out[33],
+ io_in_rp1[33],
+ io_oeb[32],
+ io_out[32],
+ io_in_rp1[32],
+ io_oeb[31],
+ io_out[31],
+ io_in_rp1[31],
+ io_oeb[30],
+ io_out[30],
+ io_in_rp1[30],
+ io_oeb[29],
+ io_out[29],
+ io_in_rp1[29],
+ io_oeb[28],
+ io_out[28],
+ io_in_rp1[28],
+ io_oeb[27],
+ io_out[27],
+ io_in_rp1[27],
+ io_oeb[26],
+ io_out[26],
+ io_in_rp1[26],
+ io_oeb[25],
+ io_out[25],
+ io_in_rp1[25],
+ io_oeb[24],
+ io_out[24],
+ io_in_rp1[24]
+
+ } = ch_out_west;
+
+bus_rep_west #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(42)
+`endif
+ ) u_rp_west(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
+`endif
+ .ch_in (ch_in_west),
+ .ch_out (ch_out_west)
+ );
+
+/*********************************************
+ Bus Repeater NORTH
+**********************************************/
+
+wire [26:0] ch_in_north = {
+ io_in[15],
+ io_out_int[15],
+ io_oeb_int[15],
+ io_in[16],
+ io_out_int[16],
+ io_oeb_int[16],
+ io_in[17],
+ io_out_int[17],
+ io_oeb_int[17],
+ io_in[18],
+ io_out_int[18],
+ io_oeb_int[18],
+ io_in[19],
+ io_out_int[19],
+ io_oeb_int[19],
+ io_in[20],
+ io_out_int[20],
+ io_oeb_int[20],
+ io_in[21],
+ io_out_int[21],
+ io_oeb_int[21],
+ io_in[22],
+ io_out_int[22],
+ io_oeb_int[22],
+ io_in[23],
+ io_out_int[23],
+ io_oeb_int[23]
+ };
+
+
+wire [26:0] ch_out_north ;
+assign {
+ io_in_rp1[15],
+ io_out[15],
+ io_oeb[15],
+ io_in_rp1[16],
+ io_out[16],
+ io_oeb[16],
+ io_in_rp1[17],
+ io_out[17],
+ io_oeb[17],
+ io_in_rp1[18],
+ io_out[18],
+ io_oeb[18],
+ io_in_rp1[19],
+ io_out[19],
+ io_oeb[19],
+ io_in_rp1[20],
+ io_out[20],
+ io_oeb[20],
+ io_in_rp1[21],
+ io_out[21],
+ io_oeb[21],
+ io_in_rp1[22],
+ io_out[22],
+ io_oeb[22],
+ io_in_rp1[23],
+ io_out[23],
+ io_oeb[23]
+ } = ch_out_north;
+
+//--------------------------------------------------------------------------------
+// As West boundary is far from Pinmux module, there is feed through created
+// through the north repeater block
+// Buffering from Pinmux to PAD , feed through Pinmux <=> north <=> west
+//--------------------------------------------------------------------------------
+
+wire [41:0] buf_in_north = {
+ io_oeb_int[37],
+ io_out_int[37],
+ io_in_rp1[37],
+ io_oeb_int[36],
+ io_out_int[36],
+ io_in_rp1[36],
+ io_oeb_int[35],
+ io_out_int[35],
+ io_in_rp1[35],
+ io_oeb_int[34],
+ io_out_int[34],
+ io_in_rp1[34],
+ io_oeb_int[33],
+ io_out_int[33],
+ io_in_rp1[33],
+ io_oeb_int[32],
+ io_out_int[32],
+ io_in_rp1[32],
+ io_oeb_int[31],
+ io_out_int[31],
+ io_in_rp1[31],
+ io_oeb_int[30],
+ io_out_int[30],
+ io_in_rp1[30],
+ io_oeb_int[29],
+ io_out_int[29],
+ io_in_rp1[29],
+ io_oeb_int[28],
+ io_out_int[28],
+ io_in_rp1[28],
+ io_oeb_int[27],
+ io_out_int[27],
+ io_in_rp1[27],
+ io_oeb_int[26],
+ io_out_int[26],
+ io_in_rp1[26],
+ io_oeb_int[25],
+ io_out_int[25],
+ io_in_rp1[25],
+ io_oeb_int[24],
+ io_out_int[24],
+ io_in_rp1[24]
+ };
+
+wire [41:0] buf_out_north ;
+assign {
+ io_oeb_rp1[37],
+ io_out_rp1[37],
+ io_in_rp2[37],
+ io_oeb_rp1[36],
+ io_out_rp1[36],
+ io_in_rp2[36],
+ io_oeb_rp1[35],
+ io_out_rp1[35],
+ io_in_rp2[35],
+ io_oeb_rp1[34],
+ io_out_rp1[34],
+ io_in_rp2[34],
+ io_oeb_rp1[33],
+ io_out_rp1[33],
+ io_in_rp2[33],
+ io_oeb_rp1[32],
+ io_out_rp1[32],
+ io_in_rp2[32],
+ io_oeb_rp1[31],
+ io_out_rp1[31],
+ io_in_rp2[31],
+ io_oeb_rp1[30],
+ io_out_rp1[30],
+ io_in_rp2[30],
+ io_oeb_rp1[29],
+ io_out_rp1[29],
+ io_in_rp2[29],
+ io_oeb_rp1[28],
+ io_out_rp1[28],
+ io_in_rp2[28],
+ io_oeb_rp1[27],
+ io_out_rp1[27],
+ io_in_rp2[27],
+ io_oeb_rp1[26],
+ io_out_rp1[26],
+ io_in_rp2[26],
+ io_oeb_rp1[25],
+ io_out_rp1[25],
+ io_in_rp2[25],
+ io_oeb_rp1[24],
+ io_out_rp1[24],
+ io_in_rp2[24]
+
+ } = buf_out_north;
+
+bus_rep_north #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(27),
+.BUS_BUF_WD(42)
+`endif
+ ) u_rp_north(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
+`endif
+ .ch_in (ch_in_north),
+ .ch_out (ch_out_north),
+ .buf_in (buf_in_north),
+ .buf_out (buf_out_north)
+ );
+
+/*********************************************
+ Bus Repeater EAST
+**********************************************/
+
+wire [44:0] ch_in_east = {
+ io_in[0],
+ io_out_int[0],
+ io_oeb_int[0],
+ io_in[1],
+ io_out_int[1],
+ io_oeb_int[1],
+ io_in[2],
+ io_out_int[2],
+ io_oeb_int[2],
+ io_in[3],
+ io_out_int[3],
+ io_oeb_int[3],
+ io_in[4],
+ io_out_int[4],
+ io_oeb_int[4],
+ io_in[5],
+ io_out_int[5],
+ io_oeb_int[5],
+ io_in[6],
+ io_out_int[6],
+ io_oeb_int[6],
+ io_in[7],
+ io_out_int[7],
+ io_oeb_int[7],
+ io_in[8],
+ io_out_int[8],
+ io_oeb_int[8],
+ io_in[9],
+ io_out_int[9],
+ io_oeb_int[9],
+ io_in[10],
+ io_out_int[10],
+ io_oeb_int[10],
+ io_in[11],
+ io_out_int[11],
+ io_oeb_int[11],
+ io_in[12],
+ io_out_int[12],
+ io_oeb_int[12],
+ io_in[13],
+ io_out_int[13],
+ io_oeb_int[13],
+ io_in[14],
+ io_out_int[14],
+ io_oeb_int[14]
+ };
+
+
+wire [44:0] ch_out_east ;
+assign {
+ io_in_rp1[0],
+ io_out[0],
+ io_oeb[0],
+ io_in_rp1[1],
+ io_out[1],
+ io_oeb[1],
+ io_in_rp1[2],
+ io_out[2],
+ io_oeb[2],
+ io_in_rp1[3],
+ io_out[3],
+ io_oeb[3],
+ io_in_rp1[4],
+ io_out[4],
+ io_oeb[4],
+ io_in_rp1[5],
+ io_out[5],
+ io_oeb[5],
+ io_in_rp1[6],
+ io_out[6],
+ io_oeb[6],
+ io_in_rp1[7],
+ io_out[7],
+ io_oeb[7],
+ io_in_rp1[8],
+ io_out[8],
+ io_oeb[8],
+ io_in_rp1[9],
+ io_out[9],
+ io_oeb[9],
+ io_in_rp1[10],
+ io_out[10],
+ io_oeb[10],
+ io_in_rp1[11],
+ io_out[11],
+ io_oeb[11],
+ io_in_rp1[12],
+ io_out[12],
+ io_oeb[12],
+ io_in_rp1[13],
+ io_out[13],
+ io_oeb[13],
+ io_in_rp1[14],
+ io_out[14],
+ io_oeb[14]
+ } = ch_out_east;
+
+bus_rep_east #(
+`ifndef SYNTHESIS
+.BUS_REP_WD(45)
+`endif
+ ) u_rp_east(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
+`endif
+ .ch_in (ch_in_east),
+ .ch_out (ch_out_east)
+ );
+
+//---------------------------------------------------------
+// No Repeated added for these ports yet
+//---------------------------------------------------------
+//assign io_oeb[14:0] = io_oeb_int[14:0];
+//assign io_out[14:0] = io_out_int[14:0];
+assign io_in_rp[37:0] = {io_in_rp2[37:24],io_in_rp1[23:0]};
+
+//assign io_oeb[37:24] = io_oeb_int[37:24];
+//assign io_out[37:24] = io_out_int[37:24];
+//assign io_in_rp1[37:24] = io_in[37:24];
diff --git a/verilog/rtl/i2cm/src/core/i2cm_top.v b/verilog/rtl/i2cm/src/core/i2cm_top.v
index 2fea533..d929ec5 100755
--- a/verilog/rtl/i2cm/src/core/i2cm_top.v
+++ b/verilog/rtl/i2cm/src/core/i2cm_top.v
@@ -129,6 +129,17 @@
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
+//###################################
+// Application Reset Synchronization
+//###################################
+wire aresetn_ss;
+reset_sync u_app_rst (
+ .scan_mode (1'b0 ),
+ .dclk (wb_clk_i ), // Destination clock domain
+ .arst_n (aresetn ), // active low async reset
+ .srst_n (aresetn_ss )
+ );
+
//
// module body
//
@@ -157,8 +168,8 @@
end
// generate registers
- always @(posedge wb_clk_i or negedge aresetn)
- if (!aresetn)
+ always @(posedge wb_clk_i or negedge aresetn_ss)
+ if (!aresetn_ss)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
@@ -181,8 +192,8 @@
endcase
// generate command register (special case)
- always @(posedge wb_clk_i or negedge aresetn)
- if (!aresetn)
+ always @(posedge wb_clk_i or negedge aresetn_ss)
+ if (!aresetn_ss)
cr <= #1 8'h0;
else if (!sresetn)
cr <= #1 8'h0;
@@ -217,7 +228,7 @@
i2cm_byte_ctrl u_byte_ctrl (
.clk ( wb_clk_i ),
.sresetn ( sresetn ),
- .aresetn ( aresetn ),
+ .aresetn ( aresetn_ss ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
@@ -241,8 +252,8 @@
);
// status register block + interrupt request signal
- always @(posedge wb_clk_i or negedge aresetn)
- if (!aresetn)
+ always @(posedge wb_clk_i or negedge aresetn_ss)
+ if (!aresetn_ss)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
@@ -265,8 +276,8 @@
end
// generate interrupt request signals
- always @(posedge wb_clk_i or negedge aresetn)
- if (!aresetn)
+ always @(posedge wb_clk_i or negedge aresetn_ss)
+ if (!aresetn_ss)
wb_inta_o <= #1 1'b0;
else if (!sresetn)
wb_inta_o <= #1 1'b0;
diff --git a/verilog/rtl/lib/async_reg_bus.sv b/verilog/rtl/lib/async_reg_bus.sv
index 3392cbf..02dca1d 100644
--- a/verilog/rtl/lib/async_reg_bus.sv
+++ b/verilog/rtl/lib/async_reg_bus.sv
@@ -58,9 +58,10 @@
out_reg_rdata ,
out_reg_ack
);
-parameter AW = 26 ; // Address width
-parameter DW = 32 ; // DATA WIDTH
-parameter BEW = 4 ; // Byte enable width
+parameter AW = 26 ; // Address width
+parameter DW = 32 ; // DATA WIDTH
+parameter BEW = 4 ; // Byte enable width
+parameter TIMEOUT_ENB = 1 ; // TIMEOUT Generation enabled
//----------------------------------------
// Reg Bus reg inout declration
@@ -191,17 +192,18 @@
in_reg_ack <= 1'b1;
in_state <= INI_WAIT_TAR_DONE;
end
- else begin
- if(in_timer == 9'h1FF) begin
- in_flag <= 1'b0;
- in_reg_ack <= 1'b1;
- in_reg_rdata <= 32'h0;
- in_reg_timeout <= 1'b1;
- in_state <= INI_IDLE;
- end
- else begin
- in_timer <= in_timer + 1;
- end
+ else begin if(TIMEOUT_ENB) begin
+ if(in_timer == 9'h1FF ) begin
+ in_flag <= 1'b0;
+ in_reg_ack <= 1'b1;
+ in_reg_rdata <= 32'h0;
+ in_reg_timeout <= 1'b1;
+ in_state <= INI_IDLE;
+ end
+ else begin
+ in_timer <= in_timer + 1;
+ end
+ end
end
end
INI_WAIT_TAR_DONE :
diff --git a/verilog/rtl/lib/clk_skew_adjust.gv b/verilog/rtl/lib/clk_skew_adjust.gv
index fc811c0..40655c9 100644
--- a/verilog/rtl/lib/clk_skew_adjust.gv
+++ b/verilog/rtl/lib/clk_skew_adjust.gv
@@ -157,24 +157,25 @@
ctech_delay_clkbuf clkbuf_15 (.A(clk_d14), .X(clk_d15));
- // Tap point selection
- assign in0 = clk_in;
- assign in1 = clk_d1;
- assign in2 = clk_d2;
- assign in3 = clk_d3;
- assign in4 = clk_d4;
- assign in5 = clk_d5;
- assign in6 = clk_d6;
- assign in7 = clk_d7;
- assign in8 = clk_d8;
- assign in9 = clk_d9;
- assign in10 = clk_d10;
- assign in11 = clk_d11;
- assign in12 = clk_d12;
- assign in13 = clk_d13;
- assign in14 = clk_d14;
- assign in15 = clk_d15;
+
+ // Tap point selection
+ ctech_clk_buf u_tap_0 (.A(clk_in), .X(in0));
+ ctech_clk_buf u_tap_1 (.A(clk_d1), .X(in1));
+ ctech_clk_buf u_tap_2 (.A(clk_d2), .X(in2));
+ ctech_clk_buf u_tap_3 (.A(clk_d3), .X(in3));
+ ctech_clk_buf u_tap_4 (.A(clk_d4), .X(in4));
+ ctech_clk_buf u_tap_5 (.A(clk_d5), .X(in5));
+ ctech_clk_buf u_tap_6 (.A(clk_d6), .X(in6));
+ ctech_clk_buf u_tap_7 (.A(clk_d7), .X(in7));
+ ctech_clk_buf u_tap_8 (.A(clk_d8), .X(in8));
+ ctech_clk_buf u_tap_9 (.A(clk_d9), .X(in9));
+ ctech_clk_buf u_tap_10 (.A(clk_d10), .X(in10));
+ ctech_clk_buf u_tap_11 (.A(clk_d11), .X(in11));
+ ctech_clk_buf u_tap_12 (.A(clk_d12), .X(in12));
+ ctech_clk_buf u_tap_13 (.A(clk_d13), .X(in13));
+ ctech_clk_buf u_tap_14 (.A(clk_d14), .X(in14));
+ ctech_clk_buf u_tap_15 (.A(clk_d15), .X(in15));
// first level mux - 8
ctech_mux2x1_2 u_mux_level_00 ( .X (d00) , .A0 (in0), .A1(in1), .S(sel[0]));
diff --git a/verilog/rtl/lib/metastability_filter.sv b/verilog/rtl/lib/metastability_filter.sv
new file mode 100644
index 0000000..ede8339
--- /dev/null
+++ b/verilog/rtl/lib/metastability_filter.sv
@@ -0,0 +1,44 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Metastability filter
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+module metastability_filter #(
+ parameter NB_STAGES = 3
+)(
+ input wire rst_n , // Asynchronous reset (active low)
+ input wire clk , // Clock (rising edge)
+
+ input wire i_raw , // Raw input
+ output wire o_filtered // Filtered output
+);
+
+ reg [NB_STAGES-1:0] meta_i;
+
+ always @(negedge rst_n or posedge clk) begin
+ if (rst_n == 1'b0) begin
+ meta_i <= 'b0;
+ end else begin
+ meta_i <= {meta_i[NB_STAGES-2: 0],i_raw};
+ end
+ end
+ assign o_filtered = meta_i[NB_STAGES-1];
+
+endmodule
diff --git a/verilog/rtl/lib/prescaler.v b/verilog/rtl/lib/prescaler.v
new file mode 100644
index 0000000..860cbe0
--- /dev/null
+++ b/verilog/rtl/lib/prescaler.v
@@ -0,0 +1,68 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
+
+module prescaler #(
+ parameter BITS = 32
+)(
+ input wire rst_n , // Asynchronous reset (active low)
+ input wire clk , // Clock (rising edge)
+ input wire clear_n , // Synchronous reset (active low)
+
+ input wire [BITS-1:0] multiplier , // frequency multiplier
+ input wire [BITS-1:0] divider , // frequency divider
+
+ output reg tick // output clock [Ftick=Fclk*(multiplier/divider)] with multiplier <= divider
+
+);
+
+ reg [BITS-1:0] div;
+ reg [BITS-1:0] mul;
+ reg [BITS-1:0] div_m_mul;
+ reg [BITS-1:0] mul_m_div;
+ reg [BITS-1:0] counter;
+
+ always @(negedge rst_n or posedge clk) begin
+ if (rst_n == 1'b0) begin
+ mul <= {(BITS){1'b0}};
+ div <= {(BITS){1'b0}};
+ div_m_mul <= {(BITS){1'b0}};
+ mul_m_div <= {(BITS){1'b0}};
+ counter <= {(BITS){1'b0}};
+ tick <= 1'b0;
+ end else begin
+ if (clear_n == 1'b0) begin
+ counter <= {(BITS){1'b0}};
+ tick <= 1'b0;
+ end else begin
+ if (counter > div_m_mul) begin
+ counter <= counter + mul_m_div;
+ tick <= 1'b1;
+ end else begin
+ counter <= counter + mul;
+ tick <= 1'b0;
+ end
+ end
+ mul <= multiplier;
+ div <= divider ;
+ div_m_mul <= div - mul ;
+ mul_m_div <= mul - div ;
+ end
+ end
+
+endmodule
diff --git a/verilog/rtl/lib/pulse_filter.sv b/verilog/rtl/lib/pulse_filter.sv
new file mode 100644
index 0000000..f5f251d
--- /dev/null
+++ b/verilog/rtl/lib/pulse_filter.sv
@@ -0,0 +1,60 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Pulse filter
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+module pulse_filter (
+ input wire rst_n , // Asynchronous reset (active low)
+ input wire clk , // Clock (rising edge)
+ input wire clear_n , // Synchronous reset (active low)
+
+ input wire i_value , // Input value
+ input wire i_valid , // Input valid strobe
+
+ output wire o_value , // Output value
+ output reg o_valid // Output valid strobe
+);
+
+ reg [2:0] filter_reg;
+
+ always @(negedge rst_n or posedge clk) begin
+ if (rst_n == 1'b0) begin
+ filter_reg <= 'b0;
+ o_valid <= 1'b0;
+ end else begin
+ if (clear_n == 1'b0) begin
+ filter_reg <= 'b0;
+ o_valid <= 1'b0;
+ end else begin
+ if (i_valid == 1'b1) begin
+ filter_reg[2] <= i_value;
+ filter_reg[1] <= filter_reg[2];
+ filter_reg[0] <= filter_reg[1];
+ o_valid <= 1'b1;
+ end else begin
+ o_valid <= 1'b0;
+ end
+ end
+ end
+ end
+
+ assign o_value = (filter_reg[0] & filter_reg[1]) |
+ (filter_reg[1] & filter_reg[2]) |
+ (filter_reg[2] & filter_reg[0]) ;
+endmodule
diff --git a/verilog/rtl/lib/simple_fifo.v b/verilog/rtl/lib/simple_fifo.v
new file mode 100644
index 0000000..9440924
--- /dev/null
+++ b/verilog/rtl/lib/simple_fifo.v
@@ -0,0 +1,86 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
+module simple_fifo #(
+ parameter ASIZE = 5 , // FIFO size (FIFO_size=(2**ASIZE)-1)
+ parameter DSIZE = 32 // Number of bits of data
+)(
+ input wire rst_n , // Asynchronous reset (active low)
+ input wire clk , // Clock (rising edge)
+ input wire clear_n , // Synchronous clear (active low)
+
+ // Write port
+ input wire [DSIZE-1:0] wr_data ,
+ input wire wr_valid,
+ output wire wr_ready, // Ready flag (0: FIFO full, 1: FIFO not full)
+
+ // Read port
+ output wire [DSIZE-1:0] rd_data ,
+ output wire rd_valid,
+ input wire rd_ready // Ready flag (0: FIFO empty, 1: FIFO not empty)
+);
+
+ wire [ASIZE-1:0] rd_ptr_next ;
+ wire [ASIZE-1:0] wr_ptr_next ;
+ reg [ASIZE-1:0] rd_ptr ;
+ reg [ASIZE-1:0] wr_ptr ;
+ reg [DSIZE-1:0] memory[2**ASIZE-1:0];
+
+ assign wr_ptr_next = wr_ptr + 1'b1;
+ assign rd_ptr_next = rd_ptr + 1'b1;
+
+ assign wr_ready = (wr_ptr_next != rd_ptr);
+ assign rd_valid = (rd_ptr != wr_ptr);
+
+ // Write pointer update
+ always @(negedge rst_n or posedge clk) begin
+ if (rst_n == 1'b0) begin
+ wr_ptr <= 'b0;
+ end else begin
+ if (clear_n == 1'b0) begin
+ wr_ptr <= 'b0;
+ end else if (wr_valid && wr_ready) begin
+ wr_ptr <= wr_ptr_next;
+ end
+ end
+ end
+
+ // Write operation
+ always @(posedge clk) begin
+ if (wr_valid && wr_ready) begin
+ memory[wr_ptr] <= wr_data;
+ end
+ end
+
+ // Read pointer update
+ always @(negedge rst_n or posedge clk) begin
+ if (rst_n == 1'b0) begin
+ rd_ptr <= 'b0;
+ end else begin
+ if (clear_n == 1'b0) begin
+ rd_ptr <= 'b0;
+ end else if (rd_valid && rd_ready) begin
+ rd_ptr <= rd_ptr_next;
+ end
+ end
+ end
+
+ // Read operation
+ assign rd_data = memory[rd_ptr];
+
+endmodule
diff --git a/verilog/rtl/lib/sync_fifo_occ.sv b/verilog/rtl/lib/sync_fifo_occ.sv
new file mode 100755
index 0000000..e842e91
--- /dev/null
+++ b/verilog/rtl/lib/sync_fifo_occ.sv
@@ -0,0 +1,161 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+/*********************************************************************
+
+ Description: SYNC FIFO with Occupancy
+ Parameters:
+ WD : Width (integer)
+ DP : Depth (integer, power of 2, 4 to 256)
+
+ To Do:
+ nothing
+
+ Author(s): Dinesh Annayya, dinesha@opencores.org
+
+ Copyright (C) 2000 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml
+
+*******************************************************************/
+
+
+module sync_fifo_occ #(parameter WD = 8,parameter DP = 4,
+ parameter AW = (DP == 2) ? 1 :
+ (DP == 4) ? 2 :
+ (DP == 8) ? 3 :
+ (DP == 16) ? 4 :
+ (DP == 32) ? 5 :
+ (DP == 64) ? 6 :
+ (DP == 128) ? 7 :
+ (DP == 256) ? 8 : 0) (
+
+ input logic clk , // Clock
+ input logic reset_n , // Reset
+ input logic sreset_n , // Synchronous Reset
+ input logic wr_en , // FIFO Write enable
+ input logic [WD-1:0] wr_data , // FIFO Write Data
+ output logic full , // FIFO Full
+ output logic empty , // FIFO Empty
+ input logic rd_en , // FIFO Read enable
+ output logic [WD-1:0] rd_data , // FIFO Read Data
+ output logic [AW:0] occupancy // Show the current FIFO occpancy
+ );
+
+
+
+
+ // synopsys translate_off
+
+ initial begin
+ if (AW == 0) begin
+ $display ("%m : ERROR!!! Fifo depth %d not in range 4 to 256", DP);
+ end // if (AW == 0)
+ end // initial begin
+
+ // synopsys translate_on
+
+
+ reg [WD-1 : 0] mem[DP-1 : 0];
+ reg [AW-1 : 0] rd_ptr, wr_ptr;
+
+
+ assign empty = (occupancy == 0);
+ assign full = (occupancy == DP);
+
+ // occpuancy computation
+ always @ (posedge clk or negedge reset_n)
+ if (reset_n == 1'b0) begin
+ occupancy <= 'h0;
+ end else if(sreset_n == 1'b0) begin
+ occupancy <= 'h0;
+ end else begin
+ if ((wr_en & !full) && (rd_en == 1'b0 )) begin // Write Only
+ occupancy <= occupancy + 1'b1 ;
+ end else if ((rd_en & !empty) && (wr_en == 1'b0 )) begin // Read Only
+ occupancy <= occupancy - 1'b1 ;
+ end
+ end
+
+
+ always @ (posedge clk or negedge reset_n)
+ if (reset_n == 1'b0) begin
+ wr_ptr <= {AW{1'b0}} ;
+ end else if(sreset_n == 1'b0) begin
+ wr_ptr <= {AW{1'b0}} ;
+ end else begin
+ if (wr_en & !full) begin
+ wr_ptr <= wr_ptr + 1'b1 ;
+ end
+ end
+
+ always @ (posedge clk or negedge reset_n)
+ if (reset_n == 1'b0) begin
+ rd_ptr <= {AW{1'b0}} ;
+ end else if(sreset_n == 1'b0) begin
+ rd_ptr <= {AW{1'b0}} ;
+ end else begin
+ if (rd_en & !empty) begin
+ rd_ptr <= rd_ptr + 1'b1 ;
+ end
+ end
+
+ always @ (posedge clk)
+ if (wr_en)
+ mem[wr_ptr] <= wr_data;
+
+assign rd_data = mem[rd_ptr];
+
+
+// synopsys translate_off
+ always @(posedge clk) begin
+ if (wr_en && full) begin
+ $display("%m : Error! sfifo overflow!");
+ end
+ end
+
+ always @(posedge clk) begin
+ if (rd_en && empty) begin
+ $display("%m : error! sfifo underflow!");
+ end
+ end
+
+// synopsys translate_on
+//---------------------------------------
+
+endmodule
+
+
diff --git a/verilog/rtl/nec_ir/src/nec_div8.sv b/verilog/rtl/nec_ir/src/nec_div8.sv
new file mode 100644
index 0000000..a4c2fe8
--- /dev/null
+++ b/verilog/rtl/nec_ir/src/nec_div8.sv
@@ -0,0 +1,46 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+// tick div8 block
+//////////////////////////////////////////////////////////////////////
+
+module nec_div8 (
+ input logic rst_n , // Asynchronous reset (active low)
+ input logic clk , // Clock (rising edge)
+ input logic tick ,
+ output logic tick_div8
+
+ );
+
+
+ logic [2:0] cnt;
+ always @(negedge rst_n or posedge clk) begin
+ if (rst_n == 1'b0) begin
+ cnt <= '0;
+ tick_div8 <= 'b0;
+ end else begin
+ if(tick) cnt <= cnt + 1;
+ if(cnt == 7 && tick) tick_div8 <= 1'b1;
+ else tick_div8 <= 1'b0;
+
+ end
+ end
+
+
+
+endmodule
diff --git a/verilog/rtl/nec_ir/src/nec_ir_event_catcher.sv b/verilog/rtl/nec_ir/src/nec_ir_event_catcher.sv
new file mode 100644
index 0000000..46d5201
--- /dev/null
+++ b/verilog/rtl/nec_ir/src/nec_ir_event_catcher.sv
@@ -0,0 +1,99 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Event catcher
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+module nec_ir_event_catcher #(
+ parameter DBITS = 32 // Number of bits of delay counter
+)(
+ input wire rst_n , // Asynchronous reset (active low)
+ input wire clk , // Clock (rising edge)
+ input wire clear_n , // Synchronous reset (active low)
+ input wire [DBITS-1:0] reload_offset , // Delay counter reload offset
+
+ input wire i_value , // Input value
+ input wire i_valid , // Input valid strobe
+
+ output reg event_new ,
+ output reg event_type ,
+ output reg [DBITS-1:0] event_delay ,
+ output reg event_timeout
+);
+
+ wire detect_event;
+ wire [DBITS-1:0] next_cnt;
+ wire full_cnt;
+
+ reg last_value;
+ reg [DBITS-1:0] cnt;
+
+ assign detect_event = (i_value != last_value);
+ assign next_cnt = cnt + 1'b1;
+ assign full_cnt = (cnt == {DBITS{1'b1}});
+
+ // Event catcher
+ always @(negedge rst_n or posedge clk) begin
+ if (rst_n == 1'b0) begin
+ last_value <= 1'b0;
+ cnt <= {DBITS{1'b1}};
+ event_new <= 1'b0;
+ event_type <= 1'b0;
+ event_delay <= {DBITS{1'b0}};
+ event_timeout <= 1'b0;
+ end else begin
+
+ if (clear_n == 1'b0) begin
+ last_value <= 1'b0;
+ cnt <= {DBITS{1'b1}};
+ event_new <= 1'b0;
+ event_type <= 1'b0;
+ event_delay <= {DBITS{1'b0}};
+ event_timeout <= 1'b0;
+ end else begin
+
+ if (i_valid == 1'b1) begin
+
+ //event detect
+ last_value <= i_value;
+
+ //counter update
+ if (detect_event == 1'b1) begin
+ cnt <= reload_offset;
+ end else if (!full_cnt) begin
+ cnt <= next_cnt;
+ end
+ end
+
+ //report event
+ if ((i_valid == 1'b1) && (detect_event == 1'b1)) begin
+ event_new <= 1'b1;
+ event_type <= i_value; // 1: rising_edge, 0: falling_edge
+ event_delay <= next_cnt;
+ event_timeout <= full_cnt;
+ end else begin
+ event_new <= 1'b0;
+ end
+
+ end
+
+ end
+ end
+
+endmodule
diff --git a/verilog/rtl/nec_ir/src/nec_ir_frame_decoder.sv b/verilog/rtl/nec_ir/src/nec_ir_frame_decoder.sv
new file mode 100644
index 0000000..129f816
--- /dev/null
+++ b/verilog/rtl/nec_ir/src/nec_ir_frame_decoder.sv
@@ -0,0 +1,176 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Frame decoder
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+module nec_ir_frame_decoder #(
+ parameter DBITS = 32 // Number of bits of delay counter
+)(
+ input wire rst_n , // Asynchronous reset (active low)
+ input wire clk , // Clock (rising edge)
+
+ input wire receiver_en , // Receiver enable
+ input wire repeat_en , // Repeat enable
+ input wire [DBITS-1:0] delay_mask , // Mask delay
+
+ // Input event interface
+ input wire event_new , // New event strobe
+ input wire event_type , // Type of event (0:rising, 1:falling)
+ input wire [DBITS-1:0] event_delay , // Delay from last event
+ input wire event_timeout , // Timeout flag
+
+ // Output frame interface
+ output reg [7:0] frame_addr , // Frame address
+ output reg [7:0] frame_data , // Frame data
+ output reg frame_repeat , // Frame repeat flag
+ output reg frame_write // Frame write strobe
+);
+
+ localparam
+ idle_state = 3'b000,
+ start_state = 3'b001,
+ data_prefix_state = 3'b010,
+ data_latch_state = 3'b011,
+ stop_state = 3'b100,
+ idle_a_state = 3'b101,
+ idle_b_state = 3'b110,
+ idle_c_state = 3'b111;
+
+ reg [2:0] frame_state_reg ;
+ wire is_valid_start_a ;
+ wire is_valid_start_b ;
+ wire is_valid_repeat ;
+ wire is_valid_bit_prefix ;
+ wire is_valid_bit_zero ;
+ wire is_valid_bit_one ;
+ wire is_valid_bit ;
+ wire is_valid_stop ;
+ wire is_valid_addr ;
+ wire is_valid_data ;
+
+ reg [31:0] frame_shift ;
+ reg initial_timeout;
+
+ assign is_valid_start_a = ((event_timeout == 1'b0) && (event_type == 1'b0) && ((event_delay & delay_mask) == 128)); // 9.00ms pulse to 1'b1
+ assign is_valid_start_b = ((event_timeout == 1'b0) && (event_type == 1'b1) && ((event_delay & delay_mask) == 64)); // 4.50ms pulse to 1'b0
+ assign is_valid_repeat = ((event_timeout == 1'b0) && (event_type == 1'b1) && ((event_delay & delay_mask) == 32) && (initial_timeout == 0)); // 2.25ms pulse to 1'b0
+ assign is_valid_bit_prefix = ((event_timeout == 1'b0) && (event_type == 1'b0) && ((event_delay & delay_mask) == 8));
+ assign is_valid_bit_zero = ((event_timeout == 1'b0) && (event_type == 1'b1) && ((event_delay & delay_mask) == 8));
+ assign is_valid_bit_one = ((event_timeout == 1'b0) && (event_type == 1'b1) && ((event_delay & delay_mask) == 24));
+ assign is_valid_bit = (is_valid_bit_zero || is_valid_bit_one);
+ assign is_valid_stop = ((event_timeout == 1'b0) && (event_type == 1'b0) && ((event_delay & delay_mask) == 8));
+ assign is_valid_addr = ((frame_shift[7:0] == ~frame_shift[15:8]));
+ assign is_valid_data = ((frame_shift[23:16] == ~frame_shift[31:24]));
+
+ // Frame decoder
+ always @(negedge rst_n or posedge clk) begin
+ if (rst_n == 1'b0) begin
+ frame_state_reg <= idle_state;
+ frame_shift <= 32'h80000000;
+ frame_repeat <= 1'b0;
+ frame_write <= 1'b0;
+ frame_addr <= 8'h00;
+ frame_data <= 8'h00;
+ end else begin
+
+ if (receiver_en == 1'b0) begin
+ frame_state_reg <= idle_state;
+ initial_timeout <= 1'b1;
+ frame_shift <= 32'h80000000;
+ frame_repeat <= 1'b0;
+ end else begin
+ if (event_new == 1'b1) begin
+ case(frame_state_reg)
+ idle_state,
+ idle_a_state,
+ idle_b_state,
+ idle_c_state:
+ if(is_valid_start_a) begin
+ frame_state_reg <= start_state;
+ end
+ start_state:
+ if (is_valid_start_b) begin
+ frame_state_reg <= data_prefix_state;
+ end else if (repeat_en && is_valid_repeat) begin
+ frame_state_reg <= stop_state;
+ end else begin
+ frame_state_reg <= idle_state;
+ end
+ data_prefix_state:
+ if (is_valid_bit_prefix) begin
+ frame_state_reg <= data_latch_state;
+ end else begin
+ frame_state_reg <= idle_state;
+ end
+ data_latch_state:
+ if (is_valid_bit) begin
+ if (frame_shift[0] == 1'b1) begin
+ frame_state_reg <= stop_state;
+ end else begin
+ frame_state_reg <= data_prefix_state;
+ end
+ end else begin
+ frame_state_reg <= idle_state;
+ end
+ stop_state:
+ frame_state_reg <= idle_state;
+ default:
+ frame_state_reg <= idle_state;
+ endcase
+
+ if ((frame_state_reg == idle_state) && (event_timeout == 1'b1)) begin
+ initial_timeout <= 1'b1;
+ end else if ((frame_state_reg == stop_state) && is_valid_stop && is_valid_addr && is_valid_data && (frame_repeat == 0)) begin
+ initial_timeout <= 1'b0;
+ end
+
+ if ((frame_state_reg == start_state) && is_valid_start_b) begin
+ frame_shift <= 32'h80000000;
+ end else if (frame_state_reg == data_latch_state) begin
+ if (is_valid_bit_zero) begin
+ frame_shift <= {1'b0, frame_shift[31:1]};
+ end else begin
+ frame_shift <= {1'b1, frame_shift[31:1]};
+ end
+ end
+
+ if (frame_state_reg == start_state) begin
+ if (repeat_en && is_valid_repeat) begin
+ frame_repeat <= 1'b1;
+ end else begin
+ frame_repeat <= 1'b0;
+ end
+ end
+
+ end
+
+ if ((receiver_en == 1'b1) && (event_new == 1'b1) && (frame_state_reg == stop_state) && is_valid_stop && is_valid_addr && is_valid_data) begin
+ frame_write <= 1'b1;
+ frame_addr <= frame_shift[7:0];
+ frame_data <= frame_shift[23:16];
+ end else begin
+ frame_write <= 1'b0;
+ end
+ end
+ end
+ end
+
+endmodule
diff --git a/verilog/rtl/nec_ir/src/nec_ir_regs.sv b/verilog/rtl/nec_ir/src/nec_ir_regs.sv
new file mode 100644
index 0000000..dff5ca9
--- /dev/null
+++ b/verilog/rtl/nec_ir/src/nec_ir_regs.sv
@@ -0,0 +1,246 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , <Julien OURY/Dinesh Annayya>
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+// and Dinesh Annayya <dinesh.annayya@gmail.com>
+//
+////////////////////////////////////////////////////////////////////////////
+/**********************************************************************
+
+ NEC IR Register
+
+ This file is part of the riscduino cores project
+ https://github.com/dineshannayya/riscduino.git
+
+
+ To Do:
+ nothing
+
+ Author(s):
+ - Julien OURY <julien.oury@outlook.fr>
+ - Dinesh Annayya <dinesh.annayya@gmail.com>
+
+ Revision :
+ 0.1 - 11 Dec 2022, Dinesh A
+ initial version picked from
+ https://github.com/JulienOury/ChristmasTreeController
+ 0.2 - 13 Dec 2022, Dinesh A
+ A. Bug fix, Read access clearing the register content
+ B. FIFO Occpancy added
+ C. Support for IR Transmitter
+
+***************************************************************************/
+
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Registers
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+module nec_ir_regs #(
+ parameter PSIZE = 32 , // Size of prescaler counter(bits)
+ parameter DSIZE = 32 , // Size of delay counter (bits)
+ parameter ASIZE = 3 // MEMORY ADDRESS POINTER SIZE
+)(
+
+ input logic rst_n , // Asynchronous reset (active low)
+ input logic clk , // Clock (rising edge)
+
+ // Configuration
+ output logic cfg_ir_en , // IR Global Enable
+ output logic cfg_ir_tx_en , // Transmitter enable
+ output logic cfg_ir_rx_en , // Receiver enable
+ output logic cfg_repeat_en , // Repeat enable
+ output logic cfg_tx_polarity , // Polarity (value of idle state)
+ output logic cfg_rx_polarity , // Polarity (value of idle state)
+ output logic [PSIZE-1:0] cfg_multiplier , // frequency multiplier
+ output logic [PSIZE-1:0] cfg_divider , // frequency divider
+ output logic [DSIZE-1:0] reload_offset , // Delay counter reload offset
+ output logic [DSIZE-1:0] delay_mask , // Mask delay
+
+ // Wishbone bus
+ input logic wbs_cyc_i , // Wishbone strobe/request
+ input logic wbs_stb_i , // Wishbone strobe/request
+ input logic [4:0] wbs_adr_i , // Wishbone address
+ input logic wbs_we_i , // Wishbone write (1:write, 0:read)
+ input logic [31:0] wbs_dat_i , // Wishbone data output
+ input logic [ 3:0] wbs_sel_i , // Wishbone byte enable
+ output logic [31:0] wbs_dat_o , // Wishbone data input
+ output logic wbs_ack_o , // Wishbone acknowlegement
+
+ // Input frame interface
+ // <IR RECEIVER> => <RX FIFO> => WB
+ input logic rx_frame_new , // New frame received
+ input logic fifo_rx_full , // RX FIFO full
+ input logic [16:0] fifo_rx_rdata , // RX FIFO Read Data
+ output logic fifo_rx_read , // RX FIFO Read
+ input logic [ASIZE:0] fifo_rx_occ , // RX FIFO Occupancy
+
+ // <WB> => <TX FIFO> => <IR Transmitter>
+ input logic fifo_tx_full , // Tx FIFO full
+ output logic [15:0] fifo_tx_wdata , // TX FIFO Wdata
+ output logic fifo_tx_write , // TX FIFO Write
+ input logic [ASIZE:0] fifo_tx_occ , // FIFO TX Occpancy
+
+ // Interrupt
+ output reg irq // Interrupt
+
+ );
+
+ localparam
+ IR_CFG_CMD = 3'b000,
+ IR_CFG_MULTIPLIER = 3'b001,
+ IR_CFG_DIVIDER = 3'b010,
+ IR_CFG_RX_DATA = 3'b011,
+ IR_CFG_TX_DATA = 3'b100;
+
+
+ logic valid;
+ logic rstrb;
+ logic [2:0] addr;
+
+ logic [1:0] cfg_tolerance;
+ logic cfg_irq_en;
+ logic frame_lost;
+ logic ready;
+
+
+ assign valid = wbs_cyc_i && wbs_stb_i;
+ assign rstrb = ~wbs_we_i;
+ assign addr = wbs_adr_i[4:2];
+ assign wbs_ack_o = ready;
+
+ wire [7:0] rx_frame_data = fifo_rx_rdata[7:0];
+ wire [7:0] rx_frame_addr = fifo_rx_rdata[15:8];
+ wire rx_frame_repeat = fifo_rx_rdata[16];
+ wire fifo_rx_available = (fifo_rx_occ > 0);
+
+ always @(negedge rst_n or posedge clk) begin
+ if (rst_n == 1'b0) begin
+ ready <= 1'b0;
+ wbs_dat_o <= 'h0;
+ cfg_tolerance <= 2'b01;
+ cfg_multiplier <= {PSIZE{1'b0}};
+ cfg_divider <= {PSIZE{1'b0}};
+ cfg_ir_en <= 1'b0;
+ cfg_ir_tx_en <= 1'b0;
+ cfg_ir_rx_en <= 1'b0;
+ cfg_repeat_en <= 1'b0;
+ cfg_irq_en <= 1'b0;
+ cfg_tx_polarity <= 1'b0;
+ cfg_rx_polarity <= 1'b0;
+ frame_lost <= 1'b0;
+ irq <= 1'b0;
+ fifo_tx_write <= 1'b0;
+ fifo_rx_read <= 1'b0;
+ end else begin
+
+ if (valid && !ready) begin
+
+ //Write
+ case (addr)
+ IR_CFG_CMD : begin
+ wbs_dat_o[31] <= cfg_ir_en ; if (wbs_sel_i[3] && wbs_we_i) cfg_ir_en <= wbs_dat_i[31];
+ wbs_dat_o[30] <= cfg_ir_tx_en ; if (wbs_sel_i[3] && wbs_we_i) cfg_ir_tx_en <= wbs_dat_i[30];
+ wbs_dat_o[29] <= cfg_ir_rx_en ; if (wbs_sel_i[3] && wbs_we_i) cfg_ir_rx_en <= wbs_dat_i[29];
+ wbs_dat_o[28] <= cfg_repeat_en ; if (wbs_sel_i[3] && wbs_we_i) cfg_repeat_en <= wbs_dat_i[28];
+ wbs_dat_o[27] <= cfg_irq_en ; if (wbs_sel_i[3] && wbs_we_i) cfg_irq_en <= wbs_dat_i[27];
+ wbs_dat_o[26] <= cfg_rx_polarity ; if (wbs_sel_i[3] && wbs_we_i) cfg_rx_polarity <= wbs_dat_i[26];
+ wbs_dat_o[25] <= cfg_tx_polarity ; if (wbs_sel_i[3] && wbs_we_i) cfg_tx_polarity <= wbs_dat_i[25];
+ wbs_dat_o[24] <= cfg_tolerance[1] ; if (wbs_sel_i[3] && wbs_we_i) cfg_tolerance[1]<= wbs_dat_i[24];
+ wbs_dat_o[23] <= cfg_tolerance[0] ; if (wbs_sel_i[2] && wbs_we_i) cfg_tolerance[0]<= wbs_dat_i[23];
+ wbs_dat_o[22:8] <= 'b0;
+ wbs_dat_o[7:4] <= fifo_tx_occ;
+ wbs_dat_o[3:0] <= fifo_rx_occ;
+ end
+ IR_CFG_MULTIPLIER : begin
+ wbs_dat_o <= cfg_multiplier;
+ if(wbs_sel_i[0] && wbs_we_i) cfg_multiplier[7:0] <= wbs_dat_i[7:0];
+ if(wbs_sel_i[1] && wbs_we_i) cfg_multiplier[15:8] <= wbs_dat_i[15:8];
+ if(wbs_sel_i[2] && wbs_we_i) cfg_multiplier[23:16] <= wbs_dat_i[23:16];
+ if(wbs_sel_i[3] && wbs_we_i) cfg_multiplier[31:24] <= wbs_dat_i[31:24];
+ end
+ IR_CFG_DIVIDER : begin
+ wbs_dat_o <= cfg_divider;
+ if(wbs_sel_i[0] && wbs_we_i) cfg_divider[7:0] <= wbs_dat_i[7:0];
+ if(wbs_sel_i[1] && wbs_we_i) cfg_divider[15:8] <= wbs_dat_i[15:8];
+ if(wbs_sel_i[2] && wbs_we_i) cfg_divider[23:16] <= wbs_dat_i[23:16];
+ if(wbs_sel_i[3] && wbs_we_i) cfg_divider[31:24] <= wbs_dat_i[31:24];
+ end
+ IR_CFG_RX_DATA : begin
+ if (fifo_rx_available == 1'b1 && !wbs_we_i) begin
+ wbs_dat_o[31] <= 1'b1;
+ wbs_dat_o[30] <= rx_frame_repeat;
+ wbs_dat_o[29] <= frame_lost;
+ wbs_dat_o[28:16] <= 13'b0;
+ wbs_dat_o[15:8] <= rx_frame_addr;
+ wbs_dat_o[7:0] <= rx_frame_data;
+ fifo_rx_read <= 1'b0;
+ end else begin
+ wbs_dat_o[31:0] <= 'b0;
+ end
+ end
+ IR_CFG_TX_DATA : begin
+ if (fifo_tx_full == 1'b0 && wbs_we_i) begin
+ fifo_tx_wdata <= wbs_dat_i[15:0];
+ fifo_tx_write <= 1'b1;
+ end
+ end
+ default: wbs_dat_o[31:0] <= 'b0;
+ endcase
+
+ ready <= 1'b1;
+ end else begin
+ fifo_tx_write <= 1'b0;
+ fifo_rx_read <= 1'b0;
+ ready <= 1'b0;
+ end
+
+ if ((rx_frame_new == 1'b1) && (fifo_rx_full == 1'b1)) begin
+ frame_lost <= 1'b1;
+ end else if (valid && !ready && rstrb && (addr == IR_CFG_RX_DATA)) begin
+ frame_lost <= 1'b0;
+ end
+
+ if (valid && !ready && rstrb && (addr == IR_CFG_RX_DATA) && fifo_rx_available) begin
+ fifo_rx_read <= 1'b1;
+ end else begin
+ fifo_rx_read <= 1'b0;
+ end
+
+ if ((cfg_irq_en == 1'b1) && (rx_frame_new == 1'b1)) begin
+ irq <= 1'b1;
+ end else begin
+ irq <= 1'b0;
+ end
+
+ end
+ end
+
+ always @(*) begin
+ case (cfg_tolerance)
+ 2'b00 : begin
+ reload_offset = {{(DSIZE-3){1'b0}}, 3'b001};
+ delay_mask = {{(DSIZE-3){1'b1}}, 3'b110};
+ end
+ 2'b01 : begin
+ reload_offset = {{(DSIZE-3){1'b0}}, 3'b010};
+ delay_mask = {{(DSIZE-3){1'b1}}, 3'b100};
+ end
+ default : begin
+ reload_offset = {{(DSIZE-3){1'b0}}, 3'b100};
+ delay_mask = {{(DSIZE-3){1'b1}}, 3'b000};
+ end
+ endcase
+ end
+
+endmodule
diff --git a/verilog/rtl/nec_ir/src/nec_ir_rx.sv b/verilog/rtl/nec_ir/src/nec_ir_rx.sv
new file mode 100644
index 0000000..0444ef8
--- /dev/null
+++ b/verilog/rtl/nec_ir/src/nec_ir_rx.sv
@@ -0,0 +1,144 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , <Julien OURY/Dinesh Annayya>
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+// and Dinesh Annayya <dinesh.annayya@gmail.com>
+//
+////////////////////////////////////////////////////////////////////////////
+/**********************************************************************
+
+ NEC IR RX
+
+ This file is part of the riscduino cores project
+ https://github.com/dineshannayya/riscduino.git
+
+ Description:
+ This block integrate
+ A. metastability_filter
+ B. pulse_filter
+ C. nec_ir_event_catcher
+
+ To Do:
+ nothing
+
+ Author(s):
+ - Julien OURY <julien.oury@outlook.fr>
+ - Dinesh Annayya <dinesh.annayya@gmail.com>
+
+ Revision :
+ 0.1 - 11 Dec 2022, Dinesh A
+ initial version picked from
+ https://github.com/JulienOury/ChristmasTreeController
+***************************************************************************/
+
+module nec_ir_rx #(
+ parameter NB_STAGES = 3 , // Number of metastability filter stages
+ parameter PSIZE = 32 , // Size of prescaler counter(bits)
+ parameter DSIZE = 32 , // Size of delay counter (bits)
+ parameter ASIZE = 3 // FIFO size (FIFO_size=(2**ASIZE)-1)
+)(
+
+ input logic rst_n , // Asynchronous reset (active low)
+ input logic clk , // Clock (rising edge)
+
+ input logic ir_rx ,
+ input logic tick8 ,
+ input logic cfg_receiver_en ,
+ input logic cfg_polarity ,
+ input logic cfg_repeat_en ,
+ input logic [DSIZE-1:0] reload_offset ,
+ input logic [DSIZE-1:0] delay_mask ,
+
+ output logic[16:0] fifo_rx_wdata ,
+ output logic fifo_rx_write
+
+);
+
+ logic [DSIZE-1:0] event_delay ;
+ wire ir_meta_f ;
+ wire ir_meta ;
+ wire value ;
+ wire new_sample ;
+ wire event_new ;
+ wire event_type ;
+ wire event_timeout ;
+ wire [7:0] frame_addr ;
+ wire [7:0] frame_data ;
+ wire frame_repeat ;
+
+ metastability_filter #(
+ .NB_STAGES(NB_STAGES)
+ ) i_metastability_filter (
+ .rst_n (rst_n ),
+ .clk (clk ),
+ .i_raw (ir_rx ),
+ .o_filtered (ir_meta_f )
+ );
+
+ // Invert polarity if needed
+ assign ir_meta = (cfg_polarity==0) ? ir_meta_f : ~ir_meta_f;
+
+ pulse_filter i_pulse_filter (
+ .rst_n (rst_n ),
+ .clk (clk ),
+ .clear_n (cfg_receiver_en),
+ .i_value (ir_meta ),
+ .i_valid (tick8 ),
+ .o_value (value ),
+ .o_valid (new_sample )
+ );
+
+ nec_ir_event_catcher #(
+ .DBITS(DSIZE)
+ ) i_event_catcher (
+ .rst_n (rst_n ),
+ .clk (clk ),
+ .clear_n (cfg_receiver_en ),
+ .reload_offset (reload_offset),
+ .i_value (value ),
+ .i_valid (new_sample ),
+ .event_new (event_new ),
+ .event_type (event_type ),
+ .event_delay (event_delay ),
+ .event_timeout (event_timeout)
+ );
+
+ nec_ir_frame_decoder #(
+ .DBITS(DSIZE)
+ ) i_frame_decoder (
+ .rst_n (rst_n ),
+ .clk (clk ),
+
+ .receiver_en (cfg_receiver_en ),
+ .repeat_en (cfg_repeat_en ),
+ .delay_mask (delay_mask ),
+
+ // Input event interface
+ .event_new (event_new ),
+ .event_type (event_type ),
+ .event_delay (event_delay ),
+ .event_timeout (event_timeout),
+
+ // Output frame interface
+ .frame_addr (frame_addr ),
+ .frame_data (frame_data ),
+ .frame_repeat (frame_repeat ),
+ .frame_write (fifo_rx_write )
+ );
+
+ assign fifo_rx_wdata = {frame_repeat, frame_addr, frame_data};
+
+
+endmodule
diff --git a/verilog/rtl/nec_ir/src/nec_ir_top.sv b/verilog/rtl/nec_ir/src/nec_ir_top.sv
new file mode 100644
index 0000000..badae10
--- /dev/null
+++ b/verilog/rtl/nec_ir/src/nec_ir_top.sv
@@ -0,0 +1,312 @@
+
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+/**********************************************************************
+
+ NEC IR Top
+
+ This file is part of the riscduino cores project
+ https://github.com/dineshannayya/riscduino.git
+
+ Description:
+ This block integrate
+ A. NEC IR Transmitter
+ B. NEC IR Reciver
+ C. Prescalar
+ D. Register Block
+ E. FIFO Block
+
+ To Do:
+ nothing
+
+ Author(s):
+ - Dinesh Annayya, dinesh.annayya@gmail.com
+
+ Revision :
+ 0.1 - 11 Dec 2022, Dinesh A
+ initial version
+ 0.2 - 13 Dec 2022, Dinesh A
+ A. Bug fix, Read access clearing the register content
+ B. FIFO Occpancy added
+ C. Support for IR Transmitter
+***************************************************************************/
+/*************************************************************************************
+Documentation Collection by Dinesh-A - dinesh.annayya@gmail.com
+Reference: https://techdocs.altium.com/display/FPGA/NEC+Infrared+Transmission+Protocol
+
+The NEC IR transmission protocol uses pulse distance encoding of the message bits. Each pulse burst (mark – RC transmitter ON) is
+562.5µs in length, at a carrier frequency of 38kHz (26.3µs). Logical bits are transmitted as follows:
+ Logical '0' – a 562.5µs pulse burst followed by a 562.5µs space, with a total transmit time of 1.125ms
+ Logical '1' – a 562.5µs pulse burst followed by a 1.6875ms space, with a total transmit time of 2.25ms
+
+
+When a key is pressed on the remote controller, the message transmitted consists of the following, in order:
+
+ * 9ms leading pulse burst (16 times the pulse burst length used for a logical data bit)
+ * 4.5ms space
+ * the 8-bit address for the receiving device
+ * the 8-bit logical inverse of the address
+ * the 8-bit command
+ * the 8-bit logical inverse of the command
+ * final 562.5µs pulse burst to signify the end of message transmission.
+
+Repeat Codes
+
+If the key on the remote controller is kept depressed, a repeat code will be issued, typically around 40ms after
+the pulse burst that signified the end of the message. A repeat code will continue to be sent out at 108ms intervals,
+until the key is finally released. The repeat code consists of the following, in order:
+
+ * 9ms leading pulse burst
+ * 2.25ms space
+ * 562.5µs pulse burst to mark the end of the space (and hence end of the transmitted repeat code).
+
+
+
+*************************************************************************************/
+
+module nec_ir_top #(
+ parameter NB_STAGES = 3 , // Number of metastability filter stages
+ parameter PSIZE = 32 , // Size of prescaler counter(bits)
+ parameter DSIZE = 32 , // Size of delay counter (bits)
+ parameter ASIZE = 3 , // FIFO size (FIFO_size=(2**ASIZE)-1)
+ parameter DP = 8 // FIFO DEPTH = 2**SIZE
+)(
+
+ input logic rst_n , // Asynchronous reset (active low)
+ input logic clk , // Clock (rising edge)
+
+ // Wishbone bus
+ input logic wbs_cyc_i , // Wishbone strobe/request
+ input logic wbs_stb_i , // Wishbone strobe/request
+ input logic [4:0] wbs_adr_i , // Wishbone address
+ input logic wbs_we_i , // Wishbone write (1:write, 0:read)
+ input logic [31:0] wbs_dat_i , // Wishbone data output
+ input logic [3:0] wbs_sel_i , // Wishbone byte enable
+ output logic [31:0] wbs_dat_o , // Wishbone data input
+ output logic wbs_ack_o , // Wishbone acknowlegement
+
+ input logic ir_rx ,
+ output logic ir_tx ,
+
+ output logic irq // Interrupt
+
+);
+
+//-----------------------------------------------
+// Reg Interface
+//------------------------------------------------
+ logic cfg_ir_en ;
+ logic cfg_ir_tx_en ;
+ logic cfg_ir_rx_en ;
+ logic cfg_repeat_en ;
+ logic cfg_tx_polarity ;
+ logic cfg_rx_polarity ;
+ logic [PSIZE-1:0] cfg_multiplier ;
+ logic [PSIZE-1:0] cfg_divider ;
+ logic [DSIZE-1:0] reload_offset ;
+ logic [DSIZE-1:0] delay_mask ;
+
+//---------------------------------------------
+// Prescal Output
+//----------------------------------------------
+ logic tick8 ; // 562.5µs/8 Pulse
+ logic tick1 ; // 562.5µs pulse
+
+//---------------------------------------------
+// FIFO RX I/F
+// <IR RECEIVER> => <RX FIFO> => WB
+//----------------------------------------------
+ logic fifo_rx_full ;
+ logic fifo_rx_empty ;
+ logic fifo_rx_write ;
+ logic [16:0] fifo_rx_wdata ;
+ logic [16:0] fifo_rx_rdata ;
+ logic fifo_rx_read ;
+ logic [ASIZE:0] fifo_rx_occ ;
+
+//---------------------------------------------
+// FIFO TX I/F
+// <WB> => <TX FIFO> => <IR Transmitter>
+//----------------------------------------------
+ logic fifo_tx_full ;
+ logic fifo_tx_empty ;
+ logic fifo_tx_write ;
+ logic [15:0] fifo_tx_wdata ;
+ logic [15:0] fifo_tx_rdata ;
+ logic fifo_tx_read ;
+ logic [ASIZE:0] fifo_tx_occ ;
+
+// --- Prescaler ---
+ prescaler #(
+ .BITS(PSIZE)
+ ) i_prescaler (
+ .rst_n (rst_n ),
+ .clk (clk ),
+ .clear_n (cfg_ir_en ),
+ .multiplier (cfg_multiplier ),
+ .divider (cfg_divider ),
+ .tick (tick8 )
+ );
+
+// --- Register ---
+
+ nec_ir_regs #(
+ .PSIZE(PSIZE),
+ .DSIZE(DSIZE),
+ .ASIZE(ASIZE)
+ ) i_ir_regs (
+ .rst_n (rst_n ),
+ .clk (clk ),
+
+ // Configuration
+ .cfg_ir_en (cfg_ir_en ),
+ .cfg_ir_tx_en (cfg_ir_tx_en ),
+ .cfg_ir_rx_en (cfg_ir_rx_en ),
+ .cfg_repeat_en (cfg_repeat_en ),
+ .cfg_tx_polarity (cfg_tx_polarity ),
+ .cfg_rx_polarity (cfg_rx_polarity ),
+ .cfg_multiplier (cfg_multiplier ),
+ .cfg_divider (cfg_divider ),
+ .reload_offset (reload_offset ),
+ .delay_mask (delay_mask ),
+
+ // Wishbone bus
+ .wbs_cyc_i (wbs_cyc_i ),
+ .wbs_stb_i (wbs_stb_i ),
+ .wbs_adr_i (wbs_adr_i ),
+ .wbs_we_i (wbs_we_i ),
+ .wbs_dat_i (wbs_dat_i ),
+ .wbs_sel_i (wbs_sel_i ),
+ .wbs_dat_o (wbs_dat_o ),
+ .wbs_ack_o (wbs_ack_o ),
+
+ // <IR RECEIVER> => <RX FIFO> => WB
+ .rx_frame_new (fifo_rx_write ),
+ .fifo_rx_full (fifo_rx_full ),
+ .fifo_rx_rdata (fifo_rx_rdata ),
+ .fifo_rx_read (fifo_rx_read ),
+ .fifo_rx_occ (fifo_rx_occ ),
+
+ // <WB> => <TX FIFO> => <IR Transmitter>
+ .fifo_tx_full (fifo_tx_full ),
+ .fifo_tx_wdata (fifo_tx_wdata ),
+ .fifo_tx_write (fifo_tx_write ),
+ .fifo_tx_occ (fifo_tx_occ ),
+
+ // Interrupt
+ .irq (irq )
+
+ );
+
+
+// --- RX FIFO ---
+
+ sync_fifo_occ #(
+ .DP(DP),
+ .WD(17),
+ .AW(ASIZE)
+ ) i_rx_fifo (
+ .reset_n (rst_n ),
+ .clk (clk ),
+ .sreset_n (cfg_ir_en ),
+ .wr_data (fifo_rx_wdata ),
+ .wr_en (fifo_rx_write ),
+ .full (fifo_rx_full ),
+ .empty (fifo_rx_empty ),
+ .rd_data (fifo_rx_rdata ),
+ .rd_en (fifo_rx_read ),
+ .occupancy (fifo_rx_occ )
+ );
+
+
+// --- IR Receiver ---
+
+nec_ir_rx #(
+ .NB_STAGES (NB_STAGES), // Number of metastability filter stages
+ .PSIZE (PSIZE ), // Size of prescaler counter(bits)
+ .DSIZE (DSIZE ), // Size of delay counter (bits)
+ .ASIZE (ASIZE ) // FIFO size (FIFO_size=(2**ASIZE)-1)
+) u_ir_rx (
+
+ .rst_n (rst_n ), // Asynchronous reset (active low)
+ .clk (clk ), // Clock (rising edge)
+
+ .ir_rx (ir_rx ),
+ .tick8 (tick8 ),
+ .cfg_receiver_en (cfg_ir_rx_en ),
+ .cfg_polarity (cfg_rx_polarity ),
+ .cfg_repeat_en (cfg_repeat_en ),
+ .reload_offset (reload_offset ),
+ .delay_mask (delay_mask ),
+ .fifo_rx_wdata (fifo_rx_wdata ),
+ .fifo_rx_write (fifo_rx_write )
+
+);
+
+// --- IR Transmitter ----
+
+// Div8 module
+nec_div8 u_div8 (
+ .rst_n (rst_n ), // Asynchronous reset (active low)
+ .clk (clk ), // Clock (rising edge)
+ .tick (tick8 ),
+ .tick_div8 (tick1 )
+ );
+
+
+nec_ir_tx u_ir_tx(
+ .rst_n (rst_n ), // Asynchronous reset (active low)
+ .clk (clk ), // Clock (rising edge)
+
+ // Configuration Input
+ .tx_en (cfg_ir_tx_en ), // Transmitter enable
+ .tx_event (tick1 ), // Transmit event at every 562.5µs
+ .p_polarity (cfg_tx_polarity ),
+
+ // FIFO Interface
+ .fifo_valid (!fifo_tx_empty ),
+ .fifo_tx_rdata (fifo_tx_rdata ),
+ .fifo_read (fifo_tx_read ),
+
+ // To Pad
+ .ir_tx (ir_tx )
+
+);
+
+// --- TX FIFO ---
+
+ sync_fifo_occ #(
+ .DP(DP),
+ .WD(16),
+ .AW(ASIZE)
+ ) i_tx_fifo (
+ .reset_n (rst_n ),
+ .clk (clk ),
+ .sreset_n (cfg_ir_en ),
+ .wr_data (fifo_tx_wdata ),
+ .wr_en (fifo_tx_write ),
+ .full (fifo_tx_full ),
+ .empty (fifo_tx_empty ),
+ .rd_data (fifo_tx_rdata ),
+ .rd_en (fifo_tx_read ),
+ .occupancy (fifo_tx_occ )
+ );
+
+
+endmodule
diff --git a/verilog/rtl/nec_ir/src/nec_ir_tx.sv b/verilog/rtl/nec_ir/src/nec_ir_tx.sv
new file mode 100644
index 0000000..077e6e3
--- /dev/null
+++ b/verilog/rtl/nec_ir/src/nec_ir_tx.sv
@@ -0,0 +1,212 @@
+
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+/**********************************************************************
+
+ NEC IR Transmitter
+
+ This file is part of the riscduino cores project
+ https://github.com/dineshannayya/riscduino.git
+
+ To Do:
+ nothing
+
+ Author(s):
+ - Dinesh Annayya, dinesh.annayya@gmail.com
+
+ Revision :
+ 0.1 - 12 Dec 2022, Dinesh A
+ initial version
+***************************************************************************/
+
+/************************************************
+https://techdocs.altium.com/display/FPGA/NEC+Infrared+Transmission+Protocol
+The NEC IR transmission protocol uses pulse distance encoding of the message bits. Each pulse burst (mark – RC transmitter ON) is 562.5µs in length,
+at a carrier frequency of 38kHz (26.3µs). Logical bits are transmitted as follows:
+
+ Logical '0' – a 562.5µs pulse burst followed by a 562.5µs space, with a total transmit time of 1.125ms
+ Logical '1' – a 562.5µs pulse burst followed by a 1.6875ms space, with a total transmit time of 2.25ms
+
+When a key is pressed on the remote controller, the message transmitted consists of the following, in order:
+
+ * 9ms leading pulse burst (16 times the pulse burst length used for a logical data bit)
+ * 4.5ms space
+ * the 8-bit address for the receiving device
+ * the 8-bit logical inverse of the address
+ * the 8-bit command
+ * the 8-bit logical inverse of the command
+ * final 562.5µs pulse burst to signify the end of message transmission.
+
+*************************************************************************************************************/
+
+
+module nec_ir_tx (
+ input logic rst_n , // Asynchronous reset (active low)
+ input logic clk , // Clock (rising edge)
+
+ // Configuration Input
+ input logic tx_en , // Transmitter enable
+ input logic tx_event , // Transmit event at every 562.5µs
+ input logic p_polarity ,
+
+ // FIFO Interface
+ input logic fifo_valid ,
+ input logic [15:0] fifo_tx_rdata , // Frame address
+ output logic fifo_read ,
+
+ // To Pad
+ output logic ir_tx
+
+);
+
+
+// FSM STATE
+parameter S_IDLE = 3'b000;
+parameter S_START_BURST = 3'b001;
+parameter S_START_SPACE = 3'b010;
+parameter S_DATA_BURST = 3'b011;
+parameter S_DATA_SPACE = 3'b100;
+parameter S_STOP = 3'b101;
+
+// Data Phase
+parameter P_TX_ADDR = 2'b00;
+parameter P_TX_INV_ADDR = 2'b01;
+parameter P_TX_DATA = 2'b10;
+parameter P_TX_INV_DATA = 2'b11;
+
+logic [7:0] tx_data;
+logic [2:0] s_state;
+logic [1:0] s_data_phase;
+logic [3:0] tick_cnt;
+logic [2:0] bit_cnt;
+
+wire [7:0] addr_cmd = fifo_tx_rdata[15:8];
+wire [7:0] data_cmd = fifo_tx_rdata[7:0];
+
+
+assign tx_data = (s_data_phase == P_TX_ADDR) ? addr_cmd : // Transmit Address
+ (s_data_phase == P_TX_INV_ADDR) ? ~addr_cmd : // logical inverse of the address
+ (s_data_phase == P_TX_DATA) ? data_cmd : // Transmit Data
+ (s_data_phase == P_TX_INV_DATA) ? ~data_cmd : // logical inverse of the data
+ 'h0;
+
+
+always @(negedge rst_n or posedge clk) begin
+ if (rst_n == 1'b0) begin
+ ir_tx <= 0;
+ tick_cnt <= 0;
+ bit_cnt <= 0;
+ fifo_read <= 0;
+ s_data_phase <= P_TX_ADDR;
+ s_state <= S_IDLE;
+ end else begin
+ if (tx_en == 1'b0) begin
+ s_state <= S_IDLE;
+ ir_tx <= ~p_polarity;
+ tick_cnt <= 0;
+ bit_cnt <= 0;
+ fifo_read <= 0;
+ end else if (tx_event == 1'b1) begin
+ case(s_state )
+ S_IDLE: begin
+ if(fifo_valid == 1'b1) begin
+ s_state <= S_START_BURST;
+ ir_tx <= p_polarity;
+ tick_cnt <= 0;
+ end else begin
+ ir_tx <= ~p_polarity;
+ end
+ end
+ // 9ms leading pulse burst (16 times the pulse burst length used for a logical data bit)
+ S_START_BURST: begin
+ if(tick_cnt == 15) begin
+ ir_tx <= ~p_polarity;
+ s_state <= S_START_SPACE;
+ tick_cnt <= 0;
+ end else begin
+ tick_cnt <= tick_cnt + 1;
+ end
+ end
+ // 4.5ms space
+ S_START_SPACE: begin
+ if(tick_cnt == 7) begin
+ ir_tx <= p_polarity;
+ s_state <= S_DATA_BURST;
+ tick_cnt <= 0;
+ bit_cnt <= 0;
+ s_data_phase <= P_TX_ADDR;
+ end else begin
+ tick_cnt <= tick_cnt + 1;
+ end
+ end
+ S_DATA_BURST: begin
+ ir_tx <= ~p_polarity;
+ s_state <= S_DATA_SPACE;
+ tick_cnt <= 0;
+ end
+ S_DATA_SPACE: begin
+ //Logical '0' – a 562.5µs pulse burst followed by a 562.5µs space, with a total transmit time of 1.125ms
+ //Logical '1' – a 562.5µs pulse burst followed by a 1.6875ms space, with a total transmit time of 2.25ms
+ if(tx_data[bit_cnt] == 1'b1 && tick_cnt == 2) begin
+ ir_tx <= p_polarity;
+ if(bit_cnt == 7) begin
+ case(s_data_phase)
+ P_TX_ADDR: begin s_data_phase <= P_TX_INV_ADDR; s_state <= S_DATA_BURST; end
+ P_TX_INV_ADDR: begin s_data_phase <= P_TX_DATA; s_state <= S_DATA_BURST; end
+ P_TX_DATA: begin s_data_phase <= P_TX_INV_DATA; s_state <= S_DATA_BURST; end
+ P_TX_INV_DATA: begin fifo_read <= 1; s_state <= S_STOP; end
+ endcase
+ bit_cnt <= 0;
+ end else begin
+ bit_cnt <= bit_cnt+1;
+ s_state <= S_DATA_BURST;
+ end
+ end else if(tx_data[bit_cnt] == 1'b0 && tick_cnt == 0) begin
+ ir_tx <= p_polarity;
+ if(bit_cnt == 7) begin
+ case(s_data_phase)
+ P_TX_ADDR: begin s_data_phase <= P_TX_INV_ADDR; s_state <= S_DATA_BURST; end
+ P_TX_INV_ADDR: begin s_data_phase <= P_TX_DATA; s_state <= S_DATA_BURST; end
+ P_TX_DATA: begin s_data_phase <= P_TX_INV_DATA; s_state <= S_DATA_BURST; end
+ P_TX_INV_DATA: begin fifo_read <= 1; s_state <= S_STOP; end
+ endcase
+ bit_cnt <= 0;
+ end else begin
+ bit_cnt <= bit_cnt+1;
+ s_state <= S_DATA_BURST;
+ end
+ end else begin
+ tick_cnt <= tick_cnt+1;
+ end
+ end
+ S_STOP: begin
+ ir_tx <= ~p_polarity;
+ fifo_read <= 0;
+ s_state <= S_IDLE;
+ end
+ default : s_state <= S_IDLE;
+ endcase
+ end else begin
+ fifo_read <= 0;
+ end
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/peripheral/src/peri_top.sv b/verilog/rtl/peripheral/src/peri_top.sv
new file mode 100755
index 0000000..8fadc5d
--- /dev/null
+++ b/verilog/rtl/peripheral/src/peri_top.sv
@@ -0,0 +1,224 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Peripheral Top ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// Hold the All the Misc IP Integration ////
+//// A. dig2ang ////
+//// B. RTC ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 07 Dec 2022, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+
+`include "user_params.svh"
+module peri_top (
+ `ifdef USE_POWER_PINS
+ input logic vccd1,// User area 1 1.8V supply
+ input logic vssd1,// User area 1 digital ground
+ `endif
+ // clock skew adjust
+ input logic [3:0] cfg_cska_peri,
+ input logic wbd_clk_int,
+ output logic wbd_clk_peri,
+
+ // System Signals
+ // Inputs
+ input logic mclk,
+ input logic s_reset_n , // soft reset
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [10:0] reg_addr,
+ input logic [31:0] reg_wdata,
+ input logic [3:0] reg_be,
+
+ // Outputs
+ output logic [31:0] reg_rdata,
+ output logic reg_ack,
+
+ // RTC Clock Domain
+ input logic rtc_clk,
+ output logic rtc_intr,
+
+ output logic inc_time_s,
+ output logic inc_date_d,
+
+ // IR Receiver I/F
+ input logic ir_rx,
+ output logic ir_tx,
+ output logic ir_intr,
+
+ // DAC Config
+ output logic [7:0] cfg_dac0_mux_sel,
+ output logic [7:0] cfg_dac1_mux_sel,
+ output logic [7:0] cfg_dac2_mux_sel,
+ output logic [7:0] cfg_dac3_mux_sel
+
+ );
+
+
+
+logic s_reset_ssn; // Sync Reset
+
+
+//----------------------------------------
+// Register Response Path Mux
+// --------------------------------------
+
+logic [31:0] reg_d2a_rdata;
+logic reg_d2a_ack;
+logic reg_d2a_cs;
+
+logic [31:0] reg_rtc_rdata;
+logic reg_rtc_ack;
+logic reg_rtc_cs;
+
+logic [31:0] reg_ir_rdata;
+logic reg_ir_ack;
+logic reg_ir_cs;
+
+assign reg_rdata = (reg_addr[10:7] == `SEL_D2A) ? reg_d2a_rdata :
+ (reg_addr[10:7] == `SEL_RTC) ? reg_rtc_rdata :
+ (reg_addr[10:7] == `SEL_IR) ? reg_ir_rdata :
+ 'h0;
+assign reg_ack = (reg_addr[10:7] == `SEL_D2A) ? reg_d2a_ack :
+ (reg_addr[10:7] == `SEL_RTC) ? reg_rtc_ack :
+ (reg_addr[10:7] == `SEL_IR) ? reg_ir_ack :
+ 1'b0;
+assign reg_d2a_cs = (reg_addr[10:7] == `SEL_D2A) ? reg_cs : 1'b0;
+assign reg_rtc_cs = (reg_addr[10:7] == `SEL_RTC) ? reg_cs : 1'b0;
+assign reg_ir_cs = (reg_addr[10:7] == `SEL_IR) ? reg_cs : 1'b0;
+
+
+// peri clock skew control
+clk_skew_adjust u_skew_peri
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_peri ),
+ .clk_out (wbd_clk_peri )
+ );
+
+reset_sync u_rst_sync (
+ .scan_mode (1'b0 ),
+ .dclk (mclk ), // Destination clock domain
+ .arst_n (s_reset_n ), // active low async reset
+ .srst_n (s_reset_ssn )
+ );
+
+
+//-----------------------------------------------------------------------
+// Digital To Analog Register
+//-----------------------------------------------------------------------
+dig2ana_reg u_d2a(
+ // System Signals
+ // Inputs
+ .mclk ( mclk ),
+ .h_reset_n (s_reset_ssn ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_d2a_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[5:2] ),
+ .reg_wdata (reg_wdata[31:0] ),
+ .reg_be (reg_be[3:0] ),
+
+ // Outputs
+ .reg_rdata (reg_d2a_rdata ),
+ .reg_ack (reg_d2a_ack ),
+
+ .cfg_dac0_mux_sel (cfg_dac0_mux_sel ),
+ .cfg_dac1_mux_sel (cfg_dac1_mux_sel ),
+ .cfg_dac2_mux_sel (cfg_dac2_mux_sel ),
+ .cfg_dac3_mux_sel (cfg_dac3_mux_sel )
+ );
+
+//-----------------------------------------------------------------------
+// RTC
+//-----------------------------------------------------------------------
+rtc_top u_rtc(
+ // System Signals
+ // Inputs
+ .sys_clk ( mclk ),
+ .rst_n (s_reset_ssn ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_rtc_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[4:0] ),
+ .reg_wdata (reg_wdata[31:0] ),
+ .reg_be (reg_be[3:0] ),
+
+ // Outputs
+ .reg_rdata (reg_rtc_rdata ),
+ .reg_ack (reg_rtc_ack ),
+
+ .rtc_clk (rtc_clk ),
+ .rtc_intr (rtc_intr ),
+
+ .inc_date_d (inc_date_d ),
+ .inc_time_s (inc_time_s )
+
+ );
+
+//--------------------------------------------------------------------------
+// IR Receiver
+//--------------------------------------------------------------------------
+
+nec_ir_top i_ir (
+
+ .rst_n (s_reset_ssn ),
+ .clk (mclk ),
+
+ // Wishbone bus
+ .wbs_cyc_i (reg_ir_cs ),
+ .wbs_stb_i (reg_ir_cs ),
+ .wbs_adr_i (reg_addr[4:0] ),
+ .wbs_we_i (reg_wr ),
+ .wbs_dat_i (reg_wdata ),
+ .wbs_sel_i (reg_be ),
+ .wbs_dat_o (reg_ir_rdata ),
+ .wbs_ack_o (reg_ir_ack ),
+
+ .ir_rx (ir_rx ),
+ .ir_tx (ir_tx ),
+
+ .irq (ir_intr )
+
+);
+
+endmodule
+
+
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv
index 4262fc4..6557c0c 100644
--- a/verilog/rtl/pinmux/src/glbl_reg.sv
+++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -94,6 +94,8 @@
input logic usb_intr ,
input logic i2cm_intr ,
input logic pwm_intr ,
+ input logic rtc_intr ,
+ input logic ir_intr ,
output logic [15:0] cfg_riscv_ctrl ,
output logic [31:0] cfg_multi_func_sel ,// multifunction pins
@@ -136,6 +138,7 @@
logic [31:0] reg_6; //
logic [31:0] reg_7; //
logic [31:0] reg_8; //
+logic [31:0] reg_9; // Random Number
logic [31:0] reg_12; // Latched Strap
logic [31:0] reg_13; // Strap Sticky
logic [31:0] reg_14; // System Strap
@@ -370,23 +373,34 @@
logic usb_intr_s,usb_intr_ss; // Usb Interrupt Double Sync
logic i2cm_intr_s,i2cm_intr_ss; // I2C Interrupt Double Sync
+logic rtc_intr_s,rtc_intr_ss;
+logic ir_intr_s,ir_intr_ss;
always @ (posedge mclk or negedge s_reset_n)
begin
if (s_reset_n == 1'b0) begin
- usb_intr_s <= 'h0;
- usb_intr_ss <= 'h0;
- i2cm_intr_s <= 'h0;
- i2cm_intr_ss <= 'h0;
+ usb_intr_s <= 'h0;
+ usb_intr_ss <= 'h0;
+ i2cm_intr_s <= 'h0;
+ i2cm_intr_ss <= 'h0;
+ rtc_intr_s <= 'h0;
+ rtc_intr_ss <= 'h0;
+ ir_intr_s <= 'h0;
+ ir_intr_ss <= 'h0;
end else begin
usb_intr_s <= usb_intr;
usb_intr_ss <= usb_intr_s;
i2cm_intr_s <= i2cm_intr;
i2cm_intr_ss <= i2cm_intr_s;
+ rtc_intr_s <= rtc_intr;
+ rtc_intr_ss <= rtc_intr_s;
+
+ ir_intr_s <= ir_intr;
+ ir_intr_ss <= ir_intr_s;
end
end
-wire [31:0] hware_intr_req = {gpio_intr[31:8], 2'b0,pwm_intr,usb_intr_ss, i2cm_intr_ss,timer_intr[2:0]};
+wire [31:0] hware_intr_req = {gpio_intr[31:8], ir_intr_ss,rtc_intr_ss,pwm_intr,usb_intr_ss, i2cm_intr_ss,timer_intr[2:0]};
generic_intr_stat_reg #(.WD(32),
.RESET_DEFAULT(0)) u_reg4 (
@@ -487,6 +501,16 @@
assign cfg_dc_trim = reg_8[25:0];
+//------------------------------------------
+// reg_9: Random Number Generator
+//------------------------------------------
+pseudorandom u_random (
+ .rst_n ( s_reset_n ),
+ .clk ( mclk ),
+ .next ( reg_ack ),
+ .random ( reg_9 )
+);
+
//-------------------------------------------------
// Strap control
@@ -668,7 +692,7 @@
5'b00110 : reg_out [31:0] = reg_6 ;
5'b00111 : reg_out [31:0] = reg_7 ;
5'b01000 : reg_out [31:0] = reg_8 ;
- 5'b01001 : reg_out [31:0] = 'h0 ;
+ 5'b01001 : reg_out [31:0] = reg_9 ;
5'b01010 : reg_out [31:0] = 'h0 ;
5'b01011 : reg_out [31:0] = 'h0 ;
5'b01100 : reg_out [31:0] = reg_12 ;
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index f8143ed..20342b5 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -52,12 +52,12 @@
* Pin-7 VCC -
* Pin-8 GND -
* Pin-9 20 PB6/WS[1]/XTAL1/TOSC1 digital_io[11]
-* Pin-10 21 PB7/WS[1]/XTAL2/TOSC2 digital_io[12]
+* Pin-10 21 PB7/WS[1]/XTAL2/TOSC2/IR-RX digital_io[12]
* Pin-11 5 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 strap[0] digital_io[13]
* Pin-12 6 PD6/WS[2]/SS[2]/OC0A(PWM2)/AIN0 strap[1] digital_io[14]/analog_io[2]
-* Pin-13 7 PD7/WS[2]/A1N1 strap[2] digital_io[15]/analog_io[3]
+* Pin-13 7 PD7/WS[2]/A1N1/IR-TX strap[2] digital_io[15]/analog_io[3]
* Pin-14 8 PB0/WS[2]/CLKO/ICP1 strap[3] digital_io[16]
-* Pin-15 9 PB1/WS[3]/SS[1]OC1A(PWM3) strap[4] digital_io[17]
+* Pin-15 9 PB1/WS[3]/SS[1]/OC1A(PWM3) strap[4] digital_io[17]
* Pin-16 10 PB2/WS[3]/SS[0]/OC1B(PWM4) strap[5] digital_io[18]
* Pin-17 11 PB3/WS[3]/MOSI/OC2A(PWM5) strap[6] digital_io[19]
* Pin-18 12 PB4/WS[3]/MISO strap[7] digital_io[20]
@@ -65,8 +65,8 @@
* Pin-20 AVCC -
* Pin-21 AREF analog_io[10]
* Pin-22 GND -
-* Pin-23 14 PC0/ADC0 digital_io[22]/analog_io[11]
-* Pin-24 15 PC1/ADC1 digital_io[23]/analog_io[12]
+* Pin-23 14 PC0/ADC0 digital_io[22]/analog_io[11]
+* Pin-24 15 PC1/ADC1 digital_io[23]/analog_io[12]
* Pin-25 16 PC2/usb_dp/ADC2 digital_io[24]/analog_io[13]
* Pin-26 17 PC3/usb_dn/ADC3 digital_io[25]/analog_io[14]
* Pin-27 18 PC4/ADC4/SDA digital_io[26]/analog_io[15]
@@ -168,7 +168,11 @@
// WS_281X TXD Port
input logic [3:0] ws_txd,
- input logic dbg_clk_mon
+ input logic dbg_clk_mon,
+
+ // IR Receiver
+ output logic ir_rx,
+ input logic ir_tx
);
@@ -189,7 +193,6 @@
//--------------------------------------------------
assign pad_strap_in = {digital_io_in[36:29],digital_io_in[20:13] };
-assign xtal_clk = digital_io_in[11];
// GPIO to PORT Mapping
assign pad_gpio_in[7:0] = port_a_in;
@@ -210,6 +213,7 @@
wire [3:0] cfg_spim_cs_enb = cfg_multi_func_sel[14:11];
wire cfg_i2cm_enb = cfg_multi_func_sel[15];
wire cfg_usb_enb = cfg_multi_func_sel[16];
+wire cfg_ir_tx_enb = cfg_multi_func_sel[17]; // NEC IR TX Enable
wire cfg_muart_enb = cfg_multi_func_sel[31]; // 1 - uart master enable,
wire [7:0] cfg_port_a_dir_sel = cfg_gpio_dir_sel[7:0];
@@ -242,6 +246,8 @@
i2cm_data_i= 'h0;
i2cm_clk_i = 'h0;
uartm_rxd = 'b1;
+ xtal_clk = 'b0;
+ ir_rx = 'b0;
//Pin-1 PC6/RESET* digital_io[5]
port_c_in[6] = digital_io_in[5];
@@ -270,9 +276,11 @@
//Pin-9 PB6/XTAL1/TOSC1 digital_io[11]
port_b_in[6] = digital_io_in[11];
+ xtal_clk = digital_io_in[11];
- // Pin-10 PB7/XTAL2/TOSC2 digital_io[12]
+ // Pin-10 PB7/XTAL2/TOSC2/IR-RX digital_io[12]
port_b_in[7] = digital_io_in[12];
+ ir_rx = digital_io_in[12];
//Pin-11 PD5/OC0B(PWM1)/T1 digital_io[13]
port_d_in[5] = digital_io_in[13];
@@ -280,7 +288,7 @@
//Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[14] /analog_io[2]
port_d_in[6] = digital_io_in[14];
- //Pin-13 PD7/A1N1 digital_io[15]/analog_io[3]
+ //Pin-13 PD7/A1N1/IR-RX digital_io[15]/analog_io[3]
port_d_in[7] = digital_io_in[15];
//Pin-14 PB0/CLKO/ICP1 digital_io[16]
@@ -393,8 +401,9 @@
else if(cfg_port_d_dir_sel[6]) digital_io_out[14] = port_d_out[6];
- //Pin-13 PD7/A1N1/WS[2] digital_io[15]/analog_io[3]
- if(cfg_port_d_port_type[7]) digital_io_out[15] = ws_txd[2];
+ //Pin-13 PD7/A1N1/WS[2]/IR-TX digital_io[15]/analog_io[3]
+ if(cfg_ir_tx_enb) digital_io_out[15] = ir_tx;
+ else if(cfg_port_d_port_type[7])digital_io_out[15] = ws_txd[2];
else if(cfg_port_d_dir_sel[7]) digital_io_out[15] = port_d_out[7];
//Pin-14 PB0/CLKO/WS[2]/ICP1 digital_io[16]
@@ -404,7 +413,7 @@
//Pin-15 PB1/SS[1]/WS[3]/OC1A(PWM3) digital_io[17]
if(cfg_pwm_enb[3]) digital_io_out[17] = pwm_wfm[3];
else if(cfg_spim_cs_enb[1]) digital_io_out[17] = spim_ssn[1];
- else if(cfg_port_b_port_type[1])digital_io_out[17] = ws_txd[3];
+ else if(cfg_port_b_port_type[1])digital_io_out[17] = ws_txd[3];
else if(cfg_port_b_dir_sel[1]) digital_io_out[17] = port_b_out[1];
//Pin-16 PB2/SS[0]/WS[3]/OC1B(PWM4) digital_io[18]
@@ -476,96 +485,96 @@
digital_io_oen = 38'h3F_FFFF_FFFF;
//Pin-1 PC6/WS[0]/RESET* digital_io[5]
- if(cfg_port_c_port_type[6]) digital_io_oen[5] = 1'b1;
+ if(cfg_port_c_port_type[6]) digital_io_oen[5] = 1'b0;
else if(cfg_port_c_dir_sel[6]) digital_io_oen[5] = 1'b0;
//Pin-2 PD0/WS[0]/MRXD/RXD[0] digital_io[6]
if (cfg_muart_enb) digital_io_oen[6] = 1'b1;
else if(cfg_uart_enb[0]) digital_io_oen[6] = 1'b1;
- else if(cfg_port_d_port_type[0])digital_io_oen[6] = 1'b1;
+ else if(cfg_port_d_port_type[0])digital_io_oen[6] = 1'b0;
else if(cfg_port_d_dir_sel[0]) digital_io_oen[6] = 1'b0;
//Pin-3 PD1/WS[0]/MTXD/TXD[0] digital_io[7]
if (cfg_muart_enb) digital_io_oen[7] = 1'b0;
else if(cfg_uart_enb[0]) digital_io_oen[7] = 1'b0;
- else if(cfg_port_d_port_type[1])digital_io_oen[7] = 1'b1;
+ else if(cfg_port_d_port_type[1])digital_io_oen[7] = 1'b0;
else if(cfg_port_d_dir_sel[1]) digital_io_oen[7] = 1'b0;
//Pin-4 PD2/WS[0]/RXD[1]/INT0 digital_io[8]
if(cfg_int_enb[0]) digital_io_oen[8] = 1'b1;
- else if(cfg_port_d_port_type[2])digital_io_oen[8] = 1'b1;
+ else if(cfg_port_d_port_type[2])digital_io_oen[8] = 1'b0;
else if(cfg_port_d_dir_sel[2]) digital_io_oen[8] = 1'b0;
//Pin-5 PD3/WS[1]/INT1/OC2B(PWM0) digital_io[9]
if(cfg_pwm_enb[0]) digital_io_oen[9] = 1'b0;
else if(cfg_int_enb[1]) digital_io_oen[9] = 1'b1;
- else if(cfg_port_d_port_type[3])digital_io_oen[9] = 1'b1;
+ else if(cfg_port_d_port_type[3])digital_io_oen[9] = 1'b0;
else if(cfg_port_d_dir_sel[3]) digital_io_oen[9] = 1'b0;
//Pin-6 PD4/WS[1]/TXD[1] digital_io[10]
if (cfg_uart_enb[1]) digital_io_oen[10] = 1'b0;
- else if(cfg_port_d_port_type[4])digital_io_oen[10] = 1'b1;
+ else if(cfg_port_d_port_type[4])digital_io_oen[10] = 1'b0;
else if(cfg_port_d_dir_sel[4]) digital_io_oen[10] = 1'b0;
//Pin-9 PB6/WS[1]/XTAL1/TOSC1 digital_io[11]
- if (cfg_uart_enb[1]) digital_io_oen[11] = 1'b1;
- else if(cfg_port_b_port_type[6]) digital_io_oen[11] = 1'b1;
+ if(cfg_port_b_port_type[6]) digital_io_oen[11] = 1'b0;
else if(cfg_port_b_dir_sel[6]) digital_io_oen[11] = 1'b0;
// Pin-10 PB7/WS[1]/XTAL2/TOSC2 digital_io[12]
- if(cfg_port_b_port_type[7]) digital_io_oen[12] = 1'b1;
+ if(cfg_port_b_port_type[7]) digital_io_oen[12] = 1'b0;
else if(cfg_port_b_dir_sel[7]) digital_io_oen[12] = 1'b0;
//Pin-11 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 digital_io[13]
if(cfg_strap_pad_ctrl) digital_io_oen[13] = 1'b1;
else if(cfg_pwm_enb[1]) digital_io_oen[13] = 1'b0;
else if(cfg_spim_cs_enb[3]) digital_io_oen[13] = 1'b0;
- else if(cfg_port_d_port_type[5])digital_io_oen[13] = 1'b1;
+ else if(cfg_port_d_port_type[5])digital_io_oen[13] = 1'b0;
else if(cfg_port_d_dir_sel[5]) digital_io_oen[13] = 1'b0;
//Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[14] /analog_io[2]
if(cfg_strap_pad_ctrl) digital_io_oen[14] = 1'b1;
else if(cfg_pwm_enb[2]) digital_io_oen[14] = 1'b0;
else if(cfg_spim_cs_enb[2]) digital_io_oen[14] = 1'b0;
- else if(cfg_port_d_port_type[6])digital_io_oen[14] = 1'b1;
+ else if(cfg_port_d_port_type[6])digital_io_oen[14] = 1'b0;
else if(cfg_port_d_dir_sel[6]) digital_io_oen[14] = 1'b0;
- //Pin-13 PD7/WS[2]/A1N1 digital_io[15]/analog_io[3]
+ //Pin-13 PD7/A1N1/WS[2]/IR-TX digital_io[15]/analog_io[3]
if(cfg_strap_pad_ctrl) digital_io_oen[15] = 1'b1;
- else if(cfg_port_d_port_type[7])digital_io_oen[15] = 1'b1;
+ else if(cfg_ir_tx_enb) digital_io_oen[15] = 1'b0;
+ else if(cfg_port_d_port_type[7])digital_io_oen[15] = 1'b0;
else if(cfg_port_d_dir_sel[7]) digital_io_oen[15] = 1'b0;
//Pin-14 PB0/WS[2]/CLKO/ICP1 digital_io[16]
if(cfg_strap_pad_ctrl) digital_io_oen[16] = 1'b1;
- else if(cfg_port_b_port_type[0])digital_io_oen[16] = 1'b1;
+ else if(cfg_port_b_port_type[0])digital_io_oen[16] = 1'b0;
else if(cfg_port_b_dir_sel[0]) digital_io_oen[16] = 1'b0;
//Pin-15 PB1/WS[3]/SS[1]/OC1A(PWM3) digital_io[17]
if(cfg_strap_pad_ctrl) digital_io_oen[17] = 1'b1;
else if(cfg_pwm_enb[3]) digital_io_oen[17] = 1'b0;
else if(cfg_spim_cs_enb[1]) digital_io_oen[17] = 1'b0;
- else if(cfg_port_b_port_type[1])digital_io_oen[17] = 1'b1;
+ else if(cfg_port_b_port_type[1])digital_io_oen[17] = 1'b0;
else if(cfg_port_b_dir_sel[1]) digital_io_oen[17] = 1'b0;
//Pin-16 PB2/WS[3]/SS[0]/OC1B(PWM4) digital_io[18]
if(cfg_strap_pad_ctrl) digital_io_oen[18] = 1'b1;
else if(cfg_pwm_enb[4]) digital_io_oen[18] = 1'b0;
else if(cfg_spim_cs_enb[0]) digital_io_oen[18] = 1'b0;
- else if(cfg_port_b_port_type[2])digital_io_oen[18] = 1'b1;
+ else if(cfg_port_b_port_type[2])digital_io_oen[18] = 1'b0;
else if(cfg_port_b_dir_sel[2]) digital_io_oen[18] = 1'b0;
//Pin-17 PB3/WS[3]/MOSI/OC2A(PWM5) digital_io[19]
if(cfg_strap_pad_ctrl) digital_io_oen[19] = 1'b1;
else if(cfg_spim_enb) digital_io_oen[19] = 1'b1; // SPIM MOSI (Input)
else if(cfg_pwm_enb[5]) digital_io_oen[19] = 1'b0;
- else if(cfg_port_b_port_type[3])digital_io_oen[19] = 1'b1;
+ else if(cfg_port_b_port_type[3])digital_io_oen[19] = 1'b0;
else if(cfg_port_b_dir_sel[3]) digital_io_oen[19] = 1'b0;
else if(spis_boot) digital_io_oen[19] = 1'b0; // SPIS MISO (Output)
//Pin-18 PB4/WS[3]/MISO digital_io[20]
if(cfg_strap_pad_ctrl) digital_io_oen[20] = 1'b1;
else if(cfg_spim_enb) digital_io_oen[20] = 1'b0; // SPIM MISO (Output)
- else if(cfg_port_b_port_type[4])digital_io_oen[20] = 1'b1;
+ else if(cfg_port_b_port_type[4])digital_io_oen[20] = 1'b0;
else if(cfg_port_b_dir_sel[4]) digital_io_oen[20] = 1'b0;
else if(spis_boot) digital_io_oen[20] = 1'b1; // SPIS MOSI (Input)
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
index 58419e2..ef2fa83 100755
--- a/verilog/rtl/pinmux/src/pinmux_top.sv
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -119,7 +119,7 @@
// Reg Bus Interface Signal
input logic reg_cs,
input logic reg_wr,
- input logic [9:0] reg_addr,
+ input logic [10:0] reg_addr,
input logic [31:0] reg_wdata,
input logic [3:0] reg_be,
@@ -198,13 +198,25 @@
output logic[25:0] cfg_dc_trim , // External trim for DCO mode
output logic pll_ref_clk , // Input oscillator to match
-
- // DAC Config
- output logic [7:0] cfg_dac0_mux_sel ,
- output logic [7:0] cfg_dac1_mux_sel ,
- output logic [7:0] cfg_dac2_mux_sel ,
- output logic [7:0] cfg_dac3_mux_sel
+ // Peripheral Reg Bus Interface Signal
+ output logic reg_peri_cs,
+ output logic reg_peri_wr,
+ output logic [10:0] reg_peri_addr,
+ output logic [31:0] reg_peri_wdata,
+ output logic [3:0] reg_peri_be,
+ // Input
+ input logic [31:0] reg_peri_rdata,
+ input logic reg_peri_ack,
+
+ input logic rtc_intr,
+
+ // IR Receiver I/F
+ output logic ir_rx,
+ input logic ir_tx,
+ input logic ir_intr
+
+
);
@@ -258,17 +270,6 @@
assign pinmux_debug = '0; // Todo: Need to fix
-//------------------------------------------------------
-// Register Map Decoding
-
-`define SEL_GLBL 3'b000 // GLOBAL REGISTER
-`define SEL_GPIO 3'b001 // GPIO REGISTER
-`define SEL_PWM 3'b010 // PWM REGISTER
-`define SEL_TIMER 3'b011 // TIMER REGISTER
-`define SEL_SEMA 3'b100 // SEMAPHORE REGISTER
-`define SEL_WS 3'b101 // WS281x REGISTER
-`define SEL_D2A 3'b110 // Digital2Analog REGISTER
-
//----------------------------------------
// Register Response Path Mux
@@ -296,6 +297,15 @@
logic [7:0] pwm_gpio_in;
+logic reg_glbl_cs ;
+logic reg_gpio_cs ;
+logic reg_pwm_cs ;
+logic reg_timer_cs;
+logic reg_sema_cs ;
+logic reg_ws_cs ;
+
+
+
//---------------------------------------------------------------------
@@ -389,6 +399,8 @@
.usb_intr (usb_intr ),
.i2cm_intr (i2cm_intr ),
.pwm_intr (pwm_intr ),
+ .rtc_intr (rtc_intr ),
+ .ir_intr (ir_intr ),
@@ -606,43 +618,19 @@
.ws_txd (ws_txd ),
- .dbg_clk_mon (dbg_clk_mon )
+ .dbg_clk_mon (dbg_clk_mon ),
+
+ .ir_rx (ir_rx ),
+ .ir_tx (ir_tx )
);
-//-----------------------------------------------------------------------
-// Digital To Analog Register
-//-----------------------------------------------------------------------
-dig2ana_reg u_d2a(
- // System Signals
- // Inputs
- .mclk ( mclk ),
- .h_reset_n (s_reset_ssn ),
-
- // Reg Bus Interface Signal
- .reg_cs (reg_d2a_cs ),
- .reg_wr (reg_wr ),
- .reg_addr (reg_addr[5:2] ),
- .reg_wdata (reg_wdata[31:0] ),
- .reg_be (reg_be[3:0] ),
-
- // Outputs
- .reg_rdata (reg_d2a_rdata ),
- .reg_ack (reg_d2a_ack ),
-
- .cfg_dac0_mux_sel (cfg_dac0_mux_sel ),
- .cfg_dac1_mux_sel (cfg_dac1_mux_sel ),
- .cfg_dac2_mux_sel (cfg_dac2_mux_sel ),
- .cfg_dac3_mux_sel (cfg_dac3_mux_sel )
-
-
- );
//-------------------------------------------------
// Register Block Selection Logic
//-------------------------------------------------
-reg [2:0] reg_blk_sel;
+reg [3:0] reg_blk_sel;
always @(posedge mclk or negedge s_reset_ssn)
begin
@@ -650,33 +638,46 @@
reg_blk_sel <= 'h0;
end
else begin
- if(reg_cs) reg_blk_sel <= reg_addr[9:7];
+ if(reg_cs) reg_blk_sel <= reg_addr[10:7];
end
end
-assign reg_rdata = (reg_blk_sel == `SEL_GLBL) ? {reg_glbl_rdata} :
- (reg_blk_sel == `SEL_GPIO) ? {reg_gpio_rdata} :
- (reg_blk_sel == `SEL_PWM) ? {reg_pwm_rdata} :
- (reg_blk_sel == `SEL_TIMER) ? reg_timer_rdata :
- (reg_blk_sel == `SEL_SEMA) ? {16'h0,reg_sema_rdata} :
- (reg_blk_sel == `SEL_WS) ? reg_ws_rdata :
- (reg_blk_sel == `SEL_D2A) ? reg_d2a_rdata : 'h0;
+assign reg_rdata = (reg_blk_sel == `SEL_GLBL) ? {reg_glbl_rdata} :
+ (reg_blk_sel == `SEL_GPIO) ? {reg_gpio_rdata} :
+ (reg_blk_sel == `SEL_PWM) ? {reg_pwm_rdata} :
+ (reg_blk_sel == `SEL_TIMER) ? reg_timer_rdata :
+ (reg_blk_sel == `SEL_SEMA) ? {16'h0,reg_sema_rdata} :
+ (reg_blk_sel == `SEL_WS) ? reg_ws_rdata :
+ (reg_blk_sel[3] == `SEL_PERI) ? reg_peri_rdata : 'h0;
-assign reg_ack = (reg_blk_sel == `SEL_GLBL) ? reg_glbl_ack :
- (reg_blk_sel == `SEL_GPIO) ? reg_gpio_ack :
- (reg_blk_sel == `SEL_PWM) ? reg_pwm_ack :
- (reg_blk_sel == `SEL_TIMER) ? reg_timer_ack :
- (reg_blk_sel == `SEL_SEMA) ? reg_sema_ack :
- (reg_blk_sel == `SEL_WS) ? reg_ws_ack :
- (reg_blk_sel == `SEL_D2A) ? reg_d2a_ack : 1'b0;
+assign reg_ack = (reg_blk_sel == `SEL_GLBL) ? reg_glbl_ack :
+ (reg_blk_sel == `SEL_GPIO) ? reg_gpio_ack :
+ (reg_blk_sel == `SEL_PWM) ? reg_pwm_ack :
+ (reg_blk_sel == `SEL_TIMER) ? reg_timer_ack :
+ (reg_blk_sel == `SEL_SEMA) ? reg_sema_ack :
+ (reg_blk_sel == `SEL_WS) ? reg_ws_ack :
+ (reg_blk_sel[3] == `SEL_PERI) ? reg_peri_ack : 1'b0;
-wire reg_glbl_cs = (reg_addr[9:7] == `SEL_GLBL) ? reg_cs : 1'b0;
-wire reg_gpio_cs = (reg_addr[9:7] == `SEL_GPIO) ? reg_cs : 1'b0;
-wire reg_pwm_cs = (reg_addr[9:7] == `SEL_PWM) ? reg_cs : 1'b0;
-wire reg_timer_cs = (reg_addr[9:7] == `SEL_TIMER)? reg_cs : 1'b0;
-wire reg_sema_cs = (reg_addr[9:7] == `SEL_SEMA) ? reg_cs : 1'b0;
-wire reg_ws_cs = (reg_addr[9:7] == `SEL_WS) ? reg_cs : 1'b0;
-wire reg_d2a_cs = (reg_addr[9:7] == `SEL_D2A) ? reg_cs : 1'b0;
+assign reg_glbl_cs = (reg_addr[10:7] == `SEL_GLBL) ? reg_cs : 1'b0;
+assign reg_gpio_cs = (reg_addr[10:7] == `SEL_GPIO) ? reg_cs : 1'b0;
+assign reg_pwm_cs = (reg_addr[10:7] == `SEL_PWM) ? reg_cs : 1'b0;
+assign reg_timer_cs = (reg_addr[10:7] == `SEL_TIMER)? reg_cs : 1'b0;
+assign reg_sema_cs = (reg_addr[10:7] == `SEL_SEMA) ? reg_cs : 1'b0;
+assign reg_ws_cs = (reg_addr[10:7] == `SEL_WS) ? reg_cs : 1'b0;
+assign reg_peri_cs = (reg_addr[10] == `SEL_PERI) ? reg_cs : 1'b0;
+
+assign reg_peri_wr = reg_wr;
+assign reg_peri_addr = reg_addr;
+assign reg_peri_wdata = reg_wdata;
+assign reg_peri_be = reg_be;
+
+
+
+
+
+
+
+
endmodule
diff --git a/verilog/rtl/pinmux/src/pseudorandom.sv b/verilog/rtl/pinmux/src/pseudorandom.sv
new file mode 100644
index 0000000..0a27e77
--- /dev/null
+++ b/verilog/rtl/pinmux/src/pseudorandom.sv
@@ -0,0 +1,68 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2022 , Julien OURY
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Julien OURY <julien.oury@outlook.fr>
+//
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Orginal Reference: https://github.com/JulienOury/ChristmasTreeController.git
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// Xoroshiro64++
+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+module pseudorandom (
+ input wire rst_n , // Asynchronous reset (active low)
+ input wire clk , // Clock (rising edge)
+ input wire next , // Request next value
+ output wire [31:0] random // Random value
+);
+ reg [31:0] s0;
+ reg [31:0] s1;
+ reg [31:0] n0;
+ reg [31:0] n1;
+ reg [31:0] n1_plus_n0;
+ wire [31:0] s1_xor_s0;
+
+ assign s1_xor_s0 = (s1 ^ s0);
+
+ assign random = ({n1_plus_n0[14:0],n1_plus_n0[31 : 15]} + n0);
+
+ always @(negedge rst_n or posedge clk) begin
+ if (rst_n == 1'b0) begin
+ s0 <= (32'h00000001);
+ s1 <= (32'h00000000);
+ n0 <= (32'h00000000);
+ n1 <= (32'h00000000);
+ n1_plus_n0 <= (32'h00000000);
+ end else begin
+
+ // stage 1
+ if (next == 1'b1) begin
+ s0 <= n0;
+ s1 <= n1;
+ end
+
+ // stage 2
+ n0 <= (({s0[5:0],s0[31:6]} ^ s1_xor_s0) ^ (s1_xor_s0 <<< 9));
+ n1 <= {s1_xor_s0[18:0],s1_xor_s0[31:19]};
+
+ // stage 3
+ n1_plus_n0 <= (n0 + n1);
+
+ end
+ end
+
+endmodule
diff --git a/verilog/rtl/rtc b/verilog/rtl/rtc
new file mode 160000
index 0000000..6e2ff09
--- /dev/null
+++ b/verilog/rtl/rtc
@@ -0,0 +1 @@
+Subproject commit 6e2ff09c3037ff83ea0ced2b87823361ca8daa78
diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv
index 97a3cae..fbd5144 100755
--- a/verilog/rtl/sspim/src/sspim_top.sv
+++ b/verilog/rtl/sspim/src/sspim_top.sv
@@ -139,10 +139,23 @@
logic cs_int_n ;
logic load_byte ;
+
+//###################################
+// Application Reset Synchronization
+//###################################
+wire reset_ssn;
+reset_sync u_app_rst (
+ .scan_mode (1'b0 ),
+ .dclk (clk ), // Destination clock domain
+ .arst_n (reset_n ), // active low async reset
+ .srst_n (reset_ssn )
+ );
+
+
sspim_if u_spi_if
(
. clk (clk ),
- . reset_n (reset_n ),
+ . reset_n (reset_ssn ),
// cfg
. cfg_bit_order (cfg_bit_order ),
@@ -170,7 +183,7 @@
sspim_clkgen u_clkgen
(
. clk (clk ),
- . reset_n (reset_n ),
+ . reset_n (reset_ssn ),
// cfg
. cfg_cpol (cfg_cpol ),
@@ -192,7 +205,7 @@
sspim_ctl u_spi_ctrl
(
. clk (clk ),
- . reset_n (reset_n ),
+ . reset_n (reset_ssn ),
// cfg
. cfg_cpol (cfg_cpol ),
@@ -222,7 +235,7 @@
sspim_cfg u_cfg (
. mclk (clk ),
- . reset_n (reset_n ),
+ . reset_n (reset_ssn ),
// Reg Bus Interface Signal
. reg_cs (reg_cs ),
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index 4b6012a..77f3582 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,9 +4,9 @@
// ASCI Representation of RISC = 32'h8273_8343
parameter CHIP_SIGNATURE = 32'h8273_8343;
// Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h2711_2022;
+parameter CHIP_RELEASE_DATE = 32'h1312_2022;
// Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION = 32'h0006_0000;
+parameter CHIP_REVISION = 32'h0006_4000;
parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_0100_1101_1010_1010_1000_0011;
parameter CLK_SKEW2_RESET_VAL = 32'b0000_0000_0100_0100_0100_0100_0011_1101;
@@ -149,6 +149,18 @@
`define STRAP_QSPI_INIT_BYPASS 30
`define STRAP_SOFT_REBOOT_REQ 31
+//------------------------------------------------------
+// Pinumux/PeriPheral Register Map Decoding
+`define SEL_GLBL 4'b0000 // GLOBAL REGISTER
+`define SEL_GPIO 4'b0001 // GPIO REGISTER
+`define SEL_PWM 4'b0010 // PWM REGISTER
+`define SEL_TIMER 4'b0011 // TIMER REGISTER
+`define SEL_SEMA 4'b0100 // SEMAPHORE REGISTER
+`define SEL_WS 4'b0101 // WS281x REGISTER
+`define SEL_PERI 1'b1 // Peripheral
+`define SEL_D2A 4'b1000 // Digital2Analog REGISTER
+`define SEL_RTC 4'b1001 // RTC REGISTER
+`define SEL_IR 4'b1010 // IR REGISTER
`endif // USER_PARMS
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index bc47afd..f43963e 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -13,7 +13,7 @@
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
//
//////////////////////////////////////////////////////////////////////
//// ////
@@ -40,6 +40,10 @@
//// 13. 3 x Hardware Timer ////
//// 14. UART Master ////
//// 15. SPI Slave (As Arduino ISP) ////
+//// 16. RTC ////
+//// 17. Random Generator ////
+//// 18. NEC IR Receiver ////
+//// 19. NEC IR Transmitter ////
//// ////
//// To Do: ////
//// nothing ////
@@ -286,7 +290,19 @@
//// cpu_clk will be feed through wb_interconnect for ////
//// buffering purpose ////
//// 6.0 Nov 27, 2022, Dinesh A ////
-//// MPW-7 Timing clean setup
+//// MPW-7 Timing clean setup ////
+//// 6.2 Dec 4, 2022, Dinesh A ////
+//// Bus repeater north/south/east/west added for better ////
+//// global buffering ////
+//// 6.3 Dec 7, 2022, Dinesh A ////
+//// A. peripheral block integration ////
+//// B. RTC Integration ////
+//// 6.4 Dec 13, 2022, Dinesh A ////
+//// A. Random Generator Integration ////
+//// B. NEC IR Receiver Integration ////
+//// C. NEC IR Transmitter Integration ////
+//// Bug Fix In Pinmux ////
+//// WS281x IO direction fix ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -561,7 +577,7 @@
// Global Register Wishbone Interface
//---------------------------------------------------------------------
wire wbd_glbl_stb_o ; // strobe/request
-wire [9:0] wbd_glbl_adr_o ; // address
+wire [10:0] wbd_glbl_adr_o ; // address
wire wbd_glbl_we_o ; // write
wire [WB_WIDTH-1:0] wbd_glbl_dat_o ; // data output
wire [3:0] wbd_glbl_sel_o ; // byte enable
@@ -613,14 +629,15 @@
wire [7:0] cfg_glb_ctrl ;
wire [31:0] cfg_clk_skew_ctrl1 ;
wire [31:0] cfg_clk_skew_ctrl2 ;
-wire [3:0] cfg_wcska_wi ; // clock skew adjust for wishbone interconnect
-wire [3:0] cfg_wcska_wh ; // clock skew adjust for web host
+wire [3:0] cfg_wcska_wi ; // clock skew adjust for wishbone interconnect
+wire [3:0] cfg_wcska_wh ; // clock skew adjust for web host
+wire [3:0] cfg_wcska_peri ; // clock skew adjust for peripheral
-wire [3:0] cfg_wcska_riscv ; // clock skew adjust for riscv
-wire [3:0] cfg_wcska_uart ; // clock skew adjust for uart
-wire [3:0] cfg_wcska_qspi ; // clock skew adjust for spi
-wire [3:0] cfg_wcska_pinmux ; // clock skew adjust for pinmux
-wire [3:0] cfg_wcska_qspi_co ; // clock skew adjust for global reg
+wire [3:0] cfg_wcska_riscv ; // clock skew adjust for riscv
+wire [3:0] cfg_wcska_uart ; // clock skew adjust for uart
+wire [3:0] cfg_wcska_qspi ; // clock skew adjust for spi
+wire [3:0] cfg_wcska_pinmux ; // clock skew adjust for pinmux
+wire [3:0] cfg_wcska_qspi_co ; // clock skew adjust for global reg
// Bus Repeater Signals output from Wishbone Interface
wire [3:0] cfg_wcska_riscv_rp ; // clock skew adjust for riscv
@@ -628,6 +645,7 @@
wire [3:0] cfg_wcska_qspi_rp ; // clock skew adjust for spi
wire [3:0] cfg_wcska_pinmux_rp ; // clock skew adjust for pinmux
wire [3:0] cfg_wcska_qspi_co_rp ; // clock skew adjust for global reg
+wire [3:0] cfg_wcska_peri_rp ; // clock skew adjust for peripheral
wire [31:0] irq_lines_rp ; // Repeater
wire soft_irq_rp ; // Repeater
@@ -637,6 +655,8 @@
wire wbd_clk_uart_rp ;
wire wbd_clk_pinmux_rp ;
wire wbd_clk_pinmux_skew ;
+wire wbd_clk_peri_rp ;
+wire wbd_clk_peri_skew ;
// Progammable Clock Skew inserted signals
wire wbd_clk_wi_skew ; // clock for wishbone interconnect with clock skew
@@ -750,6 +770,7 @@
// AES Integration local decleration
//------------------------------------------------------------
wire cpu_clk_aes ;
+wire cpu_clk_aes_skew ;
wire [3:0] cfg_ccska_aes ;
wire [3:0] cfg_ccska_aes_rp ;
wire aes_dmem_req ;
@@ -764,7 +785,8 @@
//------------------------------------------------------------
// FPU Integration local decleration
//------------------------------------------------------------
-wire cpu_clk_fpu ;
+wire cpu_clk_fpu ;
+wire cpu_clk_fpu_skew ;
wire [3:0] cfg_ccska_fpu ;
wire [3:0] cfg_ccska_fpu_rp ;
wire fpu_dmem_req ;
@@ -812,6 +834,26 @@
wire [7:0] cfg_dac3_mux_sel ;
//---------------------------------------------------------------------
+// Peripheral Reg I/F
+//---------------------------------------------------------------------
+wire reg_peri_cs ;
+wire reg_peri_wr ;
+wire [10:0] reg_peri_addr ;
+wire [31:0] reg_peri_wdata ;
+wire [3:0] reg_peri_be ;
+
+wire [31:0] reg_peri_rdata ;
+wire reg_peri_ack ;
+
+wire rtc_intr ; // RTC interrupt
+
+//---------------------------------------------------------------------
+// IR Receiver
+//---------------------------------------------------------------------
+wire ir_rx ; // IR Receiver Input from pad
+wire ir_tx ; // IR Transmitter
+wire ir_intr ; // IR Interrupt
+//---------------------------------------------------------------------
// Strap
//---------------------------------------------------------------------
wire [31:0] system_strap ;
@@ -849,6 +891,7 @@
assign cfg_wcska_uart = cfg_clk_skew_ctrl1[19:16];
assign cfg_wcska_pinmux = cfg_clk_skew_ctrl1[23:20];
assign cfg_wcska_qspi_co = cfg_clk_skew_ctrl1[27:24];
+assign cfg_wcska_peri = cfg_clk_skew_ctrl1[31:28];
/////////////////////////////////////////////////////////
// RISCV Clock skew control
@@ -869,7 +912,8 @@
assign cfg_ccska_aes = cfg_clk_skew_ctrl2[27:24];
assign cfg_ccska_fpu = cfg_clk_skew_ctrl2[31:28];
-assign la_data_out[127:0] = {pinmux_debug,spi_debug,riscv_debug};
+// BUS Repeater
+wire [127:0] la_data_out_int = {pinmux_debug,spi_debug,riscv_debug};
wire int_pll_clock = pll_clk_out[0];
@@ -881,8 +925,19 @@
wire [1:0] cpu_clk_rp_risc = cpu_clk_rp[1:0];
wire cpu_clk_rp_pinmux = cpu_clk_rp[2];
+//----------------------------------------------------------
+// Bus Repeater Initiatiation
+//----------------------------------------------------------
+wire [37:0] io_in_rp ;
+wire [37:0] io_in_rp1 ;
+wire [37:0] io_in_rp2 ;
+wire [37:0] io_out_int ;
+wire [37:0] io_oeb_int ;
+wire [37:0] io_out_rp1 ;
+wire [37:0] io_oeb_rp1 ;
+wire user_clock2_rp ;
-
+`include "bus_repeater.sv"
/***********************************************
Wishbone HOST
@@ -893,8 +948,8 @@
.vccd1 (vccd1 ),// User area 1 1.8V supply
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .user_clock1 (wb_clk_i ),
- .user_clock2 (user_clock2 ),
+ .user_clock1 (wb_clk_i_rp ),
+ .user_clock2 (user_clock2_rp ),
.int_pll_clock (int_pll_clock ),
.cpu_clk (cpu_clk ),
@@ -913,16 +968,16 @@
.wbd_pll_rst_n (wbd_pll_rst_n ),
// Master Port
- .wbm_rst_i (wb_rst_i ),
- .wbm_clk_i (wb_clk_i ),
- .wbm_cyc_i (wbs_cyc_i ),
- .wbm_stb_i (wbs_stb_i ),
- .wbm_adr_i (wbs_adr_i ),
- .wbm_we_i (wbs_we_i ),
- .wbm_dat_i (wbs_dat_i ),
- .wbm_sel_i (wbs_sel_i ),
- .wbm_dat_o (wbs_dat_o ),
- .wbm_ack_o (wbs_ack_o ),
+ .wbm_rst_i (wb_rst_i_rp ),
+ .wbm_clk_i (wb_clk_i_rp ),
+ .wbm_cyc_i (wbs_cyc_i_rp ),
+ .wbm_stb_i (wbs_stb_i_rp ),
+ .wbm_adr_i (wbs_adr_i_rp ),
+ .wbm_we_i (wbs_we_i_rp ),
+ .wbm_dat_i (wbs_dat_i_rp ),
+ .wbm_sel_i (wbs_sel_i_rp ),
+ .wbm_dat_o (wbs_dat_int_o ),
+ .wbm_ack_o (wbs_ack_int_o ),
.wbm_err_o ( ),
// Clock Skeq Adjust
@@ -946,7 +1001,7 @@
.cfg_clk_skew_ctrl1 (cfg_clk_skew_ctrl1 ),
.cfg_clk_skew_ctrl2 (cfg_clk_skew_ctrl2 ),
- .la_data_in (la_data_in[17:0] ),
+ .la_data_in (la_data_in_rp[17:0] ),
.uartm_rxd (uartm_rxd ),
.uartm_txd (uartm_txd ),
@@ -1129,6 +1184,10 @@
.wbd_dmem_err_i (wbd_riscv_dmem_err_o )
);
+//----------------------------------------------
+// TCM
+//----------------------------------------------
+
`ifndef SCR1_TCM_MEM
sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb(
`ifdef USE_POWER_PINS
@@ -1173,6 +1232,9 @@
***/
`endif
+//------------------------------------------------
+// icache
+//------------------------------------------------
sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb(
`ifdef USE_POWER_PINS
@@ -1194,6 +1256,10 @@
.dout1 (icache_mem_dout1 )
);
+//----------------------------------------------------------
+// dcache
+//----------------------------------------------------------
+
sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb(
`ifdef USE_POWER_PINS
.vccd1 (vccd1 ),// User area 1 1.8V supply
@@ -1271,32 +1337,38 @@
);
+//---------------------------------------------------
+// wb_interconnect
+//---------------------------------------------------
wb_interconnect #(
`ifndef SYNTHESIS
- .CH_CLK_WD (7 ),
- .CH_DATA_WD (154 )
+ .CH_CLK_WD (8 ),
+ .CH_DATA_WD (158 )
`endif
) u_intercon (
`ifdef USE_POWER_PINS
- .vccd1 (vccd1 ),// User area 1 1.8V supply
- .vssd1 (vssd1 ),// User area 1 digital ground
+ .vccd1 (vccd1 ),// User area 1 1 .8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .ch_clk_in ({
+ .ch_clk_in ({
cpu_clk,
cpu_clk,
cpu_clk,
wbd_clk_int,
wbd_clk_int,
wbd_clk_int,
+ wbd_clk_int,
wbd_clk_int} ),
- .ch_clk_out ({
+ .ch_clk_out ({
cpu_clk_rp,
+ wbd_clk_peri_rp,
wbd_clk_pinmux_rp,
wbd_clk_uart_rp,
wbd_clk_qspi_rp,
wbd_clk_risc_rp} ),
- .ch_data_in ({
+ .ch_data_in ({
+ cfg_wcska_peri[3:0],
cfg_ccska_fpu[3:0],
cfg_ccska_aes[3:0],
strap_sticky[31:0],
@@ -1306,25 +1378,26 @@
e_reset_n,
cfg_strap_pad_ctrl,
- soft_irq,
- irq_lines[31:0],
+ soft_irq,
+ irq_lines[31:0],
- cfg_ccska_riscv_core3[3:0],
- cfg_ccska_riscv_core2[3:0],
- cfg_ccska_riscv_core1[3:0],
- cfg_ccska_riscv_core0[3:0],
- cfg_ccska_riscv_icon[3:0],
- cfg_ccska_riscv_intf[3:0],
+ cfg_ccska_riscv_core3[3:0],
+ cfg_ccska_riscv_core2[3:0],
+ cfg_ccska_riscv_core1[3:0],
+ cfg_ccska_riscv_core0[3:0],
+ cfg_ccska_riscv_icon[3:0],
+ cfg_ccska_riscv_intf[3:0],
- cfg_wcska_qspi_co[3:0],
- cfg_wcska_pinmux[3:0],
- cfg_wcska_uart[3:0],
- cfg_wcska_qspi[3:0],
+ cfg_wcska_qspi_co[3:0],
+ cfg_wcska_pinmux[3:0],
+ cfg_wcska_uart[3:0],
+ cfg_wcska_qspi[3:0],
cfg_wcska_riscv[3:0]
} ),
- .ch_data_out ({
- cfg_ccska_fpu_rp[3:0],
- cfg_ccska_aes_rp[3:0],
+ .ch_data_out ({
+ cfg_wcska_peri_rp[3:0],
+ cfg_ccska_fpu_rp[3:0],
+ cfg_ccska_aes_rp[3:0],
strap_sticky_rp[31:0],
strap_uartm_rp[1:0],
system_strap_rp[31:0],
@@ -1332,326 +1405,397 @@
e_reset_n_rp,
cfg_strap_pad_ctrl_rp,
- soft_irq_rp,
- irq_lines_rp[31:0],
+ soft_irq_rp,
+ irq_lines_rp[31:0],
- cfg_ccska_riscv_core3_rp[3:0],
- cfg_ccska_riscv_core2_rp[3:0],
- cfg_ccska_riscv_core1_rp[3:0],
- cfg_ccska_riscv_core0_rp[3:0],
- cfg_ccska_riscv_icon_rp[3:0],
- cfg_ccska_riscv_intf_rp[3:0],
+ cfg_ccska_riscv_core3_rp[3:0],
+ cfg_ccska_riscv_core2_rp[3:0],
+ cfg_ccska_riscv_core1_rp[3:0],
+ cfg_ccska_riscv_core0_rp[3:0],
+ cfg_ccska_riscv_icon_rp[3:0],
+ cfg_ccska_riscv_intf_rp[3:0],
- cfg_wcska_qspi_co_rp[3:0],
- cfg_wcska_pinmux_rp[3:0],
- cfg_wcska_uart_rp[3:0],
- cfg_wcska_qspi_rp[3:0],
+ cfg_wcska_qspi_co_rp[3:0],
+ cfg_wcska_pinmux_rp[3:0],
+ cfg_wcska_uart_rp[3:0],
+ cfg_wcska_qspi_rp[3:0],
cfg_wcska_riscv_rp[3:0]
} ),
// Clock Skew adjust
- .wbd_clk_int (wbd_clk_int ),
- .cfg_cska_wi (cfg_wcska_wi ),
- .wbd_clk_wi (wbd_clk_wi_skew ),
+ .wbd_clk_int (wbd_clk_int ),
+ .cfg_cska_wi (cfg_wcska_wi ),
+ .wbd_clk_wi (wbd_clk_wi_skew ),
- .clk_i (wbd_clk_wi_skew ),
- .rst_n (wbd_int_rst_n ),
+ .clk_i (wbd_clk_wi_skew ),
+ .rst_n (wbd_int_rst_n ),
// Master 0 Interface
- .m0_wbd_dat_i (wbd_int_dat_i ),
- .m0_wbd_adr_i (wbd_int_adr_i ),
- .m0_wbd_sel_i (wbd_int_sel_i ),
- .m0_wbd_we_i (wbd_int_we_i ),
- .m0_wbd_cyc_i (wbd_int_cyc_i ),
- .m0_wbd_stb_i (wbd_int_stb_i ),
- .m0_wbd_dat_o (wbd_int_dat_o ),
- .m0_wbd_ack_o (wbd_int_ack_o ),
- .m0_wbd_err_o (wbd_int_err_o ),
+ .m0_wbd_dat_i (wbd_int_dat_i ),
+ .m0_wbd_adr_i (wbd_int_adr_i ),
+ .m0_wbd_sel_i (wbd_int_sel_i ),
+ .m0_wbd_we_i (wbd_int_we_i ),
+ .m0_wbd_cyc_i (wbd_int_cyc_i ),
+ .m0_wbd_stb_i (wbd_int_stb_i ),
+ .m0_wbd_dat_o (wbd_int_dat_o ),
+ .m0_wbd_ack_o (wbd_int_ack_o ),
+ .m0_wbd_err_o (wbd_int_err_o ),
// Master 1 Interface
- .m1_wbd_dat_i (wbd_riscv_dmem_dat_i ),
- .m1_wbd_adr_i (wbd_riscv_dmem_adr_i ),
- .m1_wbd_sel_i (wbd_riscv_dmem_sel_i ),
- .m1_wbd_bl_i (wbd_riscv_dmem_bl_i ),
- .m1_wbd_bry_i (wbd_riscv_dmem_bry_i ),
- .m1_wbd_we_i (wbd_riscv_dmem_we_i ),
- .m1_wbd_cyc_i (wbd_riscv_dmem_stb_i ),
- .m1_wbd_stb_i (wbd_riscv_dmem_stb_i ),
- .m1_wbd_dat_o (wbd_riscv_dmem_dat_o ),
- .m1_wbd_ack_o (wbd_riscv_dmem_ack_o ),
- .m1_wbd_lack_o (wbd_riscv_dmem_lack_o ),
- .m1_wbd_err_o (wbd_riscv_dmem_err_o ),
+ .m1_wbd_dat_i (wbd_riscv_dmem_dat_i ),
+ .m1_wbd_adr_i (wbd_riscv_dmem_adr_i ),
+ .m1_wbd_sel_i (wbd_riscv_dmem_sel_i ),
+ .m1_wbd_bl_i (wbd_riscv_dmem_bl_i ),
+ .m1_wbd_bry_i (wbd_riscv_dmem_bry_i ),
+ .m1_wbd_we_i (wbd_riscv_dmem_we_i ),
+ .m1_wbd_cyc_i (wbd_riscv_dmem_stb_i ),
+ .m1_wbd_stb_i (wbd_riscv_dmem_stb_i ),
+ .m1_wbd_dat_o (wbd_riscv_dmem_dat_o ),
+ .m1_wbd_ack_o (wbd_riscv_dmem_ack_o ),
+ .m1_wbd_lack_o (wbd_riscv_dmem_lack_o ),
+ .m1_wbd_err_o (wbd_riscv_dmem_err_o ),
// Master 2 Interface
- .m2_wbd_dat_i (wbd_riscv_dcache_dat_i ),
- .m2_wbd_adr_i (wbd_riscv_dcache_adr_i ),
- .m2_wbd_sel_i (wbd_riscv_dcache_sel_i ),
- .m2_wbd_bl_i (wbd_riscv_dcache_bl_i ),
- .m2_wbd_bry_i (wbd_riscv_dcache_bry_i ),
- .m2_wbd_we_i (wbd_riscv_dcache_we_i ),
- .m2_wbd_cyc_i (wbd_riscv_dcache_stb_i ),
- .m2_wbd_stb_i (wbd_riscv_dcache_stb_i ),
- .m2_wbd_dat_o (wbd_riscv_dcache_dat_o ),
- .m2_wbd_ack_o (wbd_riscv_dcache_ack_o ),
- .m2_wbd_lack_o (wbd_riscv_dcache_lack_o ),
- .m2_wbd_err_o (wbd_riscv_dcache_err_o ),
+ .m2_wbd_dat_i (wbd_riscv_dcache_dat_i ),
+ .m2_wbd_adr_i (wbd_riscv_dcache_adr_i ),
+ .m2_wbd_sel_i (wbd_riscv_dcache_sel_i ),
+ .m2_wbd_bl_i (wbd_riscv_dcache_bl_i ),
+ .m2_wbd_bry_i (wbd_riscv_dcache_bry_i ),
+ .m2_wbd_we_i (wbd_riscv_dcache_we_i ),
+ .m2_wbd_cyc_i (wbd_riscv_dcache_stb_i ),
+ .m2_wbd_stb_i (wbd_riscv_dcache_stb_i ),
+ .m2_wbd_dat_o (wbd_riscv_dcache_dat_o ),
+ .m2_wbd_ack_o (wbd_riscv_dcache_ack_o ),
+ .m2_wbd_lack_o (wbd_riscv_dcache_lack_o ),
+ .m2_wbd_err_o (wbd_riscv_dcache_err_o ),
// Master 3 Interface
- .m3_wbd_adr_i (wbd_riscv_icache_adr_i ),
- .m3_wbd_sel_i (wbd_riscv_icache_sel_i ),
- .m3_wbd_bl_i (wbd_riscv_icache_bl_i ),
- .m3_wbd_bry_i (wbd_riscv_icache_bry_i ),
- .m3_wbd_we_i (wbd_riscv_icache_we_i ),
- .m3_wbd_cyc_i (wbd_riscv_icache_stb_i ),
- .m3_wbd_stb_i (wbd_riscv_icache_stb_i ),
- .m3_wbd_dat_o (wbd_riscv_icache_dat_o ),
- .m3_wbd_ack_o (wbd_riscv_icache_ack_o ),
- .m3_wbd_lack_o (wbd_riscv_icache_lack_o ),
- .m3_wbd_err_o (wbd_riscv_icache_err_o ),
+ .m3_wbd_adr_i (wbd_riscv_icache_adr_i ),
+ .m3_wbd_sel_i (wbd_riscv_icache_sel_i ),
+ .m3_wbd_bl_i (wbd_riscv_icache_bl_i ),
+ .m3_wbd_bry_i (wbd_riscv_icache_bry_i ),
+ .m3_wbd_we_i (wbd_riscv_icache_we_i ),
+ .m3_wbd_cyc_i (wbd_riscv_icache_stb_i ),
+ .m3_wbd_stb_i (wbd_riscv_icache_stb_i ),
+ .m3_wbd_dat_o (wbd_riscv_icache_dat_o ),
+ .m3_wbd_ack_o (wbd_riscv_icache_ack_o ),
+ .m3_wbd_lack_o (wbd_riscv_icache_lack_o ),
+ .m3_wbd_err_o (wbd_riscv_icache_err_o ),
// Slave 0 Interface
- // .s0_wbd_err_i (1'b0 ), - Moved inside IP
- .s0_wbd_dat_i (wbd_spim_dat_i ),
- .s0_wbd_ack_i (wbd_spim_ack_i ),
- .s0_wbd_lack_i (wbd_spim_lack_i ),
- .s0_wbd_dat_o (wbd_spim_dat_o ),
- .s0_wbd_adr_o (wbd_spim_adr_o ),
- .s0_wbd_bry_o (wbd_spim_bry_o ),
- .s0_wbd_bl_o (wbd_spim_bl_o ),
- .s0_wbd_sel_o (wbd_spim_sel_o ),
- .s0_wbd_we_o (wbd_spim_we_o ),
- .s0_wbd_cyc_o (wbd_spim_cyc_o ),
- .s0_wbd_stb_o (wbd_spim_stb_o ),
+ // .s0_wbd_err_i (1'b0 ), - Moved inside IP
+ .s0_wbd_dat_i (wbd_spim_dat_i ),
+ .s0_wbd_ack_i (wbd_spim_ack_i ),
+ .s0_wbd_lack_i (wbd_spim_lack_i ),
+ .s0_wbd_dat_o (wbd_spim_dat_o ),
+ .s0_wbd_adr_o (wbd_spim_adr_o ),
+ .s0_wbd_bry_o (wbd_spim_bry_o ),
+ .s0_wbd_bl_o (wbd_spim_bl_o ),
+ .s0_wbd_sel_o (wbd_spim_sel_o ),
+ .s0_wbd_we_o (wbd_spim_we_o ),
+ .s0_wbd_cyc_o (wbd_spim_cyc_o ),
+ .s0_wbd_stb_o (wbd_spim_stb_o ),
// Slave 1 Interface
- // .s1_wbd_err_i (1'b0 ), - Moved inside IP
- .s1_wbd_dat_i (wbd_uart_dat_i ),
- .s1_wbd_ack_i (wbd_uart_ack_i ),
- .s1_wbd_dat_o (wbd_uart_dat_o ),
- .s1_wbd_adr_o (wbd_uart_adr_o ),
- .s1_wbd_sel_o (wbd_uart_sel_o ),
- .s1_wbd_we_o (wbd_uart_we_o ),
- .s1_wbd_cyc_o (wbd_uart_cyc_o ),
- .s1_wbd_stb_o (wbd_uart_stb_o ),
+ // .s1_wbd_err_i (1'b0 ), - Moved inside IP
+ .s1_wbd_dat_i (wbd_uart_dat_i ),
+ .s1_wbd_ack_i (wbd_uart_ack_i ),
+ .s1_wbd_dat_o (wbd_uart_dat_o ),
+ .s1_wbd_adr_o (wbd_uart_adr_o ),
+ .s1_wbd_sel_o (wbd_uart_sel_o ),
+ .s1_wbd_we_o (wbd_uart_we_o ),
+ .s1_wbd_cyc_o (wbd_uart_cyc_o ),
+ .s1_wbd_stb_o (wbd_uart_stb_o ),
// Slave 2 Interface
- // .s2_wbd_err_i (1'b0 ), - Moved inside IP
- .s2_wbd_dat_i (wbd_glbl_dat_i ),
- .s2_wbd_ack_i (wbd_glbl_ack_i ),
- .s2_wbd_dat_o (wbd_glbl_dat_o ),
- .s2_wbd_adr_o (wbd_glbl_adr_o ),
- .s2_wbd_sel_o (wbd_glbl_sel_o ),
- .s2_wbd_we_o (wbd_glbl_we_o ),
- .s2_wbd_cyc_o (wbd_glbl_cyc_o ),
- .s2_wbd_stb_o (wbd_glbl_stb_o )
+ // .s2_wbd_err_i (1'b0 ), - Moved inside IP
+ .s2_wbd_dat_i (wbd_glbl_dat_i ),
+ .s2_wbd_ack_i (wbd_glbl_ack_i ),
+ .s2_wbd_dat_o (wbd_glbl_dat_o ),
+ .s2_wbd_adr_o (wbd_glbl_adr_o ),
+ .s2_wbd_sel_o (wbd_glbl_sel_o ),
+ .s2_wbd_we_o (wbd_glbl_we_o ),
+ .s2_wbd_cyc_o (wbd_glbl_cyc_o ),
+ .s2_wbd_stb_o (wbd_glbl_stb_o )
);
+//-----------------------------------------------
+// uart+i2c+usb+spi
+//-----------------------------------------------
uart_i2c_usb_spi_top u_uart_i2c_usb_spi (
`ifdef USE_POWER_PINS
- .vccd1 (vccd1 ),// User area 1 1.8V supply
- .vssd1 (vssd1 ),// User area 1 digital ground
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .wbd_clk_int (wbd_clk_uart_rp ),
- .cfg_cska_uart (cfg_wcska_uart_rp ),
- .wbd_clk_uart (wbd_clk_uart_skew ),
+ .wbd_clk_int (wbd_clk_uart_rp ),
+ .cfg_cska_uart (cfg_wcska_uart_rp ),
+ .wbd_clk_uart (wbd_clk_uart_skew ),
- .uart_rstn (uart_rst_n ), // uart reset
- .i2c_rstn (i2c_rst_n ), // i2c reset
- .usb_rstn (usb_rst_n ), // USB reset
- .spi_rstn (sspim_rst_n ), // SPI reset
- .app_clk (wbd_clk_uart_skew ),
- .usb_clk (usb_clk ),
+ .uart_rstn (uart_rst_n ), // uart reset
+ .i2c_rstn (i2c_rst_n ), // i2c reset
+ .usb_rstn (usb_rst_n ), // USB reset
+ .spi_rstn (sspim_rst_n ), // SPI reset
+ .app_clk (wbd_clk_uart_skew ),
+ .usb_clk (usb_clk ),
// Reg Bus Interface Signal
- .reg_cs (wbd_uart_stb_o ),
- .reg_wr (wbd_uart_we_o ),
- .reg_addr (wbd_uart_adr_o[8:0] ),
- .reg_wdata (wbd_uart_dat_o ),
- .reg_be (wbd_uart_sel_o ),
+ .reg_cs (wbd_uart_stb_o ),
+ .reg_wr (wbd_uart_we_o ),
+ .reg_addr (wbd_uart_adr_o[8:0] ),
+ .reg_wdata (wbd_uart_dat_o ),
+ .reg_be (wbd_uart_sel_o ),
// Outputs
- .reg_rdata (wbd_uart_dat_i ),
- .reg_ack (wbd_uart_ack_i ),
+ .reg_rdata (wbd_uart_dat_i ),
+ .reg_ack (wbd_uart_ack_i ),
// Pad interface
- .scl_pad_i (i2cm_clk_i ),
- .scl_pad_o (i2cm_clk_o ),
- .scl_pad_oen_o (i2cm_clk_oen ),
+ .scl_pad_i (i2cm_clk_i ),
+ .scl_pad_o (i2cm_clk_o ),
+ .scl_pad_oen_o (i2cm_clk_oen ),
- .sda_pad_i (i2cm_data_i ),
- .sda_pad_o (i2cm_data_o ),
- .sda_padoen_o (i2cm_data_oen ),
+ .sda_pad_i (i2cm_data_i ),
+ .sda_pad_o (i2cm_data_o ),
+ .sda_padoen_o (i2cm_data_oen ),
- .i2cm_intr_o (i2cm_intr_o ),
+ .i2cm_intr_o (i2cm_intr_o ),
- .uart_rxd (uart_rxd ),
- .uart_txd (uart_txd ),
+ .uart_rxd (uart_rxd ),
+ .uart_txd (uart_txd ),
- .usb_in_dp (usb_dp_i ),
- .usb_in_dn (usb_dn_i ),
+ .usb_in_dp (usb_dp_i ),
+ .usb_in_dn (usb_dn_i ),
- .usb_out_dp (usb_dp_o ),
- .usb_out_dn (usb_dn_o ),
- .usb_out_tx_oen (usb_oen ),
+ .usb_out_dp (usb_dp_o ),
+ .usb_out_dn (usb_dn_o ),
+ .usb_out_tx_oen (usb_oen ),
- .usb_intr_o (usb_intr_o ),
+ .usb_intr_o (usb_intr_o ),
// SPIM Master
- .sspim_sck (sspim_sck ),
- .sspim_so (sspim_so ),
- .sspim_si (sspim_si ),
- .sspim_ssn (sspim_ssn )
+ .sspim_sck (sspim_sck ),
+ .sspim_so (sspim_so ),
+ .sspim_si (sspim_si ),
+ .sspim_ssn (sspim_ssn )
);
+//---------------------------------------
+// Pinmux
+//---------------------------------------
+
pinmux_top u_pinmux(
`ifdef USE_POWER_PINS
- .vccd1 (vccd1 ),// User area 1 1.8V supply
- .vssd1 (vssd1 ),// User area 1 digital ground
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
`endif
//clk skew adjust
- .cfg_cska_pinmux (cfg_wcska_pinmux_rp ),
- .wbd_clk_int (wbd_clk_pinmux_rp ),
- .wbd_clk_pinmux (wbd_clk_pinmux_skew ),
+ .cfg_cska_pinmux (cfg_wcska_pinmux_rp ),
+ .wbd_clk_int (wbd_clk_pinmux_rp ),
+ .wbd_clk_pinmux (wbd_clk_pinmux_skew ),
// System Signals
// Inputs
- .mclk (wbd_clk_pinmux_skew ),
- .e_reset_n (e_reset_n_rp ),
- .p_reset_n (p_reset_n_rp ),
- .s_reset_n (wbd_int_rst_n ),
+ .mclk (wbd_clk_pinmux_skew ),
+ .e_reset_n (e_reset_n_rp ),
+ .p_reset_n (p_reset_n_rp ),
+ .s_reset_n (wbd_int_rst_n ),
- .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl_rp ),
- .system_strap (system_strap_rp ),
- .strap_sticky (strap_sticky ),
- .strap_uartm (strap_uartm ),
+ .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl_rp ),
+ .system_strap (system_strap_rp ),
+ .strap_sticky (strap_sticky ),
+ .strap_uartm (strap_uartm ),
- .user_clock1 (wb_clk_i ),
- .user_clock2 (user_clock2 ),
- .int_pll_clock (int_pll_clock ),
- .xtal_clk (xtal_clk ),
- .cpu_clk (cpu_clk_rp_pinmux ),
+ .user_clock1 (wb_clk_i_rp ),
+ .user_clock2 (user_clock2_rp ),
+ .int_pll_clock (int_pll_clock ),
+ .xtal_clk (xtal_clk ),
+ .cpu_clk (cpu_clk_rp_pinmux ),
- .rtc_clk (rtc_clk ),
- .usb_clk (usb_clk ),
+ .rtc_clk (rtc_clk ),
+ .usb_clk (usb_clk ),
// Reset Control
- .cpu_core_rst_n (cpu_core_rst_n ),
- .cpu_intf_rst_n (cpu_intf_rst_n ),
- .qspim_rst_n (qspim_rst_n ),
- .sspim_rst_n (sspim_rst_n ),
- .uart_rst_n (uart_rst_n ),
- .i2cm_rst_n (i2c_rst_n ),
- .usb_rst_n (usb_rst_n ),
+ .cpu_core_rst_n (cpu_core_rst_n ),
+ .cpu_intf_rst_n (cpu_intf_rst_n ),
+ .qspim_rst_n (qspim_rst_n ),
+ .sspim_rst_n (sspim_rst_n ),
+ .uart_rst_n (uart_rst_n ),
+ .i2cm_rst_n (i2c_rst_n ),
+ .usb_rst_n (usb_rst_n ),
- .cfg_riscv_ctrl (cfg_riscv_ctrl ),
+ .cfg_riscv_ctrl (cfg_riscv_ctrl ),
// Reg Bus Interface Signal
- .reg_cs (wbd_glbl_stb_o ),
- .reg_wr (wbd_glbl_we_o ),
- .reg_addr (wbd_glbl_adr_o ),
- .reg_wdata (wbd_glbl_dat_o ),
- .reg_be (wbd_glbl_sel_o ),
+ .reg_cs (wbd_glbl_stb_o ),
+ .reg_wr (wbd_glbl_we_o ),
+ .reg_addr (wbd_glbl_adr_o ),
+ .reg_wdata (wbd_glbl_dat_o ),
+ .reg_be (wbd_glbl_sel_o ),
// Outputs
- .reg_rdata (wbd_glbl_dat_i ),
- .reg_ack (wbd_glbl_ack_i ),
+ .reg_rdata (wbd_glbl_dat_i ),
+ .reg_ack (wbd_glbl_ack_i ),
// Risc configuration
- .irq_lines (irq_lines ),
- .soft_irq (soft_irq ),
- .user_irq (user_irq ),
- .usb_intr (usb_intr_o ),
- .i2cm_intr (i2cm_intr_o ),
+ .irq_lines (irq_lines ),
+ .soft_irq (soft_irq ),
+ .user_irq (user_irq ),
+ .usb_intr (usb_intr_o ),
+ .i2cm_intr (i2cm_intr_o ),
// Digital IO
- .digital_io_out (io_out ),
- .digital_io_oen (io_oeb ),
- .digital_io_in (io_in ),
+ .digital_io_out (io_out_int ),
+ .digital_io_oen (io_oeb_int ),
+ .digital_io_in (io_in_rp ),
// SFLASH I/F
- .sflash_sck (sflash_sck ),
- .sflash_ss (spi_csn ),
- .sflash_oen (sflash_oen ),
- .sflash_do (sflash_do ),
- .sflash_di (sflash_di ),
+ .sflash_sck (sflash_sck ),
+ .sflash_ss (spi_csn ),
+ .sflash_oen (sflash_oen ),
+ .sflash_do (sflash_do ),
+ .sflash_di (sflash_di ),
// USB I/F
- .usb_dp_o (usb_dp_o ),
- .usb_dn_o (usb_dn_o ),
- .usb_oen (usb_oen ),
- .usb_dp_i (usb_dp_i ),
- .usb_dn_i (usb_dn_i ),
+ .usb_dp_o (usb_dp_o ),
+ .usb_dn_o (usb_dn_o ),
+ .usb_oen (usb_oen ),
+ .usb_dp_i (usb_dp_i ),
+ .usb_dn_i (usb_dn_i ),
// UART I/F
- .uart_txd (uart_txd ),
- .uart_rxd (uart_rxd ),
+ .uart_txd (uart_txd ),
+ .uart_rxd (uart_rxd ),
// I2CM I/F
- .i2cm_clk_o (i2cm_clk_o ),
- .i2cm_clk_i (i2cm_clk_i ),
- .i2cm_clk_oen (i2cm_clk_oen ),
- .i2cm_data_oen (i2cm_data_oen ),
- .i2cm_data_o (i2cm_data_o ),
- .i2cm_data_i (i2cm_data_i ),
+ .i2cm_clk_o (i2cm_clk_o ),
+ .i2cm_clk_i (i2cm_clk_i ),
+ .i2cm_clk_oen (i2cm_clk_oen ),
+ .i2cm_data_oen (i2cm_data_oen ),
+ .i2cm_data_o (i2cm_data_o ),
+ .i2cm_data_i (i2cm_data_i ),
// SPI MASTER
- .spim_sck (sspim_sck ),
- .spim_ssn (sspim_ssn ),
- .spim_miso (sspim_so ),
- .spim_mosi (sspim_si ),
+ .spim_sck (sspim_sck ),
+ .spim_ssn (sspim_ssn ),
+ .spim_miso (sspim_so ),
+ .spim_mosi (sspim_si ),
// SPI SLAVE
- .spis_sck (sspis_sck ),
- .spis_ssn (sspis_ssn ),
- .spis_miso (sspis_so ),
- .spis_mosi (sspis_si ),
+ .spis_sck (sspis_sck ),
+ .spis_ssn (sspis_ssn ),
+ .spis_miso (sspis_so ),
+ .spis_mosi (sspis_si ),
// UART MASTER I/F
- .uartm_rxd (uartm_rxd ),
- .uartm_txd (uartm_txd ),
+ .uartm_rxd (uartm_rxd ),
+ .uartm_txd (uartm_txd ),
- .pulse1m_mclk (pulse1m_mclk ),
+ .pulse1m_mclk (pulse1m_mclk ),
+
+ .pinmux_debug (pinmux_debug ),
+
+
+ .cfg_pll_enb (cfg_pll_enb ),
+ .cfg_pll_fed_div (cfg_pll_fed_div ),
+ .cfg_dco_mode (cfg_dco_mode ),
+ .cfg_dc_trim (cfg_dc_trim ),
+ .pll_ref_clk (pll_ref_clk ),
+
+ // Peripheral Reg Bus Interface Signal
+ .reg_peri_cs (reg_peri_cs ),
+ .reg_peri_wr (reg_peri_wr ),
+ .reg_peri_addr (reg_peri_addr ),
+ .reg_peri_wdata (reg_peri_wdata ),
+ .reg_peri_be (reg_peri_be ),
- .pinmux_debug (pinmux_debug ),
+ // Outputs
+ .reg_peri_rdata (reg_peri_rdata ),
+ .reg_peri_ack (reg_peri_ack ),
+ .rtc_intr (rtc_intr ),
- .cfg_pll_enb (cfg_pll_enb ),
- .cfg_pll_fed_div (cfg_pll_fed_div ),
- .cfg_dco_mode (cfg_dco_mode ),
- .cfg_dc_trim (cfg_dc_trim ),
- .pll_ref_clk (pll_ref_clk ),
+ .ir_rx (ir_rx ),
+ .ir_tx (ir_tx ),
+ .ir_intr (ir_intr )
- .cfg_dac0_mux_sel (cfg_dac0_mux_sel ),
- .cfg_dac1_mux_sel (cfg_dac1_mux_sel ),
- .cfg_dac2_mux_sel (cfg_dac2_mux_sel ),
- .cfg_dac3_mux_sel (cfg_dac3_mux_sel )
+ );
+
+//---------------------------------------------------------
+// Peripheral block
+//----------------------------------------------------------
+
+peri_top u_peri(
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ //clk skew adjust
+ .cfg_cska_peri (cfg_wcska_peri_rp ),
+ .wbd_clk_int (wbd_clk_peri_rp ),
+ .wbd_clk_peri (wbd_clk_peri_skew ),
+
+ // System Signals
+ // Inputs
+ .mclk (wbd_clk_peri_skew ),
+ .s_reset_n (wbd_int_rst_n ),
+
+ // Peripheral Reg Bus Interface Signal
+ .reg_cs (reg_peri_cs ),
+ .reg_wr (reg_peri_wr ),
+ .reg_addr (reg_peri_addr ),
+ .reg_wdata (reg_peri_wdata ),
+ .reg_be (reg_peri_be ),
+
+ // Outputs
+ .reg_rdata (reg_peri_rdata ),
+ .reg_ack (reg_peri_ack ),
+
+ // RTC clock domain
+ .rtc_clk (rtc_clk ),
+ .rtc_intr (rtc_intr ),
+
+ .inc_time_s ( ),
+ .inc_date_d ( ),
+
+ .ir_rx (ir_rx ),
+ .ir_tx (ir_tx ),
+ .ir_intr (ir_intr ),
+
+ .cfg_dac0_mux_sel (cfg_dac0_mux_sel ),
+ .cfg_dac1_mux_sel (cfg_dac1_mux_sel ),
+ .cfg_dac2_mux_sel (cfg_dac2_mux_sel ),
+ .cfg_dac3_mux_sel (cfg_dac3_mux_sel )
);
+//------------------------------------------
+// 4 x 8 bit DAC
+//------------------------------------------
+
dac_top u_4x8bit_dac(
`ifdef USE_POWER_PINS
- .vccd1 (vdda1 ),
- .vssd1 (vssa1 ),
+ .vccd1 (vdda1 ),
+ .vssd1 (vssa1 ),
`endif
- .Vref (analog_io[23]),
- .DIn0 (cfg_dac0_mux_sel),
- .DIn1 (cfg_dac1_mux_sel),
- .DIn2 (cfg_dac2_mux_sel),
- .DIn3 (cfg_dac3_mux_sel),
- .Vout0(analog_io[15] ),
- .Vout1(analog_io[16] ),
- .Vout2(analog_io[17] ),
- .Vout3(analog_io[18] )
+ .Vref (analog_io[23] ),
+ .DIn0 (cfg_dac0_mux_sel ),
+ .DIn1 (cfg_dac1_mux_sel ),
+ .DIn2 (cfg_dac2_mux_sel ),
+ .DIn3 (cfg_dac3_mux_sel ),
+ .Vout0 (analog_io[15] ),
+ .Vout1 (analog_io[16] ),
+ .Vout2 (analog_io[17] ),
+ .Vout3 (analog_io[18] )
);
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index 3c904f9..25b2a6e 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v
@@ -15,7 +15,9 @@
`define ADDR_SPACE_TIMER 32'h3002_0180
`define ADDR_SPACE_SEMA 32'h3002_0200
`define ADDR_SPACE_WS281X 32'h3002_0280
-`define ADDR_SPACE_ANALOG 32'h3002_0300
+`define ADDR_SPACE_ANALOG 32'h3002_0400
+`define ADDR_SPACE_RTC 32'h3002_0480
+`define ADDR_SPACE_IR 32'h3002_0500
`define ADDR_SPACE_WBHOST 32'h3008_0000
//--------------------------------------------------
@@ -38,6 +40,7 @@
`define GLBL_CFG_CLK_CTRL 8'h18 // reg_6 - RTC/USB CLK CTRL
`define GLBL_CFG_PLL_CTRL1 8'h1C // reg_7 - PLL Control-1
`define GLBL_CFG_PLL_CTRL2 8'h20 // reg_8 - PLL Control-2
+`define GLBL_CFG_RANDOM_NO 8'h24 // reg_9 - Random Number
`define GLBL_CFG_PAD_STRAP 8'h30 // Strap as seen in Pad
`define GLBL_CFG_STRAP_STICKY 8'h34 // Sticky Strap used in next soft boot
`define GLBL_CFG_SYSTEM_STRAP 8'h38 // Current System Strap
@@ -166,3 +169,22 @@
`define UART_RDATA 8'h18 // Reg-6
`define UART_TFIFO_STAT 8'h1C // Reg-7
`define UART_RFIFO_STAT 8'h20 // Reg-8
+
+//--------------------------------------------------------
+// RTC Register Map
+//--------------------------------------------------------
+`define RTC_CMD 8'h0
+`define RTC_TIME 8'h4
+`define RTC_DATE 8'h8
+`define RTC_ALRM1 8'hC
+`define RTC_ALRM2 8'h10
+`define RTC_CTRL 8'h14
+
+//--------------------------------------------------------
+// IR RECEIVER Register Map
+//--------------------------------------------------------
+`define IR_CFG_CMD 8'h00
+`define IR_CFG_MULTIPLIER 8'h04
+`define IR_CFG_DIVIDER 8'h08
+`define IR_CFG_RX_DATA 8'h0C
+`define IR_CFG_TX_DATA 8'h10
diff --git a/verilog/rtl/wb_host/src/wbh_reg.sv b/verilog/rtl/wb_host/src/wbh_reg.sv
index ab3ad2b..4c6a5ca 100644
--- a/verilog/rtl/wb_host/src/wbh_reg.sv
+++ b/verilog/rtl/wb_host/src/wbh_reg.sv
@@ -228,7 +228,7 @@
(strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b01) ? CLK_SKEW1_RESET_VAL[27:24] + 2 :
(strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b10) ? CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4;
-assign rst_clk_ctrl1[31:28] = 4'b0;
+assign rst_clk_ctrl1[31:28] = CLK_SKEW1_RESET_VAL[31:28];
always @ (posedge mclk ) begin
diff --git a/verilog/rtl/wb_interconnect/src/wb_arb.sv b/verilog/rtl/wb_interconnect/src/wb_arb.sv
index a67047b..5c4d50c 100644
--- a/verilog/rtl/wb_interconnect/src/wb_arb.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_arb.sv
@@ -114,15 +114,15 @@
grant0:
// if this req is dropped or next is asserted, check for other req's
if(!req[0] ) begin
- if(req[1]) next_state = grant1;
+ if(req[1]) next_state = grant1;
else if(req[2]) next_state = grant2;
else if(req[3]) next_state = grant3;
end
grant1:
// if this req is dropped or next is asserted, check for other req's
if(!req[1] ) begin
- if(req[2]) next_state = grant2;
- if(req[3]) next_state = grant3;
+ if(req[2]) next_state = grant2;
+ if(req[3]) next_state = grant3;
else if(req[0]) next_state = grant0;
end
grant2:
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index e595919..ea798b9 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -203,7 +203,7 @@
input logic s2_wbd_ack_i,
// input logic s2_wbd_err_i, - unused
output logic [31:0] s2_wbd_dat_o,
- output logic [9:0] s2_wbd_adr_o, // glbl reg need only 9 bits
+ output logic [10:0] s2_wbd_adr_o, // glbl reg need only 9 bits
output logic [3:0] s2_wbd_sel_o,
output logic s2_wbd_we_o,
output logic s2_wbd_cyc_o,
@@ -677,7 +677,7 @@
assign s1_wbd_stb_o = s1_wb_wr.wbd_stb ;
assign s2_wbd_dat_o = s2_wb_wr.wbd_dat ;
- assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[9:0] ; // Global Reg Need 8 bit
+ assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[10:0] ; // Global Reg Need 8 bit
assign s2_wbd_sel_o = s2_wb_wr.wbd_sel ;
assign s2_wbd_we_o = s2_wb_wr.wbd_we ;
assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ;
diff --git a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
index bc70ea2..4c5196b 100644
--- a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
@@ -238,10 +238,10 @@
// Generate Multiplexed Master Interface based on grant
always_comb begin
case(gnt)
- 3'h0: m_bus_wr = m0_wb_wr;
- 3'h1: m_bus_wr = m1_wb_wr;
- 3'h2: m_bus_wr = m2_wb_wr;
- 3'h3: m_bus_wr = m3_wb_wr;
+ 2'h0: m_bus_wr = m0_wb_wr;
+ 2'h1: m_bus_wr = m1_wb_wr;
+ 2'h2: m_bus_wr = m2_wb_wr;
+ 2'h3: m_bus_wr = m3_wb_wr;
default: m_bus_wr = m0_wb_wr;
endcase
end
