peri_top placement adjustment
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index 8d239d4..bceb7e8 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz index 843138f..f4a0c2e 100644 --- a/lef/user_project_wrapper.lef.gz +++ b/lef/user_project_wrapper.lef.gz Binary files differ
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 36306e2..3cd4c94 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -2,8 +2,8 @@ u_qspi_master 2250 350 N u_uart_i2c_usb_spi 2250 1000 N u_pinmux 2250 1900 N -u_peri 2200 3000 N -u_pll 2650 3000 N +u_peri 2200 2900 N +u_pll 2650 2900 N u_fpu 1100 2600 N u_aes 150 2600 N
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index 8b1036f..92e0edc 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -25,6 +25,7 @@ set ::env(CLOCK_PORT) "clk" set ::env(SYNTH_MAX_FANOUT) 4 +set ::env(SYNTH_BUFFERING) {0} ## CTS BUFFER set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc index 79e509a..78aca1c 100644 --- a/sdc/user_project_wrapper.sdc +++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@ ############################################################################### # Created by write_sdc -# Tue Dec 13 07:55:31 2022 +# Tue Dec 13 14:14:41 2022 ############################################################################### current_design user_project_wrapper ###############################################################################
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz index 4cf5dbd..84421be 100644 --- a/verilog/gl/user_project_wrapper.v.gz +++ b/verilog/gl/user_project_wrapper.v.gz Binary files differ
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index f0e9ffd..84cab15 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -918,6 +918,7 @@ assign cfg_ccska_aes = cfg_clk_skew_ctrl2[27:24]; assign cfg_ccska_fpu = cfg_clk_skew_ctrl2[31:28]; +// BUS Repeater wire [127:0] la_data_out_int = {pinmux_debug,spi_debug,riscv_debug}; wire int_pll_clock = pll_clk_out[0]; @@ -1442,7 +1443,7 @@ wbd_clk_qspi_rp, wbd_clk_risc_rp} ), .ch_data_in ({ - cfg_wcska_peri[3:0], + cfg_wcska_peri[3:0], cfg_ccska_fpu[3:0], cfg_ccska_aes[3:0], strap_sticky[31:0], @@ -1452,26 +1453,26 @@ e_reset_n, cfg_strap_pad_ctrl, - soft_irq, - irq_lines[31:0], + soft_irq, + irq_lines[31:0], - cfg_ccska_riscv_core3[3:0], - cfg_ccska_riscv_core2[3:0], - cfg_ccska_riscv_core1[3:0], - cfg_ccska_riscv_core0[3:0], - cfg_ccska_riscv_icon[3:0], - cfg_ccska_riscv_intf[3:0], + cfg_ccska_riscv_core3[3:0], + cfg_ccska_riscv_core2[3:0], + cfg_ccska_riscv_core1[3:0], + cfg_ccska_riscv_core0[3:0], + cfg_ccska_riscv_icon[3:0], + cfg_ccska_riscv_intf[3:0], - cfg_wcska_qspi_co[3:0], - cfg_wcska_pinmux[3:0], - cfg_wcska_uart[3:0], - cfg_wcska_qspi[3:0], + cfg_wcska_qspi_co[3:0], + cfg_wcska_pinmux[3:0], + cfg_wcska_uart[3:0], + cfg_wcska_qspi[3:0], cfg_wcska_riscv[3:0] } ), .ch_data_out ({ - cfg_wcska_peri_rp[3:0], - cfg_ccska_fpu_rp[3:0], - cfg_ccska_aes_rp[3:0], + cfg_wcska_peri_rp[3:0], + cfg_ccska_fpu_rp[3:0], + cfg_ccska_aes_rp[3:0], strap_sticky_rp[31:0], strap_uartm_rp[1:0], system_strap_rp[31:0], @@ -1479,20 +1480,20 @@ e_reset_n_rp, cfg_strap_pad_ctrl_rp, - soft_irq_rp, - irq_lines_rp[31:0], + soft_irq_rp, + irq_lines_rp[31:0], - cfg_ccska_riscv_core3_rp[3:0], - cfg_ccska_riscv_core2_rp[3:0], - cfg_ccska_riscv_core1_rp[3:0], - cfg_ccska_riscv_core0_rp[3:0], - cfg_ccska_riscv_icon_rp[3:0], - cfg_ccska_riscv_intf_rp[3:0], + cfg_ccska_riscv_core3_rp[3:0], + cfg_ccska_riscv_core2_rp[3:0], + cfg_ccska_riscv_core1_rp[3:0], + cfg_ccska_riscv_core0_rp[3:0], + cfg_ccska_riscv_icon_rp[3:0], + cfg_ccska_riscv_intf_rp[3:0], - cfg_wcska_qspi_co_rp[3:0], - cfg_wcska_pinmux_rp[3:0], - cfg_wcska_uart_rp[3:0], - cfg_wcska_qspi_rp[3:0], + cfg_wcska_qspi_co_rp[3:0], + cfg_wcska_pinmux_rp[3:0], + cfg_wcska_uart_rp[3:0], + cfg_wcska_qspi_rp[3:0], cfg_wcska_riscv_rp[3:0] } ), // Clock Skew adjust