riscv core physical Area clean-up
diff --git a/openlane/ycr2_iconnect/base.sdc b/openlane/ycr2_iconnect/base.sdc index 00fe508..75c713b 100644 --- a/openlane/ycr2_iconnect/base.sdc +++ b/openlane/ycr2_iconnect/base.sdc
@@ -2,8 +2,6 @@ # Timing Constraints ############################################################################### create_clock -name core_clk -period 20.0000 [get_ports {core_clk}] -create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}] -create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}] set_clock_transition 0.1500 [all_clocks] set_clock_uncertainty -setup 0.2500 [all_clocks] @@ -14,16 +12,83 @@ set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] -set_clock_groups -name async_clock -asynchronous \ - -group [get_clocks {core_clk}]\ - -group [get_clocks {rtc_clk}]\ - -group [get_clocks {wb_clk}] -comment {Async Clock group} +#CORE-0 IMEM Constraints +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req_ack}] +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req_ack}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}] + +#CORE-0 DMEM Constraints +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}] +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}] + +#CORE-1 IMEM Constraints +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req_ack}] +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req_ack}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}] + +#CORE-1 DMEM Constraints +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req_ack}] +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req_ack}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}] ############################################################################### # Environment ############################################################################### -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] -set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs] +set cap_load 0.0334 puts "\[INFO\]: Setting load to: $cap_load" set_load $cap_load [all_outputs]
diff --git a/openlane/ycr2_mintf/base.sdc b/openlane/ycr2_mintf/base.sdc deleted file mode 100644 index 00fe508..0000000 --- a/openlane/ycr2_mintf/base.sdc +++ /dev/null
@@ -1,32 +0,0 @@ -############################################################################### -# Timing Constraints -############################################################################### -create_clock -name core_clk -period 20.0000 [get_ports {core_clk}] -create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}] -create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}] - -set_clock_transition 0.1500 [all_clocks] -set_clock_uncertainty -setup 0.2500 [all_clocks] -set_clock_uncertainty -hold 0.2500 [all_clocks] - -set ::env(SYNTH_TIMING_DERATE) 0.05 -puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" -set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] -set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] - -set_clock_groups -name async_clock -asynchronous \ - -group [get_clocks {core_clk}]\ - -group [get_clocks {rtc_clk}]\ - -group [get_clocks {wb_clk}] -comment {Async Clock group} - -############################################################################### -# Environment -############################################################################### -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] -set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] -puts "\[INFO\]: Setting load to: $cap_load" -set_load $cap_load [all_outputs] - -############################################################################### -# Design Rules -###############################################################################
diff --git a/openlane/ycr2_mintf/config.tcl b/openlane/ycr2_mintf/config.tcl deleted file mode 100644 index a829fc4..0000000 --- a/openlane/ycr2_mintf/config.tcl +++ /dev/null
@@ -1,97 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -set script_dir [file dirname [file normalize [info script]]] - -set ::env(ROUTING_CORES) "6" - -set ::env(DESIGN_NAME) ycr2_mintf -set ::env(DESIGN_IS_CORE) "0" -set ::env(FP_PDN_CORE_RING) "0" - -# Timing configuration -set ::env(CLOCK_PERIOD) "10" -set ::env(CLOCK_PORT) "wb_clk core_clk rtc_clk" - -set ::env(SYNTH_MAX_FANOUT) 4 - -## CTS BUFFER -set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" -set ::env(CTS_SINK_CLUSTERING_SIZE) "16" -set ::env(CLOCK_BUFFER_FANOUT) "8" -set ::env(LEC_ENABLE) 0 - -set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_imem_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_icache_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dcache_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_mcore_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_tcm.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_timer.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_wb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_imem_wb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_intf.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_mintf.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_tag_fifo.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ycr_async_wbb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ycr_arb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/sync_fifo.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/async_fifo.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ctech_cells.sv \ - $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv \ - " -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ] -set ::env(SYNTH_READ_BLACKBOX_LIB) 1 -set ::env(SYNTH_DEFINES) [list SYNTHESIS ] - - -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" - -set ::env(LEC_ENABLE) 0 - -set ::env(VDD_PIN) [list {vccd1}] -set ::env(GND_PIN) [list {vssd1}] - -## Floorplan -set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 830 700 " - -set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg -set ::env(PL_TARGET_DENSITY) 0.36 -set ::env(CELL_PAD) "4" - - -set ::env(RT_MAX_LAYER) {met4} -set ::env(GLB_RT_MAXLAYER) "5" -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 -set ::env(DIODE_INSERTION_STRATEGY) 4 - - -set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" -set ::env(QUIT_ON_MAGIC_DRC) "1" -set ::env(QUIT_ON_LVS_ERROR) "0" -set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" - -#Need to cross-check why global timing opimization creating setup vio with hugh hold fix -set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" -
diff --git a/openlane/ycr2_mintf/macro_placement.cfg b/openlane/ycr2_mintf/macro_placement.cfg deleted file mode 100644 index 46c82ae..0000000 --- a/openlane/ycr2_mintf/macro_placement.cfg +++ /dev/null
@@ -1,2 +0,0 @@ -u_icache.u_cmem_2kb 185.000 291.000 FS -u_dcache.u_cmem_2kb 1185.000 291.000 N
diff --git a/openlane/ycr2_mintf/pin_order.cfg b/openlane/ycr2_mintf/pin_order.cfg deleted file mode 100644 index 7cae03b..0000000 --- a/openlane/ycr2_mintf/pin_order.cfg +++ /dev/null
@@ -1,1287 +0,0 @@ -#BUS_SORT -#MANUAL_PLACE -#W -sram0_clk0 0 0 2 -sram0_csb0 -sram0_web0 -sram0_addr0\[0\] -sram0_addr0\[1\] -sram0_addr0\[2\] -sram0_addr0\[3\] -sram0_addr0\[4\] -sram0_addr0\[5\] -sram0_addr0\[6\] -sram0_addr0\[7\] -sram0_addr0\[8\] -sram0_wmask0\[0\] -sram0_wmask0\[1\] -sram0_wmask0\[2\] -sram0_wmask0\[3\] -sram0_din0\[0\] -sram0_din0\[1\] -sram0_din0\[2\] -sram0_din0\[3\] -sram0_din0\[4\] -sram0_din0\[5\] -sram0_din0\[6\] -sram0_din0\[7\] -sram0_din0\[8\] -sram0_din0\[9\] -sram0_din0\[10\] -sram0_din0\[11\] -sram0_din0\[12\] -sram0_din0\[13\] -sram0_din0\[14\] -sram0_din0\[15\] -sram0_din0\[16\] -sram0_din0\[17\] -sram0_din0\[18\] -sram0_din0\[19\] -sram0_din0\[20\] -sram0_din0\[21\] -sram0_din0\[22\] -sram0_din0\[23\] -sram0_din0\[24\] -sram0_din0\[25\] -sram0_din0\[26\] -sram0_din0\[27\] -sram0_din0\[28\] -sram0_din0\[29\] -sram0_din0\[30\] -sram0_din0\[31\] - - -sram0_dout0\[0\] 0100 0 2 -sram0_dout0\[1\] -sram0_dout0\[2\] -sram0_dout0\[3\] -sram0_dout0\[4\] -sram0_dout0\[5\] -sram0_dout0\[6\] -sram0_dout0\[7\] -sram0_dout0\[8\] -sram0_dout0\[9\] -sram0_dout0\[10\] -sram0_dout0\[11\] -sram0_dout0\[12\] -sram0_dout0\[13\] -sram0_dout0\[14\] -sram0_dout0\[15\] -sram0_dout0\[16\] -sram0_dout0\[17\] -sram0_dout0\[18\] -sram0_dout0\[19\] -sram0_dout0\[20\] -sram0_dout0\[21\] -sram0_dout0\[22\] -sram0_dout0\[23\] -sram0_dout0\[24\] -sram0_dout0\[25\] -sram0_dout0\[26\] -sram0_dout0\[27\] -sram0_dout0\[28\] -sram0_dout0\[29\] -sram0_dout0\[30\] -sram0_dout0\[31\] - -sram0_clk1 0200 0 2 -sram0_csb1 -sram0_addr1\[8\] -sram0_addr1\[7\] -sram0_addr1\[6\] -sram0_addr1\[5\] -sram0_addr1\[4\] -sram0_addr1\[3\] -sram0_addr1\[2\] -sram0_addr1\[1\] -sram0_addr1\[0\] - -sram0_dout1\[0\] 0250 0 2 -sram0_dout1\[1\] -sram0_dout1\[2\] -sram0_dout1\[3\] -sram0_dout1\[4\] -sram0_dout1\[5\] -sram0_dout1\[6\] -sram0_dout1\[7\] -sram0_dout1\[8\] -sram0_dout1\[9\] -sram0_dout1\[10\] -sram0_dout1\[11\] -sram0_dout1\[12\] -sram0_dout1\[13\] -sram0_dout1\[14\] -sram0_dout1\[15\] -sram0_dout1\[16\] -sram0_dout1\[17\] -sram0_dout1\[18\] -sram0_dout1\[19\] -sram0_dout1\[20\] -sram0_dout1\[21\] -sram0_dout1\[22\] -sram0_dout1\[23\] -sram0_dout1\[24\] -sram0_dout1\[25\] -sram0_dout1\[26\] -sram0_dout1\[27\] -sram0_dout1\[28\] -sram0_dout1\[29\] -sram0_dout1\[30\] -sram0_dout1\[31\] - - -#S -icache_mem_clk0 -icache_mem_csb0 -icache_mem_web0 -icache_mem_addr0\[0\] -icache_mem_addr0\[1\] -icache_mem_addr0\[2\] -icache_mem_addr0\[3\] -icache_mem_addr0\[4\] -icache_mem_addr0\[5\] -icache_mem_addr0\[6\] -icache_mem_addr0\[7\] -icache_mem_addr0\[8\] -icache_mem_wmask0\[0\] -icache_mem_wmask0\[1\] -icache_mem_wmask0\[2\] -icache_mem_wmask0\[3\] -icache_mem_din0\[0\] -icache_mem_din0\[1\] -icache_mem_din0\[2\] -icache_mem_din0\[3\] -icache_mem_din0\[4\] -icache_mem_din0\[5\] -icache_mem_din0\[6\] -icache_mem_din0\[7\] -icache_mem_din0\[8\] -icache_mem_din0\[9\] -icache_mem_din0\[10\] -icache_mem_din0\[11\] -icache_mem_din0\[12\] -icache_mem_din0\[13\] -icache_mem_din0\[14\] -icache_mem_din0\[15\] -icache_mem_din0\[16\] -icache_mem_din0\[17\] -icache_mem_din0\[18\] -icache_mem_din0\[19\] -icache_mem_din0\[20\] -icache_mem_din0\[21\] -icache_mem_din0\[22\] -icache_mem_din0\[23\] -icache_mem_din0\[24\] -icache_mem_din0\[25\] -icache_mem_din0\[26\] -icache_mem_din0\[27\] -icache_mem_din0\[28\] -icache_mem_din0\[29\] -icache_mem_din0\[30\] -icache_mem_din0\[31\] - -icache_mem_clk1 100 0 2 -icache_mem_csb1 -icache_mem_addr1\[8\] -icache_mem_addr1\[7\] -icache_mem_addr1\[6\] -icache_mem_addr1\[5\] -icache_mem_addr1\[4\] -icache_mem_addr1\[3\] -icache_mem_addr1\[2\] -icache_mem_addr1\[1\] -icache_mem_addr1\[0\] - -icache_mem_dout1\[0\] 150 0 2 -icache_mem_dout1\[1\] -icache_mem_dout1\[2\] -icache_mem_dout1\[3\] -icache_mem_dout1\[4\] -icache_mem_dout1\[5\] -icache_mem_dout1\[6\] -icache_mem_dout1\[7\] -icache_mem_dout1\[8\] -icache_mem_dout1\[9\] -icache_mem_dout1\[10\] -icache_mem_dout1\[11\] -icache_mem_dout1\[12\] -icache_mem_dout1\[13\] -icache_mem_dout1\[14\] -icache_mem_dout1\[15\] -icache_mem_dout1\[16\] -icache_mem_dout1\[17\] -icache_mem_dout1\[18\] -icache_mem_dout1\[19\] -icache_mem_dout1\[20\] -icache_mem_dout1\[21\] -icache_mem_dout1\[22\] -icache_mem_dout1\[23\] -icache_mem_dout1\[24\] -icache_mem_dout1\[25\] -icache_mem_dout1\[26\] -icache_mem_dout1\[27\] -icache_mem_dout1\[28\] -icache_mem_dout1\[29\] -icache_mem_dout1\[30\] -icache_mem_dout1\[31\] - -dcache_mem_clk0 400 0 2 -dcache_mem_csb0 -dcache_mem_web0 -dcache_mem_addr0\[0\] -dcache_mem_addr0\[1\] -dcache_mem_addr0\[2\] -dcache_mem_addr0\[3\] -dcache_mem_addr0\[4\] -dcache_mem_addr0\[5\] -dcache_mem_addr0\[6\] -dcache_mem_addr0\[7\] -dcache_mem_addr0\[8\] -dcache_mem_wmask0\[0\] -dcache_mem_wmask0\[1\] -dcache_mem_wmask0\[2\] -dcache_mem_wmask0\[3\] -dcache_mem_din0\[0\] -dcache_mem_din0\[1\] -dcache_mem_din0\[2\] -dcache_mem_din0\[3\] -dcache_mem_din0\[4\] -dcache_mem_din0\[5\] -dcache_mem_din0\[6\] -dcache_mem_din0\[7\] -dcache_mem_din0\[8\] -dcache_mem_din0\[9\] -dcache_mem_din0\[10\] -dcache_mem_din0\[11\] -dcache_mem_din0\[12\] -dcache_mem_din0\[13\] -dcache_mem_din0\[14\] -dcache_mem_din0\[15\] -dcache_mem_din0\[16\] -dcache_mem_din0\[17\] -dcache_mem_din0\[18\] -dcache_mem_din0\[19\] -dcache_mem_din0\[20\] -dcache_mem_din0\[21\] -dcache_mem_din0\[22\] -dcache_mem_din0\[23\] -dcache_mem_din0\[24\] -dcache_mem_din0\[25\] -dcache_mem_din0\[26\] -dcache_mem_din0\[27\] -dcache_mem_din0\[28\] -dcache_mem_din0\[29\] -dcache_mem_din0\[30\] -dcache_mem_din0\[31\] - - -dcache_mem_dout0\[0\] 500 0 2 -dcache_mem_dout0\[1\] -dcache_mem_dout0\[2\] -dcache_mem_dout0\[3\] -dcache_mem_dout0\[4\] -dcache_mem_dout0\[5\] -dcache_mem_dout0\[6\] -dcache_mem_dout0\[7\] -dcache_mem_dout0\[8\] -dcache_mem_dout0\[9\] -dcache_mem_dout0\[10\] -dcache_mem_dout0\[11\] -dcache_mem_dout0\[12\] -dcache_mem_dout0\[13\] -dcache_mem_dout0\[14\] -dcache_mem_dout0\[15\] -dcache_mem_dout0\[16\] -dcache_mem_dout0\[17\] -dcache_mem_dout0\[18\] -dcache_mem_dout0\[19\] -dcache_mem_dout0\[20\] -dcache_mem_dout0\[21\] -dcache_mem_dout0\[22\] -dcache_mem_dout0\[23\] -dcache_mem_dout0\[24\] -dcache_mem_dout0\[25\] -dcache_mem_dout0\[26\] -dcache_mem_dout0\[27\] -dcache_mem_dout0\[28\] -dcache_mem_dout0\[29\] -dcache_mem_dout0\[30\] -dcache_mem_dout0\[31\] - -dcache_mem_clk1 600 0 2 -dcache_mem_csb1 -dcache_mem_addr1\[8\] -dcache_mem_addr1\[7\] -dcache_mem_addr1\[6\] -dcache_mem_addr1\[5\] -dcache_mem_addr1\[4\] -dcache_mem_addr1\[3\] -dcache_mem_addr1\[2\] -dcache_mem_addr1\[1\] -dcache_mem_addr1\[0\] - -dcache_mem_dout1\[0\] 650 0 2 -dcache_mem_dout1\[1\] -dcache_mem_dout1\[2\] -dcache_mem_dout1\[3\] -dcache_mem_dout1\[4\] -dcache_mem_dout1\[5\] -dcache_mem_dout1\[6\] -dcache_mem_dout1\[7\] -dcache_mem_dout1\[8\] -dcache_mem_dout1\[9\] -dcache_mem_dout1\[10\] -dcache_mem_dout1\[11\] -dcache_mem_dout1\[12\] -dcache_mem_dout1\[13\] -dcache_mem_dout1\[14\] -dcache_mem_dout1\[15\] -dcache_mem_dout1\[16\] -dcache_mem_dout1\[17\] -dcache_mem_dout1\[18\] -dcache_mem_dout1\[19\] -dcache_mem_dout1\[20\] -dcache_mem_dout1\[21\] -dcache_mem_dout1\[22\] -dcache_mem_dout1\[23\] -dcache_mem_dout1\[24\] -dcache_mem_dout1\[25\] -dcache_mem_dout1\[26\] -dcache_mem_dout1\[27\] -dcache_mem_dout1\[28\] -dcache_mem_dout1\[29\] -dcache_mem_dout1\[30\] -dcache_mem_dout1\[31\] -riscv_debug\[0\] -riscv_debug\[1\] -riscv_debug\[2\] -riscv_debug\[3\] -riscv_debug\[4\] -riscv_debug\[5\] -riscv_debug\[6\] -riscv_debug\[7\] -riscv_debug\[8\] -riscv_debug\[9\] -riscv_debug\[10\] -riscv_debug\[11\] -riscv_debug\[12\] -riscv_debug\[13\] -riscv_debug\[14\] -riscv_debug\[15\] -riscv_debug\[16\] -riscv_debug\[17\] -riscv_debug\[18\] -riscv_debug\[19\] -riscv_debug\[20\] -riscv_debug\[21\] -riscv_debug\[22\] -riscv_debug\[23\] -riscv_debug\[24\] -riscv_debug\[25\] -riscv_debug\[26\] -riscv_debug\[27\] -riscv_debug\[28\] -riscv_debug\[29\] -riscv_debug\[30\] -riscv_debug\[31\] -riscv_debug\[32\] -riscv_debug\[33\] -riscv_debug\[34\] -riscv_debug\[35\] -riscv_debug\[36\] -riscv_debug\[37\] -riscv_debug\[38\] -riscv_debug\[39\] -riscv_debug\[40\] -riscv_debug\[41\] -riscv_debug\[42\] -riscv_debug\[43\] -riscv_debug\[44\] -riscv_debug\[45\] -riscv_debug\[46\] -riscv_debug\[47\] -riscv_debug\[48\] -riscv_debug\[49\] -riscv_debug\[50\] -riscv_debug\[51\] -riscv_debug\[52\] -riscv_debug\[53\] -riscv_debug\[54\] -riscv_debug\[55\] -riscv_debug\[56\] -riscv_debug\[57\] -riscv_debug\[58\] -riscv_debug\[59\] -riscv_debug\[60\] -riscv_debug\[61\] -riscv_debug\[62\] -riscv_debug\[63\] - -wb_rst_n 750 0 -pwrup_rst_n -rst_n -core_clk -rtc_clk -core_debug_sel\[1\] -core_debug_sel\[0\] -cpu_core_rst_n\[1\] -cpu_core_rst_n\[0\] - - -#E -cfg_cska_riscv\[3\] 0000 0 2 -cfg_cska_riscv\[2\] -cfg_cska_riscv\[1\] -cfg_cska_riscv\[0\] -wbd_clk_int -wbd_clk_riscv -wb_clk - -wbd_dmem_stb_o 0100 0 2 -wbd_dmem_we_o -wbd_dmem_adr_o\[31\] -wbd_dmem_adr_o\[30\] -wbd_dmem_adr_o\[29\] -wbd_dmem_adr_o\[28\] -wbd_dmem_adr_o\[27\] -wbd_dmem_adr_o\[26\] -wbd_dmem_adr_o\[25\] -wbd_dmem_adr_o\[24\] -wbd_dmem_adr_o\[23\] -wbd_dmem_adr_o\[22\] -wbd_dmem_adr_o\[21\] -wbd_dmem_adr_o\[20\] -wbd_dmem_adr_o\[19\] -wbd_dmem_adr_o\[18\] -wbd_dmem_adr_o\[17\] -wbd_dmem_adr_o\[16\] -wbd_dmem_adr_o\[15\] -wbd_dmem_adr_o\[14\] -wbd_dmem_adr_o\[13\] -wbd_dmem_adr_o\[12\] -wbd_dmem_adr_o\[11\] -wbd_dmem_adr_o\[10\] -wbd_dmem_adr_o\[9\] -wbd_dmem_adr_o\[8\] -wbd_dmem_adr_o\[7\] -wbd_dmem_adr_o\[6\] -wbd_dmem_adr_o\[5\] -wbd_dmem_adr_o\[4\] -wbd_dmem_adr_o\[3\] -wbd_dmem_adr_o\[2\] -wbd_dmem_adr_o\[1\] -wbd_dmem_adr_o\[0\] -wbd_dmem_sel_o\[3\] -wbd_dmem_sel_o\[2\] -wbd_dmem_sel_o\[1\] -wbd_dmem_sel_o\[0\] -wbd_dmem_dat_o\[31\] -wbd_dmem_dat_o\[30\] -wbd_dmem_dat_o\[29\] -wbd_dmem_dat_o\[28\] -wbd_dmem_dat_o\[27\] -wbd_dmem_dat_o\[26\] -wbd_dmem_dat_o\[25\] -wbd_dmem_dat_o\[24\] -wbd_dmem_dat_o\[23\] -wbd_dmem_dat_o\[22\] -wbd_dmem_dat_o\[21\] -wbd_dmem_dat_o\[20\] -wbd_dmem_dat_o\[19\] -wbd_dmem_dat_o\[18\] -wbd_dmem_dat_o\[17\] -wbd_dmem_dat_o\[16\] -wbd_dmem_dat_o\[15\] -wbd_dmem_dat_o\[14\] -wbd_dmem_dat_o\[13\] -wbd_dmem_dat_o\[12\] -wbd_dmem_dat_o\[11\] -wbd_dmem_dat_o\[10\] -wbd_dmem_dat_o\[9\] -wbd_dmem_dat_o\[8\] -wbd_dmem_dat_o\[7\] -wbd_dmem_dat_o\[6\] -wbd_dmem_dat_o\[5\] -wbd_dmem_dat_o\[4\] -wbd_dmem_dat_o\[3\] -wbd_dmem_dat_o\[2\] -wbd_dmem_dat_o\[1\] -wbd_dmem_dat_o\[0\] -wbd_dmem_dat_i\[31\] -wbd_dmem_dat_i\[30\] -wbd_dmem_dat_i\[29\] -wbd_dmem_dat_i\[28\] -wbd_dmem_dat_i\[27\] -wbd_dmem_dat_i\[26\] -wbd_dmem_dat_i\[25\] -wbd_dmem_dat_i\[24\] -wbd_dmem_dat_i\[23\] -wbd_dmem_dat_i\[22\] -wbd_dmem_dat_i\[21\] -wbd_dmem_dat_i\[20\] -wbd_dmem_dat_i\[19\] -wbd_dmem_dat_i\[18\] -wbd_dmem_dat_i\[17\] -wbd_dmem_dat_i\[16\] -wbd_dmem_dat_i\[15\] -wbd_dmem_dat_i\[14\] -wbd_dmem_dat_i\[13\] -wbd_dmem_dat_i\[12\] -wbd_dmem_dat_i\[11\] -wbd_dmem_dat_i\[10\] -wbd_dmem_dat_i\[9\] -wbd_dmem_dat_i\[8\] -wbd_dmem_dat_i\[7\] -wbd_dmem_dat_i\[6\] -wbd_dmem_dat_i\[5\] -wbd_dmem_dat_i\[4\] -wbd_dmem_dat_i\[3\] -wbd_dmem_dat_i\[2\] -wbd_dmem_dat_i\[1\] -wbd_dmem_dat_i\[0\] -wbd_dmem_ack_i -wbd_dmem_err_i - -wb_dcache_stb_o 0250 0 2 -wb_dcache_we_o -wb_dcache_adr_o\[31\] -wb_dcache_adr_o\[30\] -wb_dcache_adr_o\[29\] -wb_dcache_adr_o\[28\] -wb_dcache_adr_o\[27\] -wb_dcache_adr_o\[26\] -wb_dcache_adr_o\[25\] -wb_dcache_adr_o\[24\] -wb_dcache_adr_o\[23\] -wb_dcache_adr_o\[22\] -wb_dcache_adr_o\[21\] -wb_dcache_adr_o\[20\] -wb_dcache_adr_o\[19\] -wb_dcache_adr_o\[18\] -wb_dcache_adr_o\[17\] -wb_dcache_adr_o\[16\] -wb_dcache_adr_o\[15\] -wb_dcache_adr_o\[14\] -wb_dcache_adr_o\[13\] -wb_dcache_adr_o\[12\] -wb_dcache_adr_o\[11\] -wb_dcache_adr_o\[10\] -wb_dcache_adr_o\[9\] -wb_dcache_adr_o\[8\] -wb_dcache_adr_o\[7\] -wb_dcache_adr_o\[6\] -wb_dcache_adr_o\[5\] -wb_dcache_adr_o\[4\] -wb_dcache_adr_o\[3\] -wb_dcache_adr_o\[2\] -wb_dcache_adr_o\[1\] -wb_dcache_adr_o\[0\] -wb_dcache_sel_o\[3\] -wb_dcache_sel_o\[2\] -wb_dcache_sel_o\[1\] -wb_dcache_sel_o\[0\] -wb_dcache_bl_o\[9\] -wb_dcache_bl_o\[8\] -wb_dcache_bl_o\[7\] -wb_dcache_bl_o\[6\] -wb_dcache_bl_o\[5\] -wb_dcache_bl_o\[4\] -wb_dcache_bl_o\[3\] -wb_dcache_bl_o\[2\] -wb_dcache_bl_o\[1\] -wb_dcache_bl_o\[0\] -wb_dcache_bry_o -wb_dcache_dat_o\[31\] -wb_dcache_dat_o\[30\] -wb_dcache_dat_o\[29\] -wb_dcache_dat_o\[28\] -wb_dcache_dat_o\[27\] -wb_dcache_dat_o\[26\] -wb_dcache_dat_o\[25\] -wb_dcache_dat_o\[24\] -wb_dcache_dat_o\[23\] -wb_dcache_dat_o\[22\] -wb_dcache_dat_o\[21\] -wb_dcache_dat_o\[20\] -wb_dcache_dat_o\[19\] -wb_dcache_dat_o\[18\] -wb_dcache_dat_o\[17\] -wb_dcache_dat_o\[16\] -wb_dcache_dat_o\[15\] -wb_dcache_dat_o\[14\] -wb_dcache_dat_o\[13\] -wb_dcache_dat_o\[12\] -wb_dcache_dat_o\[11\] -wb_dcache_dat_o\[10\] -wb_dcache_dat_o\[9\] -wb_dcache_dat_o\[8\] -wb_dcache_dat_o\[7\] -wb_dcache_dat_o\[6\] -wb_dcache_dat_o\[5\] -wb_dcache_dat_o\[4\] -wb_dcache_dat_o\[3\] -wb_dcache_dat_o\[2\] -wb_dcache_dat_o\[1\] -wb_dcache_dat_o\[0\] -wb_dcache_dat_i\[31\] -wb_dcache_dat_i\[30\] -wb_dcache_dat_i\[29\] -wb_dcache_dat_i\[28\] -wb_dcache_dat_i\[27\] -wb_dcache_dat_i\[26\] -wb_dcache_dat_i\[25\] -wb_dcache_dat_i\[24\] -wb_dcache_dat_i\[23\] -wb_dcache_dat_i\[22\] -wb_dcache_dat_i\[21\] -wb_dcache_dat_i\[20\] -wb_dcache_dat_i\[19\] -wb_dcache_dat_i\[18\] -wb_dcache_dat_i\[17\] -wb_dcache_dat_i\[16\] -wb_dcache_dat_i\[15\] -wb_dcache_dat_i\[14\] -wb_dcache_dat_i\[13\] -wb_dcache_dat_i\[12\] -wb_dcache_dat_i\[11\] -wb_dcache_dat_i\[10\] -wb_dcache_dat_i\[9\] -wb_dcache_dat_i\[8\] -wb_dcache_dat_i\[7\] -wb_dcache_dat_i\[6\] -wb_dcache_dat_i\[5\] -wb_dcache_dat_i\[4\] -wb_dcache_dat_i\[3\] -wb_dcache_dat_i\[2\] -wb_dcache_dat_i\[1\] -wb_dcache_dat_i\[0\] -wb_dcache_ack_i -wb_dcache_lack_i -wb_dcache_err_i -wb_dcache_cyc_o - -wb_icache_stb_o 450 0 2 -wb_icache_we_o -wb_icache_adr_o\[31\] -wb_icache_adr_o\[30\] -wb_icache_adr_o\[29\] -wb_icache_adr_o\[28\] -wb_icache_adr_o\[27\] -wb_icache_adr_o\[26\] -wb_icache_adr_o\[25\] -wb_icache_adr_o\[24\] -wb_icache_adr_o\[23\] -wb_icache_adr_o\[22\] -wb_icache_adr_o\[21\] -wb_icache_adr_o\[20\] -wb_icache_adr_o\[19\] -wb_icache_adr_o\[18\] -wb_icache_adr_o\[17\] -wb_icache_adr_o\[16\] -wb_icache_adr_o\[15\] -wb_icache_adr_o\[14\] -wb_icache_adr_o\[13\] -wb_icache_adr_o\[12\] -wb_icache_adr_o\[11\] -wb_icache_adr_o\[10\] -wb_icache_adr_o\[9\] -wb_icache_adr_o\[8\] -wb_icache_adr_o\[7\] -wb_icache_adr_o\[6\] -wb_icache_adr_o\[5\] -wb_icache_adr_o\[4\] -wb_icache_adr_o\[3\] -wb_icache_adr_o\[2\] -wb_icache_adr_o\[1\] -wb_icache_adr_o\[0\] -wb_icache_sel_o\[3\] -wb_icache_sel_o\[2\] -wb_icache_sel_o\[1\] -wb_icache_sel_o\[0\] -wb_icache_bl_o\[9\] -wb_icache_bl_o\[8\] -wb_icache_bl_o\[7\] -wb_icache_bl_o\[6\] -wb_icache_bl_o\[5\] -wb_icache_bl_o\[4\] -wb_icache_bl_o\[3\] -wb_icache_bl_o\[2\] -wb_icache_bl_o\[1\] -wb_icache_bl_o\[0\] -wb_icache_bry_o -wb_icache_dat_i\[31\] -wb_icache_dat_i\[30\] -wb_icache_dat_i\[29\] -wb_icache_dat_i\[28\] -wb_icache_dat_i\[27\] -wb_icache_dat_i\[26\] -wb_icache_dat_i\[25\] -wb_icache_dat_i\[24\] -wb_icache_dat_i\[23\] -wb_icache_dat_i\[22\] -wb_icache_dat_i\[21\] -wb_icache_dat_i\[20\] -wb_icache_dat_i\[19\] -wb_icache_dat_i\[18\] -wb_icache_dat_i\[17\] -wb_icache_dat_i\[16\] -wb_icache_dat_i\[15\] -wb_icache_dat_i\[14\] -wb_icache_dat_i\[13\] -wb_icache_dat_i\[12\] -wb_icache_dat_i\[11\] -wb_icache_dat_i\[10\] -wb_icache_dat_i\[9\] -wb_icache_dat_i\[8\] -wb_icache_dat_i\[7\] -wb_icache_dat_i\[6\] -wb_icache_dat_i\[5\] -wb_icache_dat_i\[4\] -wb_icache_dat_i\[3\] -wb_icache_dat_i\[2\] -wb_icache_dat_i\[1\] -wb_icache_dat_i\[0\] -wb_icache_ack_i -wb_icache_lack_i -wb_icache_err_i -wb_icache_cyc_o - - -cpu_intf_rst_n - - -#N -core0_uid\[1\] 000 0 2 -core0_uid\[0\] -cpu_core_rst_n_sync\[0\] -core0_imem_req_ack -core0_imem_req -core0_imem_cmd -core0_imem_addr\[31\] -core0_imem_addr\[30\] -core0_imem_addr\[29\] -core0_imem_addr\[28\] -core0_imem_addr\[27\] -core0_imem_addr\[26\] -core0_imem_addr\[25\] -core0_imem_addr\[24\] -core0_imem_addr\[23\] -core0_imem_addr\[22\] -core0_imem_addr\[21\] -core0_imem_addr\[20\] -core0_imem_addr\[19\] -core0_imem_addr\[18\] -core0_imem_addr\[17\] -core0_imem_addr\[16\] -core0_imem_addr\[15\] -core0_imem_addr\[14\] -core0_imem_addr\[13\] -core0_imem_addr\[12\] -core0_imem_addr\[11\] -core0_imem_addr\[10\] -core0_imem_addr\[9\] -core0_imem_addr\[8\] -core0_imem_addr\[7\] -core0_imem_addr\[6\] -core0_imem_addr\[5\] -core0_imem_addr\[4\] -core0_imem_addr\[3\] -core0_imem_addr\[2\] -core0_imem_addr\[1\] -core0_imem_addr\[0\] -core0_imem_bl\[2\] -core0_imem_bl\[1\] -core0_imem_bl\[0\] -core0_imem_rdata\[31\] -core0_imem_rdata\[30\] -core0_imem_rdata\[29\] -core0_imem_rdata\[28\] -core0_imem_rdata\[27\] -core0_imem_rdata\[26\] -core0_imem_rdata\[25\] -core0_imem_rdata\[24\] -core0_imem_rdata\[23\] -core0_imem_rdata\[22\] -core0_imem_rdata\[21\] -core0_imem_rdata\[20\] -core0_imem_rdata\[19\] -core0_imem_rdata\[18\] -core0_imem_rdata\[17\] -core0_imem_rdata\[16\] -core0_imem_rdata\[15\] -core0_imem_rdata\[14\] -core0_imem_rdata\[13\] -core0_imem_rdata\[12\] -core0_imem_rdata\[11\] -core0_imem_rdata\[10\] -core0_imem_rdata\[9\] -core0_imem_rdata\[8\] -core0_imem_rdata\[7\] -core0_imem_rdata\[6\] -core0_imem_rdata\[5\] -core0_imem_rdata\[4\] -core0_imem_rdata\[3\] -core0_imem_rdata\[2\] -core0_imem_rdata\[1\] -core0_imem_rdata\[0\] -core0_imem_resp\[1\] -core0_imem_resp\[0\] - -core0_dmem_req_ack 100 0 2 -core0_dmem_req -core0_dmem_cmd -core0_dmem_width\[1\] -core0_dmem_width\[0\] -core0_dmem_addr\[31\] -core0_dmem_addr\[30\] -core0_dmem_addr\[29\] -core0_dmem_addr\[28\] -core0_dmem_addr\[27\] -core0_dmem_addr\[26\] -core0_dmem_addr\[25\] -core0_dmem_addr\[24\] -core0_dmem_addr\[23\] -core0_dmem_addr\[22\] -core0_dmem_addr\[21\] -core0_dmem_addr\[20\] -core0_dmem_addr\[19\] -core0_dmem_addr\[18\] -core0_dmem_addr\[17\] -core0_dmem_addr\[16\] -core0_dmem_addr\[15\] -core0_dmem_addr\[14\] -core0_dmem_addr\[13\] -core0_dmem_addr\[12\] -core0_dmem_addr\[11\] -core0_dmem_addr\[10\] -core0_dmem_addr\[9\] -core0_dmem_addr\[8\] -core0_dmem_addr\[7\] -core0_dmem_addr\[6\] -core0_dmem_addr\[5\] -core0_dmem_addr\[4\] -core0_dmem_addr\[3\] -core0_dmem_addr\[2\] -core0_dmem_addr\[1\] -core0_dmem_addr\[0\] -core0_dmem_wdata\[31\] -core0_dmem_wdata\[30\] -core0_dmem_wdata\[29\] -core0_dmem_wdata\[28\] -core0_dmem_wdata\[27\] -core0_dmem_wdata\[26\] -core0_dmem_wdata\[25\] -core0_dmem_wdata\[24\] -core0_dmem_wdata\[23\] -core0_dmem_wdata\[22\] -core0_dmem_wdata\[21\] -core0_dmem_wdata\[20\] -core0_dmem_wdata\[19\] -core0_dmem_wdata\[18\] -core0_dmem_wdata\[17\] -core0_dmem_wdata\[16\] -core0_dmem_wdata\[15\] -core0_dmem_wdata\[14\] -core0_dmem_wdata\[13\] -core0_dmem_wdata\[12\] -core0_dmem_wdata\[11\] -core0_dmem_wdata\[10\] -core0_dmem_wdata\[9\] -core0_dmem_wdata\[8\] -core0_dmem_wdata\[7\] -core0_dmem_wdata\[6\] -core0_dmem_wdata\[5\] -core0_dmem_wdata\[4\] -core0_dmem_wdata\[3\] -core0_dmem_wdata\[2\] -core0_dmem_wdata\[1\] -core0_dmem_wdata\[0\] -core0_dmem_rdata\[31\] -core0_dmem_rdata\[30\] -core0_dmem_rdata\[29\] -core0_dmem_rdata\[28\] -core0_dmem_rdata\[27\] -core0_dmem_rdata\[26\] -core0_dmem_rdata\[25\] -core0_dmem_rdata\[24\] -core0_dmem_rdata\[23\] -core0_dmem_rdata\[22\] -core0_dmem_rdata\[21\] -core0_dmem_rdata\[20\] -core0_dmem_rdata\[19\] -core0_dmem_rdata\[18\] -core0_dmem_rdata\[17\] -core0_dmem_rdata\[16\] -core0_dmem_rdata\[15\] -core0_dmem_rdata\[14\] -core0_dmem_rdata\[13\] -core0_dmem_rdata\[12\] -core0_dmem_rdata\[11\] -core0_dmem_rdata\[10\] -core0_dmem_rdata\[9\] -core0_dmem_rdata\[8\] -core0_dmem_rdata\[7\] -core0_dmem_rdata\[6\] -core0_dmem_rdata\[5\] -core0_dmem_rdata\[4\] -core0_dmem_rdata\[3\] -core0_dmem_rdata\[2\] -core0_dmem_rdata\[1\] -core0_dmem_rdata\[0\] -core0_dmem_resp\[1\] -core0_dmem_resp\[0\] - -core0_debug\[48\] 200 0 2 -core0_debug\[47\] -core0_debug\[46\] -core0_debug\[45\] -core0_debug\[44\] -core0_debug\[43\] -core0_debug\[42\] -core0_debug\[41\] -core0_debug\[40\] -core0_debug\[39\] -core0_debug\[38\] -core0_debug\[37\] -core0_debug\[36\] -core0_debug\[35\] -core0_debug\[34\] -core0_debug\[33\] -core0_debug\[32\] -core0_debug\[31\] -core0_debug\[30\] -core0_debug\[29\] -core0_debug\[28\] -core0_debug\[27\] -core0_debug\[26\] -core0_debug\[25\] -core0_debug\[24\] -core0_debug\[23\] -core0_debug\[22\] -core0_debug\[21\] -core0_debug\[20\] -core0_debug\[19\] -core0_debug\[18\] -core0_debug\[17\] -core0_debug\[16\] -core0_debug\[15\] -core0_debug\[14\] -core0_debug\[13\] -core0_debug\[12\] -core0_debug\[11\] -core0_debug\[10\] -core0_debug\[9\] -core0_debug\[8\] -core0_debug\[7\] -core0_debug\[6\] -core0_debug\[5\] -core0_debug\[4\] -core0_debug\[3\] -core0_debug\[2\] -core0_debug\[1\] -core0_debug\[0\] - -core1_uid\[1\] 400 0 2 -core1_uid\[0\] -cpu_core_rst_n_sync\[1\] -core1_imem_req_ack -core1_imem_req -core1_imem_cmd -core1_imem_addr\[31\] -core1_imem_addr\[30\] -core1_imem_addr\[29\] -core1_imem_addr\[28\] -core1_imem_addr\[27\] -core1_imem_addr\[26\] -core1_imem_addr\[25\] -core1_imem_addr\[24\] -core1_imem_addr\[23\] -core1_imem_addr\[22\] -core1_imem_addr\[21\] -core1_imem_addr\[20\] -core1_imem_addr\[19\] -core1_imem_addr\[18\] -core1_imem_addr\[17\] -core1_imem_addr\[16\] -core1_imem_addr\[15\] -core1_imem_addr\[14\] -core1_imem_addr\[13\] -core1_imem_addr\[12\] -core1_imem_addr\[11\] -core1_imem_addr\[10\] -core1_imem_addr\[9\] -core1_imem_addr\[8\] -core1_imem_addr\[7\] -core1_imem_addr\[6\] -core1_imem_addr\[5\] -core1_imem_addr\[4\] -core1_imem_addr\[3\] -core1_imem_addr\[2\] -core1_imem_addr\[1\] -core1_imem_addr\[0\] -core1_imem_bl\[2\] -core1_imem_bl\[1\] -core1_imem_bl\[0\] -core1_imem_rdata\[31\] -core1_imem_rdata\[30\] -core1_imem_rdata\[29\] -core1_imem_rdata\[28\] -core1_imem_rdata\[27\] -core1_imem_rdata\[26\] -core1_imem_rdata\[25\] -core1_imem_rdata\[24\] -core1_imem_rdata\[23\] -core1_imem_rdata\[22\] -core1_imem_rdata\[21\] -core1_imem_rdata\[20\] -core1_imem_rdata\[19\] -core1_imem_rdata\[18\] -core1_imem_rdata\[17\] -core1_imem_rdata\[16\] -core1_imem_rdata\[15\] -core1_imem_rdata\[14\] -core1_imem_rdata\[13\] -core1_imem_rdata\[12\] -core1_imem_rdata\[11\] -core1_imem_rdata\[10\] -core1_imem_rdata\[9\] -core1_imem_rdata\[8\] -core1_imem_rdata\[7\] -core1_imem_rdata\[6\] -core1_imem_rdata\[5\] -core1_imem_rdata\[4\] -core1_imem_rdata\[3\] -core1_imem_rdata\[2\] -core1_imem_rdata\[1\] -core1_imem_rdata\[0\] -core1_imem_resp\[1\] -core1_imem_resp\[0\] - -core1_dmem_req_ack 0500 0 2 -core1_dmem_req -core1_dmem_cmd -core1_dmem_width\[1\] -core1_dmem_width\[0\] -core1_dmem_addr\[31\] -core1_dmem_addr\[30\] -core1_dmem_addr\[29\] -core1_dmem_addr\[28\] -core1_dmem_addr\[27\] -core1_dmem_addr\[26\] -core1_dmem_addr\[25\] -core1_dmem_addr\[24\] -core1_dmem_addr\[23\] -core1_dmem_addr\[22\] -core1_dmem_addr\[21\] -core1_dmem_addr\[20\] -core1_dmem_addr\[19\] -core1_dmem_addr\[18\] -core1_dmem_addr\[17\] -core1_dmem_addr\[16\] -core1_dmem_addr\[15\] -core1_dmem_addr\[14\] -core1_dmem_addr\[13\] -core1_dmem_addr\[12\] -core1_dmem_addr\[11\] -core1_dmem_addr\[10\] -core1_dmem_addr\[9\] -core1_dmem_addr\[8\] -core1_dmem_addr\[7\] -core1_dmem_addr\[6\] -core1_dmem_addr\[5\] -core1_dmem_addr\[4\] -core1_dmem_addr\[3\] -core1_dmem_addr\[2\] -core1_dmem_addr\[1\] -core1_dmem_addr\[0\] -core1_dmem_wdata\[31\] -core1_dmem_wdata\[30\] -core1_dmem_wdata\[29\] -core1_dmem_wdata\[28\] -core1_dmem_wdata\[27\] -core1_dmem_wdata\[26\] -core1_dmem_wdata\[25\] -core1_dmem_wdata\[24\] -core1_dmem_wdata\[23\] -core1_dmem_wdata\[22\] -core1_dmem_wdata\[21\] -core1_dmem_wdata\[20\] -core1_dmem_wdata\[19\] -core1_dmem_wdata\[18\] -core1_dmem_wdata\[17\] -core1_dmem_wdata\[16\] -core1_dmem_wdata\[15\] -core1_dmem_wdata\[14\] -core1_dmem_wdata\[13\] -core1_dmem_wdata\[12\] -core1_dmem_wdata\[11\] -core1_dmem_wdata\[10\] -core1_dmem_wdata\[9\] -core1_dmem_wdata\[8\] -core1_dmem_wdata\[7\] -core1_dmem_wdata\[6\] -core1_dmem_wdata\[5\] -core1_dmem_wdata\[4\] -core1_dmem_wdata\[3\] -core1_dmem_wdata\[2\] -core1_dmem_wdata\[1\] -core1_dmem_wdata\[0\] -core1_dmem_rdata\[31\] -core1_dmem_rdata\[30\] -core1_dmem_rdata\[29\] -core1_dmem_rdata\[28\] -core1_dmem_rdata\[27\] -core1_dmem_rdata\[26\] -core1_dmem_rdata\[25\] -core1_dmem_rdata\[24\] -core1_dmem_rdata\[23\] -core1_dmem_rdata\[22\] -core1_dmem_rdata\[21\] -core1_dmem_rdata\[20\] -core1_dmem_rdata\[19\] -core1_dmem_rdata\[18\] -core1_dmem_rdata\[17\] -core1_dmem_rdata\[16\] -core1_dmem_rdata\[15\] -core1_dmem_rdata\[14\] -core1_dmem_rdata\[13\] -core1_dmem_rdata\[12\] -core1_dmem_rdata\[11\] -core1_dmem_rdata\[10\] -core1_dmem_rdata\[9\] -core1_dmem_rdata\[8\] -core1_dmem_rdata\[7\] -core1_dmem_rdata\[6\] -core1_dmem_rdata\[5\] -core1_dmem_rdata\[4\] -core1_dmem_rdata\[3\] -core1_dmem_rdata\[2\] -core1_dmem_rdata\[1\] -core1_dmem_rdata\[0\] -core1_dmem_resp\[1\] -core1_dmem_resp\[0\] - -core1_debug\[48\] 0600 0 2 -core1_debug\[47\] -core1_debug\[46\] -core1_debug\[45\] -core1_debug\[44\] -core1_debug\[43\] -core1_debug\[42\] -core1_debug\[41\] -core1_debug\[40\] -core1_debug\[39\] -core1_debug\[38\] -core1_debug\[37\] -core1_debug\[36\] -core1_debug\[35\] -core1_debug\[34\] -core1_debug\[33\] -core1_debug\[32\] -core1_debug\[31\] -core1_debug\[30\] -core1_debug\[29\] -core1_debug\[28\] -core1_debug\[27\] -core1_debug\[26\] -core1_debug\[25\] -core1_debug\[24\] -core1_debug\[23\] -core1_debug\[22\] -core1_debug\[21\] -core1_debug\[20\] -core1_debug\[19\] -core1_debug\[18\] -core1_debug\[17\] -core1_debug\[16\] -core1_debug\[15\] -core1_debug\[14\] -core1_debug\[13\] -core1_debug\[12\] -core1_debug\[11\] -core1_debug\[10\] -core1_debug\[9\] -core1_debug\[8\] -core1_debug\[7\] -core1_debug\[6\] -core1_debug\[5\] -core1_debug\[4\] -core1_debug\[3\] -core1_debug\[2\] -core1_debug\[1\] -core1_debug\[0\] - -timer_irq 0700 0 2 -timer_val\[63\] -timer_val\[62\] -timer_val\[61\] -timer_val\[60\] -timer_val\[59\] -timer_val\[58\] -timer_val\[57\] -timer_val\[56\] -timer_val\[55\] -timer_val\[54\] -timer_val\[53\] -timer_val\[52\] -timer_val\[51\] -timer_val\[50\] -timer_val\[49\] -timer_val\[48\] -timer_val\[47\] -timer_val\[46\] -timer_val\[45\] -timer_val\[44\] -timer_val\[43\] -timer_val\[42\] -timer_val\[41\] -timer_val\[40\] -timer_val\[39\] -timer_val\[38\] -timer_val\[37\] -timer_val\[36\] -timer_val\[35\] -timer_val\[34\] -timer_val\[33\] -timer_val\[32\] -timer_val\[31\] -timer_val\[30\] -timer_val\[29\] -timer_val\[28\] -timer_val\[27\] -timer_val\[26\] -timer_val\[25\] -timer_val\[24\] -timer_val\[23\] -timer_val\[22\] -timer_val\[21\] -timer_val\[20\] -timer_val\[19\] -timer_val\[18\] -timer_val\[17\] -timer_val\[16\] -timer_val\[15\] -timer_val\[14\] -timer_val\[13\] -timer_val\[12\] -timer_val\[11\] -timer_val\[10\] -timer_val\[9\] -timer_val\[8\] -timer_val\[7\] -timer_val\[6\] -timer_val\[5\] -timer_val\[4\] -timer_val\[3\] -timer_val\[2\] -timer_val\[1\] -timer_val\[0\] - -pwrup_rst_n_sync -rst_n_sync -test_mode -test_rst_n -core2_uid\[1\] -core2_uid\[0\] -core3_uid\[1\] -core3_uid\[0\]
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc index 51d4ab8..f0ec289 100644 --- a/openlane/ycr_core_top/base.sdc +++ b/openlane/ycr_core_top/base.sdc
@@ -12,12 +12,47 @@ set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] +#IMEM Constraints +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}] + +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}] + +#DMEM Constraints +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}] + +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}] ############################################################################### # Environment ############################################################################### -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] -set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs] +set cap_load 0.0334 puts "\[INFO\]: Setting load to: $cap_load" set_load $cap_load [all_outputs]
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index 5325e7f..3038a4e 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -72,11 +72,11 @@ ## Floorplan set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 590 960 " +set ::env(DIE_AREA) "0 0 560 950 " set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg -set ::env(PL_TARGET_DENSITY) 0.37 -set ::env(CELL_PAD) "6" +set ::env(PL_TARGET_DENSITY) 0.40 +set ::env(CELL_PAD) "4" set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4}
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 8112563..95e3399 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h48m17s0ms,0h3m48s0ms,-2.0,-1,-1,-1,569.73,12,0,0,0,0,0,0,-1,0,0,-1,-1,1426146,10402,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.6,6.54,1.16,1.88,0.0,349,3680,349,3680,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h49m29s0ms,0h4m19s0ms,-2.0,-1,-1,-1,569.15,12,0,0,0,0,0,0,-1,0,0,-1,-1,1433179,10348,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.53,6.45,1.29,1.91,0.0,349,3680,349,3680,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/ycr2_iconnect/final_summary_report.csv b/signoff/ycr2_iconnect/final_summary_report.csv index 73e1d26..8d1274c 100644 --- a/signoff/ycr2_iconnect/final_summary_report.csv +++ b/signoff/ycr2_iconnect/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/ycr2_iconnect,ycr2_iconnect,ycr2_iconnect,flow completed,0h16m4s0ms,0h12m33s0ms,24394.736842105263,0.38,12197.368421052632,11.41,1190.28,4635,0,0,0,0,0,0,0,124,0,0,-1,707492,57833,0.0,-0.82,-1,0.0,0.0,0.0,-34.39,-1,0.0,0.0,532306334.0,0.0,39.01,55.4,18.98,40.67,-1,4809,10170,596,5894,0,0,0,5214,457,45,221,65,788,146,6,1661,783,796,18,718,5054,0,5772,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.2,0.3,sky130_fd_sc_hd,14,3 +0,/project/openlane/ycr2_iconnect,ycr2_iconnect,ycr2_iconnect,flow completed,0h14m56s0ms,0h10m9s0ms,24394.736842105263,0.38,12197.368421052632,11.41,1115.72,4635,0,0,0,0,0,0,0,89,0,0,-1,679278,55379,-1.83,-2.29,-1,-0.1,-0.27,-3.61,-38.89,-1,-0.12,-0.43,520617992.0,0.0,38.01,53.45,17.58,41.27,-1,4809,10170,596,5894,0,0,0,5214,457,45,221,65,788,146,6,1661,783,796,18,718,5054,0,5772,97.37098344693281,10.27,10,AREA 0,4,50,1,153.6,153.18,0.2,0.3,sky130_fd_sc_hd,14,3
diff --git a/signoff/ycr_core_top/final_summary_report.csv b/signoff/ycr_core_top/final_summary_report.csv index 34d92ad..c78c86f 100644 --- a/signoff/ycr_core_top/final_summary_report.csv +++ b/signoff/ycr_core_top/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/ycr_core_top,ycr_core_top,ycr_core_top,flow completed,1h11m5s0ms,1h3m1s0ms,72524.7175141243,0.5664,36262.35875706215,36.42,2339.02,20539,0,0,0,0,0,0,0,149,0,0,-1,1331865,186774,0.0,-9.52,-1,0.0,0.0,0.0,-9015.79,-1,0.0,0.0,1033053596.0,0.0,51.08,69.94,24.69,50.9,-1,16396,22729,542,6775,0,0,0,19178,557,261,518,596,2917,897,259,4835,2528,2435,37,688,7612,0,8300,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.37,0.3,sky130_fd_sc_hd,6,3 +0,/project/openlane/ycr_core_top,ycr_core_top,ycr_core_top,flow completed,1h30m16s0ms,1h22m51s0ms,77214.28571428571,0.532,38607.142857142855,38.76,2318.77,20539,0,0,0,0,0,0,0,158,0,0,-1,1266700,185348,0.0,-8.32,-1,-0.56,-0.57,0.0,-7803.43,-1,-1.86,-2.28,996539415.0,0.0,49.4,71.61,26.89,54.45,-1,16396,22729,542,6775,0,0,0,19178,557,261,518,596,2917,897,259,4835,2528,2435,37,682,7203,0,7885,94.6073793755913,10.57,10,AREA 0,4,50,1,153.6,153.18,0.4,0.3,sky130_fd_sc_hd,4,3
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl index f78d21e..8d09b61 100644 --- a/sta/scripts/caravel_timing.tcl +++ b/sta/scripts/caravel_timing.tcl
@@ -1,7 +1,7 @@ - set ::env(USER_ROOT) "/home/dinesha/workarea/opencore/git/riscduino" - set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe" - set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4" + set ::env(USER_ROOT) ".." + set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel" + set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw5" read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib @@ -43,13 +43,14 @@ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v # User project netlist - read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v - read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v - read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v + read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v + read_verilog $::env(USER_ROOT)/verilog/gl/ycr2_iconnect.v + read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v + read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v + read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v - read_verilog $::env(USER_ROOT)/verilog/gl/mbist_wrapper.v read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v @@ -144,15 +145,17 @@ read_spef -path gpio_defaults_block_37 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef ## User Project Spef - read_spef -path mprj/u_mbist $::env(USER_ROOT)/spef/mbist_wrapper.spef - read_spef -path mprj/u_riscv_top $::env(USER_ROOT)/spef/ycr1_top_wb.spef - read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef - read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef - read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef - read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef - read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef - read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef + read_spef -path mprj/u_riscv_top.u_connect $::env(USER_ROOT)/spef/ycr2_iconnect.spef + read_spef -path mprj/u_riscv_top.u_intf $::env(USER_ROOT)/spef/ycr_intf.spef + read_spef -path mprj/u_riscv_top.i_core_top_0 $::env(USER_ROOT)/spef/ycr_core_top.spef + read_spef -path mprj/u_riscv_top.i_core_top_1 $::env(USER_ROOT)/spef/ycr_core_top.spef + read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef + read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef + read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef + read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef + read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef + read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef read_sdc -echo ./sdc/caravel.sdc
diff --git a/sta/scripts/ycr2_iconnect_timing.tcl b/sta/scripts/ycr2_iconnect_timing.tcl new file mode 100644 index 0000000..ea8852d --- /dev/null +++ b/sta/scripts/ycr2_iconnect_timing.tcl
@@ -0,0 +1,47 @@ + + set ::env(USER_ROOT) ".." + set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel" + set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw5" + + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib + + # User project netlist + read_verilog $::env(USER_ROOT)/verilog/gl/ycr2_iconnect.v + + + link_design ycr2_iconnect + + + ## User Project Spef + read_spef $::env(USER_ROOT)/spef/ycr2_iconnect.spef + + + read_sdc -echo ./sdc/ycr2_iconnect.sdc + set_propagated_clock [all_clocks] + + check_setup -verbose > unconstraints.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50 + report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50 + report_worst_slack -max + report_worst_slack -min + report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10 + report_check_types -max_slew -max_capacitance -max_fanout -violators > slew.cap.fanout.vio.rpt + +
diff --git a/sta/scripts/ycr_core_timing.tcl b/sta/scripts/ycr_core_timing.tcl new file mode 100644 index 0000000..62484ae --- /dev/null +++ b/sta/scripts/ycr_core_timing.tcl
@@ -0,0 +1,83 @@ + + set ::env(USER_ROOT) ".." + set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel" + set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw5" + + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib + + # User project netlist + read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v + + + link_design ycr_core_top + + + ## User Project Spef + read_spef $::env(USER_ROOT)/spef/ycr_core_top.spef + + + read_sdc -echo ./sdc/ycr_core_top.sdc + set_propagated_clock [all_clocks] + + check_setup -verbose > unconstraints.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50 + report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50 + report_worst_slack -max + report_worst_slack -min + report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10 + report_check_types -max_slew -max_capacitance -max_fanout -violators > slew.cap.fanout.vio.rpt + + + #Delay check around imem + echo "imem Interface Min Timing.................." > imem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through core2imem_cmd_o >> imem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through core2imem_req_o >> imem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through imem2core_req_ack_i >> imem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through core2imem_addr_o[*] >> imem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through core2imem_bl_o[*] >> imem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through imem2core_rdata_i[*] >> imem.min.rpt + + echo "imem Interface max Timing.................." > imem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through core2imem_cmd_o >> imem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through core2imem_req_o >> imem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through imem2core_req_ack_i >> imem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through core2imem_addr_o[*] >> imem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through core2imem_bl_o[*] >> imem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through imem2core_rdata_i[*] >> imem.max.rpt + + #Delay check around imem + echo "dmem Interface Min Timing.................." > dmem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through core2dmem_cmd_o >> dmem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through core2dmem_req_o >> dmem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through dmem2core_req_ack_i >> dmem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through core2dmem_addr_o[*] >> dmem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through core2dmem_wdata_o[*] >> dmem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through core2dmem_width_o[*] >> dmem.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through dmem2core_rdata_i[*] >> dmem.min.rpt + + echo "imem Interface max Timing.................." > imem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through core2dmem_cmd_o >> dmem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through core2dmem_req_o >> dmem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through dmem2core_req_ack_i >> dmem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through core2dmem_addr_o[*] >> dmem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through core2dmem_wdata_o[*] >> dmem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through core2dmem_width_o[*] >> dmem.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through dmem2core_rdata_i[*] >> dmem.max.rpt +
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 711014a..85ec73f 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -1,7 +1,7 @@ set ::env(IO_PCT) "0.2" set ::env(SYNTH_MAX_FANOUT) "5" set ::env(SYNTH_CAP_LOAD) "1" -set ::env(SYNTH_TIMING_DERATE) 0.05 +set ::env(SYNTH_TIMING_DERATE) 0.01 set ::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) 0.25 set ::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) 0.25 set ::env(SYNTH_CLOCK_TRANSITION) 0.15 @@ -22,10 +22,6 @@ create_clock -name uarts_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart_core.u_lineclk_buf.u_mux/X}] create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.u_mux/X}] -create_generated_clock -name mem_clk0 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[0].u_mem_sel.u_mem_clk_sel.u_mux/X] -create_generated_clock -name mem_clk1 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[1].u_mem_sel.u_mem_clk_sel.u_mux/X] -create_generated_clock -name mem_clk2 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[2].u_mem_sel.u_mem_clk_sel.u_mux/X] -create_generated_clock -name mem_clk3 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[3].u_mem_sel.u_mem_clk_sel.u_mux/X] ## Case analysis @@ -49,10 +45,10 @@ set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[0]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[1]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[2]}] -set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[3]}] +set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[1]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}] +set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}] set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}] set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}] @@ -64,10 +60,6 @@ set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}] set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}] -set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[0]}] -set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[1]}] -set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[2]}] -set_case_analysis 1 [get_pins {mprj/u_mbist/cfg_cska_mbist[3]}] #disable clock gating check at static clock select pins
diff --git a/sta/sdc/ycr2_iconnect.sdc b/sta/sdc/ycr2_iconnect.sdc new file mode 100644 index 0000000..75c713b --- /dev/null +++ b/sta/sdc/ycr2_iconnect.sdc
@@ -0,0 +1,97 @@ +############################################################################### +# Timing Constraints +############################################################################### +create_clock -name core_clk -period 20.0000 [get_ports {core_clk}] + +set_clock_transition 0.1500 [all_clocks] +set_clock_uncertainty -setup 0.2500 [all_clocks] +set_clock_uncertainty -hold 0.2500 [all_clocks] + +set ::env(SYNTH_TIMING_DERATE) 0.05 +puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" +set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] +set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] + +#CORE-0 IMEM Constraints +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req_ack}] +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req_ack}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}] + +#CORE-0 DMEM Constraints +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}] +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}] + +#CORE-1 IMEM Constraints +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req_ack}] +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req_ack}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}] + +#CORE-1 DMEM Constraints +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}] +set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}] + +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req_ack}] +set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req_ack}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}] + +############################################################################### +# Environment +############################################################################### +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs] +set cap_load 0.0334 +puts "\[INFO\]: Setting load to: $cap_load" +set_load $cap_load [all_outputs] + +############################################################################### +# Design Rules +###############################################################################
diff --git a/sta/sdc/ycr_core_top.sdc b/sta/sdc/ycr_core_top.sdc new file mode 100644 index 0000000..f0ec289 --- /dev/null +++ b/sta/sdc/ycr_core_top.sdc
@@ -0,0 +1,61 @@ +############################################################################### +# Timing Constraints +############################################################################### +create_clock -name core_clk -period 20.0000 [get_ports {clk}] + +set_clock_transition 0.1500 [all_clocks] +set_clock_uncertainty -setup 0.2500 [all_clocks] +set_clock_uncertainty -hold 0.2500 [all_clocks] + +set ::env(SYNTH_TIMING_DERATE) 0.05 +puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" +set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] +set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] + +#IMEM Constraints +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}] + +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}] + +#DMEM Constraints +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}] +set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}] + +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}] + +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}] + +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}] + +############################################################################### +# Environment +############################################################################### +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs] +set cap_load 0.0334 +puts "\[INFO\]: Setting load to: $cap_load" +set_load $cap_load [all_outputs] + +############################################################################### +# Design Rules +###############################################################################