dual core clean up
diff --git a/Makefile b/Makefile
index cd5722b..7c36e24 100644
--- a/Makefile
+++ b/Makefile
@@ -72,10 +72,8 @@
PDK_PATH=${PDK_ROOT}/sky130A
VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} RISC_CORE=${RISC_CORE} && make"
$(DV_PATTERNS): verify-% : ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo
- docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_PATH}:${PDK_PATH} \
- -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
- -e TARGET_PATH=${TARGET_PATH} -e PDK_PATH=${PDK_PATH} \
- -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} \
+ -e TARGET_PATH=${TARGET_PATH} \
-u $(id -u $$USER):$(id -g $$USER) dineshannayya/dv_setup:mpw5 \
sh -c $(VERIFY_COMMAND)
@@ -188,6 +186,24 @@
cd $(RISCV_TEST_DIR); git checkout $(RISCV_TEST_BRANCH); \
fi
+zip:
+ gzip -f def/*
+ gzip -f lef/*
+ gzip -f gds/*
+ gzip -f mag/*
+ gzip -f maglef/*
+ gzip -f spef/*
+ gzip -f spi/lvs/*
+
+unzip:
+ gzip -d def/*
+ gzip -d lef/*
+ gzip -d gds/*
+ gzip -d mag/*
+ gzip -d maglef/*
+ gzip -d spef/*
+ gzip -d spi/lvs/*
+
.PHONY: help
help:
cd $(CARAVEL_ROOT) && $(MAKE) help
diff --git a/README.md b/README.md
index 7271967..e6e9b0b 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,5 @@
```
- Riscduino SOC
+ Riscduino Dual Risc Core SOC
Permission to use, copy, modify, and/or distribute this soc for any
@@ -32,7 +32,7 @@
# Overview
-Riscduino is a 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targetted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
+Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targetted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
# Riscduino Block Diagram
@@ -47,15 +47,15 @@
# Key features
```
* Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
- * industry-grade and silicon-proven Open-Source RISC-V core from syntacore
- * 4KB SRAM for data memory
- * 8KB SRAM for program memory
+ * Dual Core 32 Bit RISC-V core
+ * 2KB SRAM for instruction cache
+ * 2KB SRAM for data cache
+ * 2KB SRAM for Tightly coupled memory - For Data Memory
* Quad SPI Master
* UART with 16Byte FIFO
* USB 1.1 Host
* I2C Master
* Simple SPI Master
- * MBIST controller for 8KB Program memory
* 6 Channel ADC (in Progress)
* 6 PWM
* Pin Compatbible to arudino uno
@@ -127,9 +127,22 @@
## RISC V Core
-Riscduino SOC Integrated Syntacore SCR1 Open-source RISV-V compatible MCU-class core.
-It is industry-grade and silicon-proven IP. Git link: https://github.com/syntacore/scr1
-
+Riscduino SOC Integrated Dual 32 Bits RISC V core. Initial version of Single core RISC-V core is picked from
+Syntacore SCR1 (https://github.com/syntacore/scr1)
+### RISC V core customization for Riscduino SOC
+Following Design changes are done on the basic version of syntacore RISC core
+```
+ * Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys
+ * Instruction Request are changed from Single word to 4 Word Burst
+ * Multiplication and Divsion are changed to improve timing
+ * Additional pipe line stages added to improve the RISC timing closure near to 50Mhz
+ * 2KB instruction cache
+ * 2KB data cache
+ * Additional router are added towards instruction cache
+ * Additional router are added towards data cache
+ * Dual core related changes
+ * Modified AXI/AHB interface to wishbone interface for instruction and data memory interface
+```
### Block Diagram
<table>
<tr>
@@ -141,17 +154,14 @@
```
* RV32I or RV32E ISA base + optional RVM and RVC standard extensions
* Machine privilege mode only
- * 2 to 4 stage pipeline
+ * 2 to 5 stage pipeline
+ * 2KB icache
+ * 2KB dcache
* Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
* Optional RISC-V Debug subsystem with JTAG interface
* Optional on-chip Tightly-Coupled Memory
```
-### RISC V core customization Riscduino SOC
-
-
-* **Update**: Modified some of the system verilog syntax to basic verilog syntax to compile/synthesis in open source tool like simulator (iverilog) and synthesis (yosys).
-* **Modification**: Modified the AXI/AHB interface to wishbone interface towards instruction & data memory interface
# SOC Memory Map
diff --git a/docs/source/_static/Riscduino_Soc.png b/docs/source/_static/Riscduino_Soc.png
index cf6c825..69e3783 100644
--- a/docs/source/_static/Riscduino_Soc.png
+++ b/docs/source/_static/Riscduino_Soc.png
Binary files differ
diff --git a/hacks/src/openlane/io_place.py b/hacks/src/openlane/io_place.py
index 1e8b2b1..81d7f4e 100644
--- a/hacks/src/openlane/io_place.py
+++ b/hacks/src/openlane/io_place.py
@@ -1,4 +1,3 @@
-#!/usr/bin/env python3
# Copyright 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
@@ -25,458 +24,511 @@
...
...
"""
+import odb
import os
import re
import sys
-import argparse
+import click
import random
-import odb
-parser = argparse.ArgumentParser(description='''
-Places the IOs according to an input file. Supports regexes.
-File format:
-#N|#S|#E|#W
-pin1_regex (low co-ordinates to high co-ordinates; e.g., bot to top and left to right)
-pin2_regex
-...
-#S|#N|#E|#W
-...
-...
-''')
+@click.command()
+@click.option("-l", "--input-lef", required=True, help="Input merged tlef/lef file.")
+@click.option(
+ "-o",
+ "--output-def",
+ default="./output.def",
+ help="Output DEF file with newly placed pins",
+)
+@click.option("-c", "--config", required=False, help="Optional configuration file.")
+@click.option(
+ "-r",
+ "--reverse",
+ default="",
+ type=str,
+ help="Reverse along comma,delimited,cardinals: e.g. N,E",
+)
+@click.option("-L", "--length", default=2, type=float, help="Pin length in microns.")
+@click.option(
+ "-V",
+ "--ver-layer",
+ required=True,
+ help="Name of metal layer to place vertical pins on.",
+)
+@click.option(
+ "-H",
+ "--hor-layer",
+ required=True,
+ help="Name of metal layer to place horizontal pins on.",
+)
+@click.option(
+ "--hor-extension",
+ default=0,
+ type=float,
+ help="Extension for vertical pins in microns.",
+)
+@click.option(
+ "--ver-extension",
+ default=0,
+ type=float,
+ help="Extension for horizontal pins in microns.",
+)
+@click.option(
+ "--ver-width-mult", default=2, type=float, help="Multiplier for vertical pins."
+)
+@click.option(
+ "--hor-width-mult", default=2, type=float, help="Multiplier for horizontal pins."
+)
+@click.option(
+ "--bus-sort/--no-bus-sort",
+ default=False,
+ help="Misnomer: pins are grouped by index instead of bus, i.e. a[0] goes with b[0] instead of a[1].",
+)
+@click.argument("input_def")
+def cli(
+ input_lef,
+ output_def,
+ config,
+ ver_layer,
+ hor_layer,
+ ver_width_mult,
+ hor_width_mult,
+ length,
+ hor_extension,
+ ver_extension,
+ reverse,
+ bus_sort,
+ input_def,
+):
+ """
+ Places the IOs in an input def with an optional config file that supports regexes.
-parser.add_argument('--input-def', '-d', required=True,
- help='Input DEF')
+ Config format:
+ #N|#S|#E|#W
+ pin1_regex (low co-ordinates to high co-ordinates; e.g., bottom to top and left to right)
+ pin2_regex
+ ...
-parser.add_argument('--input-lef', '-l', required=True,
- help='Input LEF')
+ #S|#N|#E|#W
+ """
-parser.add_argument('--output-def', '-o',
- default='output.def', help='Output DEF with new pin placements')
+ def_file_name = input_def
+ lef_file_name = input_lef
+ output_def_file_name = output_def
+ config_file_name = config
+ bus_sort_flag = bus_sort
-parser.add_argument('--config', '-cfg',
- help='Configuration file. See -h for format')
+ #1. Manual Pad Placement - Dinesh A
+ manual_place_flag = False
-parser.add_argument('--ver-layer', '-vl',
- default=3,
- help='Number of metal layer to place the vertical pins on. Defaults to SKY130 metal layer names. 1-based.')
+ h_layer_name = hor_layer
+ v_layer_name = ver_layer
-parser.add_argument('--hor-layer', '-hl',
- default=4,
- help='Number of metal layer to place the horizontal pins on. Defaults to SKY130 metal layer names. 1-based.')
+ h_width_mult = float(hor_width_mult)
+ v_width_mult = float(ver_width_mult)
-parser.add_argument('--hor-width-mult', '-hwm',
- default=2,
- help='')
+ # Initialize OpenDB
+ db_top = odb.dbDatabase.create()
+ odb.read_lef(db_top, lef_file_name)
+ odb.read_def(db_top, def_file_name)
+ block = db_top.getChip().getBlock()
-parser.add_argument('--ver-width-mult', '-vwm',
- default=2,
- help='')
+ micron_in_units = block.getDefUnits()
-parser.add_argument('--length', '-len', type=float,
- default=2,
- help='')
+ LENGTH = int(micron_in_units * length)
-parser.add_argument('--hor-extension', '-hext', type=float,
- default=0.0,
- help='')
+ H_EXTENSION = int(micron_in_units * hor_extension)
+ V_EXTENSION = int(micron_in_units * ver_extension)
-parser.add_argument('--ver-extension', '-vext', type=float,
- default=0.0,
- help='')
+ if H_EXTENSION < 0:
+ H_EXTENSION = 0
-parser.add_argument('--reverse', '-rev',
- choices=['N', 'E', 'S', 'W'],
- nargs='+',
- required=False,
- default=[],
- help='')
+ if V_EXTENSION < 0:
+ V_EXTENSION = 0
-parser.add_argument('--bus-sort', '-bsort', action='store_true',
- default=False,
- help='Sort pins so that bus bits with the same index are grouped'
- 'together. e.g., a[0] b[0] c[0] a[1] b[1] c[1]')
-# TODO
-# width, length, and extension multipliers
+ reverse_arr_raw = reverse.split(",")
+ reverse_arr = []
+ for element in reverse_arr_raw:
+ if element.strip() != "":
+ reverse_arr.append(f"#{element}")
-args = parser.parse_args()
+ def getGrid(origin, count, step):
+ tracks = []
+ pos = origin
+ for i in range(count):
+ tracks.append(pos)
+ pos += step
+ assert len(tracks) > 0
+ tracks.sort()
-def_file_name = args.input_def
-lef_file_name = args.input_lef
-output_def_file_name = args.output_def
-config_file_name = args.config
-bus_sort_flag = args.bus_sort
+ return tracks
-#Manual Pad Placement - Dinesh A
-manual_place_flag = False
+ def equallySpacedSeq(m, arr):
+ seq = []
+ n = len(arr)
+ # Bresenham
+ indices = [i * n // m + n // (2 * m) for i in range(m)]
+ for i in indices:
+ seq.append(arr[i])
+ return seq
-h_layer_index = int(args.hor_layer)
-v_layer_index = int(args.ver_layer)
+ # HUMAN SORTING: https://stackoverflow.com/questions/5967500/how-to-correctly-sort-a-string-with-a-number-inside
+ def natural_keys(enum):
+ def atof(text):
+ try:
+ retval = float(text)
+ except ValueError:
+ retval = text
+ return retval
-h_width_mult = int(args.hor_width_mult)
-v_width_mult = int(args.ver_width_mult)
+ text = enum[0]
+ text = re.sub(r"(\[|\]|\.|\$)", "", text)
+ """
+ alist.sort(key=natural_keys) sorts in human order
+ http://nedbatchelder.com/blog/200712/human_sorting.html
+ (see toothy's implementation in the comments)
+ float regex comes from https://stackoverflow.com/a/12643073/190597
+ """
+ return [
+ atof(c) for c in re.split(r"[+-]?([0-9]+(?:[.][0-9]*)?|[.][0-9]+)", text)
+ ]
-LENGTH = int(1000*args.length)
+ def bus_keys(enum):
+ text = enum[0]
+ m = re.match(r"^.*\[(\d+)\]$", text)
+ if not m:
+ return -1
+ else:
+ return int(m.group(1))
-H_EXTENSION = int(1000*args.hor_extension)
-V_EXTENSION = int(1000*args.ver_extension)
-
-if H_EXTENSION < 0:
- H_EXTENSION = 0
-
-if V_EXTENSION < 0:
- V_EXTENSION = 0
-
-reverse_arr = args.reverse
-reverse_arr = ["#"+rev for rev in reverse_arr]
-
-def getGrid(origin, count, step):
- tracks = []
- pos = origin
- for i in range(count):
- tracks.append(pos)
- pos += step
- assert len(tracks) > 0
- tracks.sort()
-
- return tracks
-
-def equallySpacedSeq(m, arr):
- seq = []
- n = len(arr)
- # Bresenham
- indices = [i*n//m + n//(2*m) for i in range(m)]
- for i in indices:
- seq.append(arr[i])
- return seq
-
-# HUMAN SORTING: https://stackoverflow.com/questions/5967500/how-to-correctly-sort-a-string-with-a-number-inside
-def atof(text):
- try:
- retval = float(text)
- except ValueError:
- retval = text
- return retval
-
-def natural_keys(enum):
- text = enum[0]
- text = re.sub("(\[|\]|\.|\$)", "", text)
- '''
- alist.sort(key=natural_keys) sorts in human order
- http://nedbatchelder.com/blog/200712/human_sorting.html
- (see toothy's implementation in the comments)
- float regex comes from https://stackoverflow.com/a/12643073/190597
- '''
- return [atof(c) for c in re.split(r'[+-]?([0-9]+(?:[.][0-9]*)?|[.][0-9]+)', text)]
-
-def bus_keys(enum):
- text = enum[0]
- m = re.match("^.*\[(\d+)\]$", text)
- if not m:
+ #2. Find the Slot matching next nearest slot-DineshA
+ def findSlot(val, arr):
+ for i in arr:
+ if(i > val):
+ return i
+ print("ERROR: Next Valid Position not found :",val)
return -1
- else:
- return int(m.group(1))
-# Find the Slot matching next nearest slot-DineshA
-def findSlot(val, arr):
- for i in arr:
- if(i > val):
- return i
- print("ERROR: Next Valid Position not found :",val)
- return -1
+ # read config
+ pin_placement_cfg = {"#N": [], "#E": [], "#S": [], "#W": []}
+ cur_side = None
+ if config_file_name is not None and config_file_name != "":
+ with open(config_file_name, "r") as config_file:
+ for line in config_file:
+ line = line.split()
+ if len(line) == 0:
+ continue
-# read config
-
-pin_placement_cfg = {"#N": [], "#E": [], "#S": [], "#W": []}
-cur_side = None
-if config_file_name is not None and config_file_name != "":
- with open(config_file_name, 'r') as config_file:
- for line in config_file:
- line = line.split()
- if len(line) == 0:
- continue
-
- if(manual_place_flag == False):
- if len(line) > 1:
- print("Only one entry allowed per line.")
- sys.exit(1)
-
- token = line[0]
- else:
- #During Manual Place we are allowing Four field
- # <Pad Name> <Offset> <Position> <Multiplier>
- # Causion: Make sure that you have given absolute name, else it will give issue
- if len(line) > 4:
- print("Only Four entry allowed per line.")
- sys.exit(1)
- if line[0] not in ["#N", "#E", "#S", "#W", "#NR", "#ER", "#SR", "#WR"]:
- token = line
- else:
- token = line[0]
-
- if cur_side is not None and token[0] != "#":
- pin_placement_cfg[cur_side].append(token)
- elif token not in ["#N", "#E", "#S", "#W", "#NR", "#ER", "#SR", "#WR", "#BUS_SORT","#MANUAL_PLACE"]:
- print("Invalid token: ",token)
- print("Valid directives are #N, #E, #S, or #W. Append R for reversing the default order.",
- "Use #BUS_SORT to group 'bus bits' by index.",
- "Use #MANUAL_PLACE Manual Placement <padname> <offset> <pin number>.",
- "Please make sure you have set a valid side first before listing pins")
- sys.exit(1)
- elif token == "#BUS_SORT":
- bus_sort_flag = True
- elif token == "#MANUAL_PLACE":
- print("Input token ",token)
- manual_place_flag = True
- else:
- if len(token) == 3:
- token = token[0:2]
- reverse_arr.append(token)
- cur_side = token
-
-# build a list of pins
-
-db_top = odb.dbDatabase.create()
-odb.read_lef(db_top, lef_file_name)
-odb.read_def(db_top, def_file_name)
-
-chip_top = db_top.getChip()
-block_top = chip_top.getBlock()
-top_design_name = block_top.getName()
-tech = db_top.getTech()
-
-H_LAYER = tech.findRoutingLayer(h_layer_index)
-V_LAYER = tech.findRoutingLayer(v_layer_index)
-
-H_WIDTH = h_width_mult * H_LAYER.getWidth()
-V_WIDTH = v_width_mult * V_LAYER.getWidth()
-
-print("Top-level design name:", top_design_name)
-
-bterms = block_top.getBTerms()
-bterms_enum = []
-for bterm in bterms:
- pin_name = bterm.getName()
- bterms_enum.append((pin_name, bterm))
-
-# sort them "humanly"
-bterms_enum.sort(key=natural_keys)
-if bus_sort_flag:
- bterms_enum.sort(key=bus_keys)
-bterms = [bterm[1] for bterm in bterms_enum]
-
-pin_placement = {"#N": [], "#E": [], "#S": [], "#W": []}
-bterm_regex_map = {}
-if(manual_place_flag == False):
- for side in pin_placement_cfg:
- for regex in pin_placement_cfg[side]: # going through them in order
- regex += "$" # anchor
- for bterm in bterms:
- # if a pin name matches multiple regexes, their order will be
- # arbitrary. More refinement requires more strict regexes (or just
- # the exact pin name).
- pin_name = bterm.getName()
- if re.match(regex, pin_name) is not None:
- if bterm in bterm_regex_map:
- print("Warning: Multiple regexes matched", pin_name,
- ". Those are", bterm_regex_map[bterm], "and", regex)
- print("Only the first one is taken into consideration.")
- continue
- # sys.exit(1)
- bterm_regex_map[bterm] = regex
- pin_placement[side].append(bterm) # to maintain the order
-
- unmatched_bterms = [bterm for bterm in bterms if bterm not in bterm_regex_map]
-
- if len(unmatched_bterms) > 0:
- print("Warning: Some pins weren't matched by the config file")
- print("Those are:", [bterm.getName() for bterm in unmatched_bterms])
- if True:
- print("Assigning random sides to the above pins")
- for bterm in unmatched_bterms:
- random_side = random.choice(list(pin_placement.keys()))
- pin_placement[random_side].append(bterm)
- else:
- sys.exit(1)
-else:
- for side in pin_placement_cfg:
- for regex in pin_placement_cfg[side]: # going through them in order
- regex = regex[0] # take first value
- regex += "$" # anchor
- for bterm in bterms:
- # if a pin name matches multiple regexes, their order will be
- # arbitrary. More refinement requires more strict regexes (or just
- # the exact pin name).
- pin_name = bterm.getName()
- if re.match(regex, pin_name) is not None:
- print("Debug: Serching Pin match",regex)
- if bterm in bterm_regex_map:
- #print("Warning: Multiple regexes matched", pin_name)
- # ". Those are", bterm_regex_map[bterm], "and", regex)
+ #3. Dinesh A - Start
+ if(manual_place_flag == False):
+ if len(line) > 1:
+ print("Only one entry allowed per line.")
sys.exit(1)
- bterm_regex_map[bterm] = regex
- pin_placement[side].append(bterm) # to maintain the order
-
- unmatched_bterms = [bterm for bterm in bterms if bterm not in bterm_regex_map]
-
- if len(unmatched_bterms) > 0:
- print("Warning: Some pins weren't matched by the config file")
- print("Those are:", [bterm.getName() for bterm in unmatched_bterms])
- sys.exit(1)
-
-
-assert len(block_top.getBTerms()) == len(pin_placement["#N"] + pin_placement["#E"] + pin_placement["#S"] + pin_placement["#W"])
-
-# generate slots
-
-
-DIE_AREA = block_top.getDieArea()
-BLOCK_LL_X = DIE_AREA.xMin()
-BLOCK_LL_Y = DIE_AREA.yMin()
-BLOCK_UR_X = DIE_AREA.xMax()
-BLOCK_UR_Y = DIE_AREA.yMax()
-
-print("Block boundaries:", BLOCK_LL_X, BLOCK_LL_Y, BLOCK_UR_X, BLOCK_UR_Y)
-
-
-origin, count, step = block_top.findTrackGrid(H_LAYER).getGridPatternY(0)
-
-# Save the horizontal origin and step - DineshA
-h_origin = origin
-h_step = step
-
-h_tracks = getGrid(origin, count, step)
-
-origin, count, step = block_top.findTrackGrid(V_LAYER).getGridPatternX(0)
-
-# Save the horizontal origin and step - DineshA
-v_origin = origin
-v_step = step
-
-v_tracks = getGrid(origin, count, step)
-
-for rev in reverse_arr:
- pin_placement[rev].reverse()
-
-if(manual_place_flag == False):
- # create the pins
- # old logic
- for side in pin_placement:
- start = 0
- if side in ["#N", "#S"]:
- slots = equallySpacedSeq(len(pin_placement[side]), v_tracks)
- else:
- slots = equallySpacedSeq(len(pin_placement[side]), h_tracks)
-
- assert len(slots) == len(pin_placement[side])
-
- for i in range(len(pin_placement[side])):
- bterm = pin_placement[side][i]
- slot = slots[i]
-
- pin_name = bterm.getName()
- pins = bterm.getBPins()
- if len(pins) > 0:
- print("Warning:", pin_name, "already has shapes. Modifying them")
- assert len(pins) == 1
- pin_bpin = pins[0]
- else:
- pin_bpin = odb.dbBPin_create(bterm)
-
- print("Dinesh: Placing Pad:" ,pin_name, " At Side: ", side, " Slot: ", slot)
- pin_bpin.setPlacementStatus("PLACED")
-
- if side in ["#N", "#S"]:
- rect = odb.Rect(0, 0, V_WIDTH, LENGTH+V_EXTENSION)
- if side == "#N":
- y = BLOCK_UR_Y-LENGTH
+ token = line[0]
else:
- y = BLOCK_LL_Y-V_EXTENSION
- rect.moveTo(slot-V_WIDTH//2, y)
- odb.dbBox_create(pin_bpin, V_LAYER, *rect.ll(), *rect.ur())
- else:
- rect = odb.Rect(0, 0, LENGTH+H_EXTENSION, H_WIDTH)
- if side == "#E":
- x = BLOCK_UR_X-LENGTH
+ #During Manual Place we are allowing Four field
+ # <Pad Name> <Offset> <Position> <Multiplier>
+ # Causion: Make sure that you have given absolute name, else it will give issue
+ if len(line) > 4:
+ print("Only Four entry allowed per line.")
+ sys.exit(1)
+ if line[0] not in ["#N", "#E", "#S", "#W", "#NR", "#ER", "#SR", "#WR"]:
+ token = line
+ else:
+ token = line[0]
+
+ if cur_side is not None and token[0] != "#":
+ pin_placement_cfg[cur_side].append(token)
+ elif token not in [
+ "#N",
+ "#E",
+ "#S",
+ "#W",
+ "#NR",
+ "#ER",
+ "#SR",
+ "#WR",
+ "#BUS_SORT",
+ "#MANUAL_PLACE"
+ ]:
+ print(
+ "Valid directives are #N, #E, #S, or #W. Append R for reversing the default order.",
+ "Use #BUS_SORT to group 'bus bits' by index.",
+ "Please make sure you have set a valid side first before listing pins",
+ )
+ sys.exit(1)
+ elif token == "#BUS_SORT":
+ bus_sort_flag = True
+ #4 - Dinesh A
+ elif token == "#MANUAL_PLACE":
+ print("Input token ",token)
+ manual_place_flag = True
else:
- x = BLOCK_LL_X-H_EXTENSION
- rect.moveTo(x, slot-H_WIDTH//2)
- odb.dbBox_create(pin_bpin, H_LAYER, *rect.ll(), *rect.ur())
-else:
- #New Logic, Manual Pin Placement - Dinesh A
- #print("Allowed VTracks",v_tracks)
- #print("Allowed hTracks",h_tracks)
+ if len(token) == 3:
+ token = token[0:2]
+ reverse_arr.append(token)
+ cur_side = token
- for side in pin_placement:
+ # build a list of pins
- if(len(pin_placement[side]) != len(pin_placement_cfg[side])):
- print("ERROR : At Side:", side, " Total Pin Defined ",len(pin_placement_cfg[side]), "More than available:",len(pin_placement[side]))
-
- #check defined pad are more than avaibale one
- assert len(pin_placement[side]) == len(pin_placement_cfg[side])
- start = 0
-
- start_loc = 0
- pad_pos = 0
- slot_pre = 0
- #Dinesh: Give Step Multipler size *2 for better pad placement
- multiplier= 2
- for i in range(len(pin_placement_cfg[side])):
- #Dinesh: Multiply the offset by 1000 for micro conversion
- if(len(pin_placement_cfg[side][i]) > 1):
- start_loc = int(pin_placement_cfg[side][i][1])
- if(len(pin_placement_cfg[side][i]) > 2):
- pad_pos = int(pin_placement_cfg[side][i][2])
- if(len(pin_placement_cfg[side][i]) > 3):
- multiplier = int(pin_placement_cfg[side][i][3])
+ chip_top = db_top.getChip()
+ block_top = chip_top.getBlock()
+ top_design_name = block_top.getName()
+ tech = db_top.getTech()
- if side in ["#N", "#S"]:
- slott = start_loc*1000+int(v_origin)+(int(v_step) * pad_pos * multiplier)
- slot =findSlot(slott,v_tracks)
- else:
- slott = start_loc*1000+int(h_origin)+(int(h_step) * pad_pos * multiplier)
- slot =findSlot(slott,h_tracks)
-
- pad_pos +=1
- bterm = pin_placement[side][i]
-
- pin_name = bterm.getName()
- pins = bterm.getBPins()
- if len(pins) > 0:
- print("Warning:", pin_name, "already has shapes. Modifying them")
- assert len(pins) == 1
- pin_bpin = pins[0]
- else:
- pin_bpin = odb.dbBPin_create(bterm)
+ H_LAYER = tech.findLayer(h_layer_name)
+ V_LAYER = tech.findLayer(v_layer_name)
- if(slot < slot_pre):
- print("ERROR:", "Current Pad:", pin_name, " Slot:" , slot, " is less than Previous Slot:",slot_pre)
+ H_WIDTH = int(h_width_mult * H_LAYER.getWidth())
+ V_WIDTH = int(v_width_mult * V_LAYER.getWidth())
+
+ print("Top-level design name:", top_design_name)
+
+ bterms = block_top.getBTerms()
+ bterms_enum = []
+ for bterm in bterms:
+ pin_name = bterm.getName()
+ bterms_enum.append((pin_name, bterm))
+
+ # sort them "humanly"
+ bterms_enum.sort(key=natural_keys)
+ if bus_sort_flag:
+ bterms_enum.sort(key=bus_keys)
+ bterms = [bterm[1] for bterm in bterms_enum]
+
+ pin_placement = {"#N": [], "#E": [], "#S": [], "#W": []}
+ bterm_regex_map = {}
+ #5. Dinesh A
+ if(manual_place_flag == False):
+ for side in pin_placement_cfg:
+ for regex in pin_placement_cfg[side]: # going through them in order
+ regex += "$" # anchor
+ for bterm in bterms:
+ # if a pin name matches multiple regexes, their order will be
+ # arbitrary. More refinement requires more strict regexes (or just
+ # the exact pin name).
+ pin_name = bterm.getName()
+ if re.match(regex, pin_name) is not None:
+ if bterm in bterm_regex_map:
+ print(
+ "Error: Multiple regexes matched",
+ pin_name,
+ ". Those are",
+ bterm_regex_map[bterm],
+ "and",
+ regex,
+ )
+ sys.exit(os.EX_DATAERR)
+ bterm_regex_map[bterm] = regex
+ pin_placement[side].append(bterm) # to maintain the order
+
+ unmatched_bterms = [bterm for bterm in bterms if bterm not in bterm_regex_map]
+
+ if len(unmatched_bterms) > 0:
+ print("Warning: Some pins weren't matched by the config file")
+ print("Those are:", [bterm.getName() for bterm in unmatched_bterms])
+ if True:
+ print("Assigning random sides to the above pins")
+ for bterm in unmatched_bterms:
+ random_side = random.choice(list(pin_placement.keys()))
+ pin_placement[random_side].append(bterm)
+ else:
+ sys.exit(1)
+
+ #6 Dinesh A
+ else:
+ for side in pin_placement_cfg:
+ for regex in pin_placement_cfg[side]: # going through them in order
+ regex = regex[0] # take first value
+ regex += "$" # anchor
+ for bterm in bterms:
+ # if a pin name matches multiple regexes, their order will be
+ # arbitrary. More refinement requires more strict regexes (or just
+ # the exact pin name).
+ pin_name = bterm.getName()
+ if re.match(regex, pin_name) is not None:
+ print("Debug: Serching Pin match",regex)
+ if bterm in bterm_regex_map:
+ #print("Warning: Multiple regexes matched", pin_name)
+ # ". Those are", bterm_regex_map[bterm], "and", regex)
+ sys.exit(1)
+ bterm_regex_map[bterm] = regex
+ pin_placement[side].append(bterm) # to maintain the order
+
+ unmatched_bterms = [bterm for bterm in bterms if bterm not in bterm_regex_map]
+
+ if len(unmatched_bterms) > 0:
+ print("Warning: Some pins weren't matched by the config file")
+ print("Those are:", [bterm.getName() for bterm in unmatched_bterms])
sys.exit(1)
- slot_pre = slot
- print("Dinesh: Placing Pad:" ,pin_name, " At Side: ", side, " Slot: ", slot)
- pin_bpin.setPlacementStatus("PLACED")
-
- if side in ["#N", "#S"]:
- rect = odb.Rect(0, 0, V_WIDTH, LENGTH+V_EXTENSION)
- if side == "#N":
- y = BLOCK_UR_Y-LENGTH
- else:
- y = BLOCK_LL_Y-V_EXTENSION
- rect.moveTo(slot-V_WIDTH//2, y)
- odb.dbBox_create(pin_bpin, V_LAYER, *rect.ll(), *rect.ur())
- else:
- rect = odb.Rect(0, 0, LENGTH+H_EXTENSION, H_WIDTH)
- if side == "#E":
- x = BLOCK_UR_X-LENGTH
- else:
- x = BLOCK_LL_X-H_EXTENSION
- rect.moveTo(x, slot-H_WIDTH//2)
- odb.dbBox_create(pin_bpin, H_LAYER, *rect.ll(), *rect.ur())
-
+ assert len(block_top.getBTerms()) == len(
+ pin_placement["#N"]
+ + pin_placement["#E"]
+ + pin_placement["#S"]
+ + pin_placement["#W"]
+ )
-print("Writing", output_def_file_name)
-odb.write_def(block_top, output_def_file_name)
+ # generate slots
+
+ DIE_AREA = block_top.getDieArea()
+ BLOCK_LL_X = DIE_AREA.xMin()
+ BLOCK_LL_Y = DIE_AREA.yMin()
+ BLOCK_UR_X = DIE_AREA.xMax()
+ BLOCK_UR_Y = DIE_AREA.yMax()
+
+ print("Block boundaries:", BLOCK_LL_X, BLOCK_LL_Y, BLOCK_UR_X, BLOCK_UR_Y)
+
+ origin, count, step = block_top.findTrackGrid(H_LAYER).getGridPatternY(0)
+
+ #7. Save the horizontal origin and step - DineshA
+ h_origin = origin
+ h_step = step
+
+ h_tracks = getGrid(origin, count, step)
+
+ origin, count, step = block_top.findTrackGrid(V_LAYER).getGridPatternX(0)
+
+ #8. Save the horizontal origin and step - DineshA
+ v_origin = origin
+ v_step = step
+
+ v_tracks = getGrid(origin, count, step)
+
+ for rev in reverse_arr:
+ pin_placement[rev].reverse()
+
+ # create the pins
+ #9. DineshA
+ if(manual_place_flag == False):
+ for side in pin_placement:
+ if side in ["#N", "#S"]:
+ slots = equallySpacedSeq(len(pin_placement[side]), v_tracks)
+ else:
+ slots = equallySpacedSeq(len(pin_placement[side]), h_tracks)
+
+ assert len(slots) == len(pin_placement[side])
+
+ for i in range(len(pin_placement[side])):
+ bterm = pin_placement[side][i]
+ slot = slots[i]
+
+ pin_name = bterm.getName()
+ pins = bterm.getBPins()
+ if len(pins) > 0:
+ print("Warning:", pin_name, "already has shapes. Modifying them")
+ assert len(pins) == 1
+ pin_bpin = pins[0]
+ else:
+ pin_bpin = odb.dbBPin_create(bterm)
+
+ pin_bpin.setPlacementStatus("PLACED")
+
+ if side in ["#N", "#S"]:
+ rect = odb.Rect(0, 0, V_WIDTH, LENGTH + V_EXTENSION)
+ if side == "#N":
+ y = BLOCK_UR_Y - LENGTH
+ else:
+ y = BLOCK_LL_Y - V_EXTENSION
+ rect.moveTo(slot - V_WIDTH // 2, y)
+ odb.dbBox_create(pin_bpin, V_LAYER, *rect.ll(), *rect.ur())
+ else:
+ rect = odb.Rect(0, 0, LENGTH + H_EXTENSION, H_WIDTH)
+ if side == "#E":
+ x = BLOCK_UR_X - LENGTH
+ else:
+ x = BLOCK_LL_X - H_EXTENSION
+ rect.moveTo(x, slot - H_WIDTH // 2)
+ odb.dbBox_create(pin_bpin, H_LAYER, *rect.ll(), *rect.ur())
+
+ else:
+ #10.New Logic, Manual Pin Placement - Dinesh A
+ #print("Allowed VTracks",v_tracks)
+ #print("Allowed hTracks",h_tracks)
+
+ for side in pin_placement:
+
+ if(len(pin_placement[side]) != len(pin_placement_cfg[side])):
+ print("ERROR : At Side:", side, " Total Pin Defined ",len(pin_placement_cfg[side]), "More than available:",len(pin_placement[side]))
+ for regex in pin_placement_cfg[side]:
+ regex = regex[0] # take first value
+ print("Pins in pin_placement_cfg: " , regex)
+ for regex in pin_placement[side]:
+ print("Pins in pin_placement: " , regex)
+
+
+ #check defined pad are more than avaibale one
+ assert len(pin_placement[side]) == len(pin_placement_cfg[side])
+ start = 0
+
+ start_loc = 0
+ pad_pos = 0
+ slot_pre = 0
+ #Dinesh: Give Step Multipler size *2 for better pad placement
+ multiplier= 2
+ for i in range(len(pin_placement_cfg[side])):
+ #Dinesh: Multiply the offset by 1000 for micro conversion
+ if(len(pin_placement_cfg[side][i]) > 1):
+ start_loc = int(pin_placement_cfg[side][i][1])
+ if(len(pin_placement_cfg[side][i]) > 2):
+ pad_pos = int(pin_placement_cfg[side][i][2])
+ if(len(pin_placement_cfg[side][i]) > 3):
+ multiplier = int(pin_placement_cfg[side][i][3])
+
+ if side in ["#N", "#S"]:
+ slott = start_loc*1000+int(v_origin)+(int(v_step) * pad_pos * multiplier)
+ slot =findSlot(slott,v_tracks)
+ else:
+ slott = start_loc*1000+int(h_origin)+(int(h_step) * pad_pos * multiplier)
+ slot =findSlot(slott,h_tracks)
+
+ pad_pos +=1
+ bterm = pin_placement[side][i]
+
+ pin_name = bterm.getName()
+ pins = bterm.getBPins()
+ if len(pins) > 0:
+ print("Warning:", pin_name, "already has shapes. Modifying them")
+ assert len(pins) == 1
+ pin_bpin = pins[0]
+ else:
+ pin_bpin = odb.dbBPin_create(bterm)
+
+ if(slot < slot_pre):
+ print("ERROR:", "Current Pad:", pin_name, " Slot:" , slot, " is less than Previous One:",slot_pre)
+ sys.exit(1)
+
+ slot_pre = slot
+
+ print("Dinesh: Placing Pad:" ,pin_name, " At Side: ", side, " Slot: ", slot)
+ pin_bpin.setPlacementStatus("PLACED")
+
+ if side in ["#N", "#S"]:
+ rect = odb.Rect(0, 0, V_WIDTH, LENGTH+V_EXTENSION)
+ if side == "#N":
+ y = BLOCK_UR_Y-LENGTH
+ else:
+ y = BLOCK_LL_Y-V_EXTENSION
+ rect.moveTo(slot-V_WIDTH//2, y)
+ odb.dbBox_create(pin_bpin, V_LAYER, *rect.ll(), *rect.ur())
+ else:
+ rect = odb.Rect(0, 0, LENGTH+H_EXTENSION, H_WIDTH)
+ if side == "#E":
+ x = BLOCK_UR_X-LENGTH
+ else:
+ x = BLOCK_LL_X-H_EXTENSION
+ rect.moveTo(x, slot-H_WIDTH//2)
+ odb.dbBox_create(pin_bpin, H_LAYER, *rect.ll(), *rect.ur())
+
+
+ print(
+ f"Writing {output_def_file_name}...",
+ )
+ odb.write_def(block_top, output_def_file_name)
+
+
+if __name__ == "__main__":
+ cli()
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index ce6c000..25a4a16 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl
@@ -49,7 +49,9 @@
$script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv \
$script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv \
$script_dir/../../verilog/rtl/lib/ser_inf_32b.sv \
- $script_dir/../../verilog/rtl/lib/registers.v"
+ $script_dir/../../verilog/rtl/lib/registers.v \
+ $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
+ "
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -94,7 +96,7 @@
set ::env(FP_PDN_VWIDTH) 5
set ::env(FP_PDN_HWIDTH) 5
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/pinmux/interactive.tcl b/openlane/pinmux/interactive.tcl
deleted file mode 100644
index b44b517..0000000
--- a/openlane/pinmux/interactive.tcl
+++ /dev/null
@@ -1,219 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
- # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
- # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
- # set_def $pdndef
- if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
- set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
- }
-
- run_placement
-}
-
-proc run_cts_step {args} {
- # set_def $::env(opendp_result_file_tag).def
- if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
- set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
- }
-
- run_cts
- run_resizer_timing
-}
-
-proc run_routing_step {args} {
- # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
- # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
- # set_def $resizerdef
- if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
- set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
- }
- run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
- set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
- }
- if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
- run_antenna_check
- heal_antenna_violators; # modifies the routed DEF
- }
-
-}
-
-proc run_power_pins_insertion_step {args} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
- set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
- }
- if { $::env(LVS_INSERT_POWER_PINS) } {
- write_powered_verilog
- set_netlist $::env(lvs_result_file_tag).powered.v
- }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
- set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
- }
- if { $lvs_enabled } {
- run_magic_spice_export
- run_lvs; # requires run_magic_spice_export
- }
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
- if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
- set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
- }
- if { $drc_enabled } {
- run_magic_drc
- run_klayout_drc
- }
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
- if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
- set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
- }
- if { $antenna_check_enabled } {
- run_antenna_check
- }
-}
-
-proc run_flow {args} {
- set script_dir [file dirname [file normalize [info script]]]
-
- set options {
- {-design required}
- {-save_path optional}
- {-no_lvs optional}
- {-no_drc optional}
- {-no_antennacheck optional}
- }
- set flags {-save}
- parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
- prep {*}$args
-
- set LVS_ENABLED 1
- set DRC_ENABLED 0
- set ANTENNACHECK_ENABLED 1
-
- set steps [dict create "synthesis" {run_synthesis "" } \
- "floorplan" {run_floorplan ""} \
- "placement" {run_placement_step ""} \
- "cts" {run_cts_step ""} \
- "routing" {run_routing_step ""}\
- "diode_insertion" {run_diode_insertion_2_5_step ""} \
- "power_pins_insertion" {run_power_pins_insertion_step ""} \
- "gds_magic" {run_magic ""} \
- "gds_drc_klayout" {run_klayout ""} \
- "gds_xor_klayout" {run_klayout_gds_xor ""} \
- "lvs" "run_lvs_step $LVS_ENABLED" \
- "drc" "run_drc_step $DRC_ENABLED" \
- "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
- "cvc" {run_lef_cvc}
- ]
-
- set_if_unset arg_values(-to) "cvc";
-
- if { [info exists ::env(CURRENT_STEP) ] } {
- puts "\[INFO\]:Picking up where last execution left off"
- puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
- } else {
- set ::env(CURRENT_STEP) "synthesis";
- }
- set_if_unset arg_values(-from) $::env(CURRENT_STEP);
- set exe 0;
- dict for {step_name step_exe} $steps {
- if { [ string equal $arg_values(-from) $step_name ] } {
- set exe 1;
- }
-
- if { $exe } {
- # For when it fails
- set ::env(CURRENT_STEP) $step_name
- [lindex $step_exe 0] [lindex $step_exe 1] ;
- }
-
- if { [ string equal $arg_values(-to) $step_name ] } {
- set exe 0:
- break;
- }
-
- }
-
- # for when it resumes
- set steps_as_list [dict keys $steps]
- set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
- set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
- if { [info exists flags_map(-save) ] } {
- if { ! [info exists arg_values(-save_path)] } {
- set arg_values(-save_path) ""
- }
- save_views -lef_path $::env(magic_result_file_tag).lef \
- -def_path $::env(CURRENT_DEF) \
- -gds_path $::env(magic_result_file_tag).gds \
- -mag_path $::env(magic_result_file_tag).mag \
- -maglef_path $::env(magic_result_file_tag).lef.mag \
- -spice_path $::env(magic_result_file_tag).spice \
- -spef_path $::env(CURRENT_SPEF) \
- -verilog_path $::env(CURRENT_NETLIST) \
- -save_path $arg_values(-save_path) \
- -tag $::env(RUN_TAG)
- }
-
-
- calc_total_runtime
- save_state
- generate_final_summary_report
-
- check_timing_violations
-
- puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg
index ffdf50f..42c2cac 100644
--- a/openlane/pinmux/pin_order.cfg
+++ b/openlane/pinmux/pin_order.cfg
@@ -3,6 +3,16 @@
#S
h_reset_n 000 0 2
+cpu_core_rst_n\[1\]
+cpu_core_rst_n\[0\]
+cpu_intf_rst_n
+qspim_rst_n
+sspim_rst_n
+uart_rst_n
+i2cm_rst_n
+usb_rst_n
+cfg_riscv_debug_sel\[1\]
+cfg_riscv_debug_sel\[0\]
user_irq\[0\]
user_irq\[1\]
user_irq\[2\]
@@ -63,40 +73,6 @@
pinmux_debug\[31\]
#W
-bist_error_cnt3\[3\] 000 0 2
-bist_error_cnt3\[2\]
-bist_error_cnt3\[1\]
-bist_error_cnt3\[0\]
-bist_correct\[3\]
-bist_error\[3\]
-
-bist_error_cnt2\[3\]
-bist_error_cnt2\[2\]
-bist_error_cnt2\[1\]
-bist_error_cnt2\[0\]
-bist_correct\[2\]
-bist_error\[2\]
-
-bist_error_cnt1\[3\]
-bist_error_cnt1\[2\]
-bist_error_cnt1\[1\]
-bist_error_cnt1\[0\]
-bist_correct\[1\]
-bist_error\[1\]
-
-bist_error_cnt0\[3\]
-bist_error_cnt0\[2\]
-bist_error_cnt0\[1\]
-bist_error_cnt0\[0\]
-bist_correct\[0\]
-bist_error\[0\]
-bist_done
-bist_sdo
-bist_shift
-bist_sdi
-bist_load
-bist_run
-bist_en
soft_irq
irq_lines\[15\]
diff --git a/openlane/qspim/config.tcl b/openlane/qspim/config.tcl
index dd9596a..129e657 100755
--- a/openlane/qspim/config.tcl
+++ b/openlane/qspim/config.tcl
@@ -93,7 +93,7 @@
set ::env(FP_PDN_VWIDTH) 5
set ::env(FP_PDN_HWIDTH) 5
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/qspim/interactive.tcl b/openlane/qspim/interactive.tcl
deleted file mode 100644
index b44b517..0000000
--- a/openlane/qspim/interactive.tcl
+++ /dev/null
@@ -1,219 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
- # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
- # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
- # set_def $pdndef
- if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
- set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
- }
-
- run_placement
-}
-
-proc run_cts_step {args} {
- # set_def $::env(opendp_result_file_tag).def
- if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
- set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
- }
-
- run_cts
- run_resizer_timing
-}
-
-proc run_routing_step {args} {
- # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
- # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
- # set_def $resizerdef
- if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
- set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
- }
- run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
- set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
- }
- if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
- run_antenna_check
- heal_antenna_violators; # modifies the routed DEF
- }
-
-}
-
-proc run_power_pins_insertion_step {args} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
- set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
- }
- if { $::env(LVS_INSERT_POWER_PINS) } {
- write_powered_verilog
- set_netlist $::env(lvs_result_file_tag).powered.v
- }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
- set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
- }
- if { $lvs_enabled } {
- run_magic_spice_export
- run_lvs; # requires run_magic_spice_export
- }
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
- if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
- set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
- }
- if { $drc_enabled } {
- run_magic_drc
- run_klayout_drc
- }
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
- if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
- set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
- }
- if { $antenna_check_enabled } {
- run_antenna_check
- }
-}
-
-proc run_flow {args} {
- set script_dir [file dirname [file normalize [info script]]]
-
- set options {
- {-design required}
- {-save_path optional}
- {-no_lvs optional}
- {-no_drc optional}
- {-no_antennacheck optional}
- }
- set flags {-save}
- parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
- prep {*}$args
-
- set LVS_ENABLED 1
- set DRC_ENABLED 0
- set ANTENNACHECK_ENABLED 1
-
- set steps [dict create "synthesis" {run_synthesis "" } \
- "floorplan" {run_floorplan ""} \
- "placement" {run_placement_step ""} \
- "cts" {run_cts_step ""} \
- "routing" {run_routing_step ""}\
- "diode_insertion" {run_diode_insertion_2_5_step ""} \
- "power_pins_insertion" {run_power_pins_insertion_step ""} \
- "gds_magic" {run_magic ""} \
- "gds_drc_klayout" {run_klayout ""} \
- "gds_xor_klayout" {run_klayout_gds_xor ""} \
- "lvs" "run_lvs_step $LVS_ENABLED" \
- "drc" "run_drc_step $DRC_ENABLED" \
- "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
- "cvc" {run_lef_cvc}
- ]
-
- set_if_unset arg_values(-to) "cvc";
-
- if { [info exists ::env(CURRENT_STEP) ] } {
- puts "\[INFO\]:Picking up where last execution left off"
- puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
- } else {
- set ::env(CURRENT_STEP) "synthesis";
- }
- set_if_unset arg_values(-from) $::env(CURRENT_STEP);
- set exe 0;
- dict for {step_name step_exe} $steps {
- if { [ string equal $arg_values(-from) $step_name ] } {
- set exe 1;
- }
-
- if { $exe } {
- # For when it fails
- set ::env(CURRENT_STEP) $step_name
- [lindex $step_exe 0] [lindex $step_exe 1] ;
- }
-
- if { [ string equal $arg_values(-to) $step_name ] } {
- set exe 0:
- break;
- }
-
- }
-
- # for when it resumes
- set steps_as_list [dict keys $steps]
- set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
- set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
- if { [info exists flags_map(-save) ] } {
- if { ! [info exists arg_values(-save_path)] } {
- set arg_values(-save_path) ""
- }
- save_views -lef_path $::env(magic_result_file_tag).lef \
- -def_path $::env(CURRENT_DEF) \
- -gds_path $::env(magic_result_file_tag).gds \
- -mag_path $::env(magic_result_file_tag).mag \
- -maglef_path $::env(magic_result_file_tag).lef.mag \
- -spice_path $::env(magic_result_file_tag).spice \
- -spef_path $::env(CURRENT_SPEF) \
- -verilog_path $::env(CURRENT_NETLIST) \
- -save_path $arg_values(-save_path) \
- -tag $::env(RUN_TAG)
- }
-
-
- calc_total_runtime
- save_state
- generate_final_summary_report
-
- check_timing_violations
-
- puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/uart_i2cm_usb_spi/config.tcl b/openlane/uart_i2cm_usb_spi/config.tcl
index fa19eff..026ba3c 100644
--- a/openlane/uart_i2cm_usb_spi/config.tcl
+++ b/openlane/uart_i2cm_usb_spi/config.tcl
@@ -114,7 +114,7 @@
set ::env(FP_PDN_VWIDTH) 5
set ::env(FP_PDN_HWIDTH) 5
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/uart_i2cm_usb_spi/interactive.tcl b/openlane/uart_i2cm_usb_spi/interactive.tcl
deleted file mode 100644
index b44b517..0000000
--- a/openlane/uart_i2cm_usb_spi/interactive.tcl
+++ /dev/null
@@ -1,219 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
- # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
- # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
- # set_def $pdndef
- if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
- set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
- }
-
- run_placement
-}
-
-proc run_cts_step {args} {
- # set_def $::env(opendp_result_file_tag).def
- if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
- set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
- }
-
- run_cts
- run_resizer_timing
-}
-
-proc run_routing_step {args} {
- # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
- # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
- # set_def $resizerdef
- if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
- set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
- }
- run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
- set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
- }
- if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
- run_antenna_check
- heal_antenna_violators; # modifies the routed DEF
- }
-
-}
-
-proc run_power_pins_insertion_step {args} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
- set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
- }
- if { $::env(LVS_INSERT_POWER_PINS) } {
- write_powered_verilog
- set_netlist $::env(lvs_result_file_tag).powered.v
- }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
- set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
- }
- if { $lvs_enabled } {
- run_magic_spice_export
- run_lvs; # requires run_magic_spice_export
- }
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
- if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
- set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
- }
- if { $drc_enabled } {
- run_magic_drc
- run_klayout_drc
- }
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
- if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
- set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
- }
- if { $antenna_check_enabled } {
- run_antenna_check
- }
-}
-
-proc run_flow {args} {
- set script_dir [file dirname [file normalize [info script]]]
-
- set options {
- {-design required}
- {-save_path optional}
- {-no_lvs optional}
- {-no_drc optional}
- {-no_antennacheck optional}
- }
- set flags {-save}
- parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
- prep {*}$args
-
- set LVS_ENABLED 1
- set DRC_ENABLED 0
- set ANTENNACHECK_ENABLED 1
-
- set steps [dict create "synthesis" {run_synthesis "" } \
- "floorplan" {run_floorplan ""} \
- "placement" {run_placement_step ""} \
- "cts" {run_cts_step ""} \
- "routing" {run_routing_step ""}\
- "diode_insertion" {run_diode_insertion_2_5_step ""} \
- "power_pins_insertion" {run_power_pins_insertion_step ""} \
- "gds_magic" {run_magic ""} \
- "gds_drc_klayout" {run_klayout ""} \
- "gds_xor_klayout" {run_klayout_gds_xor ""} \
- "lvs" "run_lvs_step $LVS_ENABLED" \
- "drc" "run_drc_step $DRC_ENABLED" \
- "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
- "cvc" {run_lef_cvc}
- ]
-
- set_if_unset arg_values(-to) "cvc";
-
- if { [info exists ::env(CURRENT_STEP) ] } {
- puts "\[INFO\]:Picking up where last execution left off"
- puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
- } else {
- set ::env(CURRENT_STEP) "synthesis";
- }
- set_if_unset arg_values(-from) $::env(CURRENT_STEP);
- set exe 0;
- dict for {step_name step_exe} $steps {
- if { [ string equal $arg_values(-from) $step_name ] } {
- set exe 1;
- }
-
- if { $exe } {
- # For when it fails
- set ::env(CURRENT_STEP) $step_name
- [lindex $step_exe 0] [lindex $step_exe 1] ;
- }
-
- if { [ string equal $arg_values(-to) $step_name ] } {
- set exe 0:
- break;
- }
-
- }
-
- # for when it resumes
- set steps_as_list [dict keys $steps]
- set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
- set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
- if { [info exists flags_map(-save) ] } {
- if { ! [info exists arg_values(-save_path)] } {
- set arg_values(-save_path) ""
- }
- save_views -lef_path $::env(magic_result_file_tag).lef \
- -def_path $::env(CURRENT_DEF) \
- -gds_path $::env(magic_result_file_tag).gds \
- -mag_path $::env(magic_result_file_tag).mag \
- -maglef_path $::env(magic_result_file_tag).lef.mag \
- -spice_path $::env(magic_result_file_tag).spice \
- -spef_path $::env(CURRENT_SPEF) \
- -verilog_path $::env(CURRENT_NETLIST) \
- -save_path $arg_values(-save_path) \
- -tag $::env(RUN_TAG)
- }
-
-
- calc_total_runtime
- save_state
- generate_final_summary_report
-
- check_timing_violations
-
- puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 2895ec4..4ca67f1 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -44,8 +44,10 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
+ $proj_dir/../../verilog/rtl//yifive/ycr2c/src/top/ycr2_top_wb.sv \
$proj_dir/../../verilog/rtl/user_project_wrapper.v"
+
## Clock configurations
set ::env(CLOCK_PORT) "user_clock2 wb_clk_i"
#set ::env(CLOCK_NET) "mprj.clk"
@@ -66,43 +68,43 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
- $proj_dir/../../verilog/gl/qspim.v \
+ $proj_dir/../../verilog/gl/qspim_top.v \
$proj_dir/../../verilog/gl/wb_interconnect.v \
$proj_dir/../../verilog/gl/pinmux.v \
- $proj_dir/../../verilog/gl/mbist_wrapper.v \
$proj_dir/../../verilog/gl/uart_i2cm_usb_spi.v \
$proj_dir/../../verilog/gl/wb_host.v \
- $proj_dir/../../verilog/gl/yifive.v \
- $proj_dir/../../verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+ $proj_dir/../../verilog/gl/ycr2_mintf.v \
+ $proj_dir/../../verilog/gl/ycr_core_top.v \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
"
set ::env(EXTRA_LEFS) "\
- $lef_root/qspim.lef \
+ $lef_root/qspim_top.lef \
$lef_root/pinmux.lef \
$lef_root/wb_interconnect.lef \
$lef_root/uart_i2cm_usb_spi.lef \
$lef_root/wb_host.lef \
- $lef_root/mbist_wrapper.lef \
- $lef_root/yifive.lef \
- $lef_root/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+ $lef_root/ycr2_mintf.lef \
+ $lef_root/ycr_core_top.lef \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
"
set ::env(EXTRA_GDS_FILES) "\
- $gds_root/qspim.gds \
+ $gds_root/qspim_top.gds \
$gds_root/pinmux.gds \
$gds_root/wb_interconnect.gds \
$gds_root/uart_i2cm_usb_spi.gds \
$gds_root/wb_host.gds \
- $gds_root/mbist_wrapper.gds \
- $gds_root/yifive.gds \
- $gds_root/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
+ $gds_root/ycr2_mintf.gds \
+ $gds_root/ycr_core_top.gds \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-#set ::env(VERILOG_INCLUDE_DIRS) [glob $proj_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ]
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met5}
set ::env(FP_PDN_CHECK_NODES) 0
@@ -118,57 +120,43 @@
set ::env(VDD_PIN) "vccd1"
set ::env(GND_PIN) "vssd1"
-set ::env(GLB_RT_OBS) " li1 150 2100 833.1 2516.54,\
- met1 150 2100 833.1 2516.54,\
- met2 150 2100 833.1 2516.54,\
- met3 150 2100 833.1 2516.54,\
- li1 950 2100 1633.1 2516.54,\
- met1 950 2100 1633.1 2516.54,\
- met2 950 2100 1633.1 2516.54,\
- met3 950 2100 1633.1 2516.54,\
- li1 150 3000 833.1 3416.54,\
- met1 150 3000 833.1 3416.54,\
- met2 150 3000 833.1 3416.54,\
- met3 150 3000 833.1 3416.54,\
- li1 950 3000 1633.1 3416.54,\
- met1 950 3000 1633.1 3416.54,\
- met2 950 3000 1633.1 3416.54,\
- met3 950 3000 1633.1 3416.54,\
- li1 150 1400 833.1 1816.54,\
- met1 150 1400 833.1 1816.54,\
- met2 150 1400 833.1 1816.54,\
- met3 150 1400 833.1 1816.54,\
- li1 150 800 833.1 1216.54,\
- met1 150 800 833.1 1216.54,\
- met2 150 800 833.1 1216.54,\
- met3 150 800 833.1 1216.54,\
- li1 150 200 833.1 616.54,\
- met1 150 200 833.1 616.54,\
- met2 150 200 833.1 616.54,\
- met3 150 200 833.1 616.54,\
+set ::env(GLB_RT_OBS) " \
+ li1 150 150 833.1 566.54,\
+ met1 150 150 833.1 566.54,\
+ met2 150 150 833.1 566.54,\
+ met3 150 150 833.1 566.54,\
+
+ li1 900 150 1583.1 566.54,\
+ met1 900 150 1583.1 566.54,\
+ met2 900 150 1583.1 566.54,\
+ met3 900 150 1583.1 566.54,\
+
+ li1 150 800 833.1 1216.54,\
+ met1 150 800 833.1 1216.54,\
+ met2 150 800 833.1 1216.54,\
+ met3 150 800 833.1 1216.54,\
met5 0 0 2920 3520"
set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
-set ::env(FP_PDN_MACRO_HOOKS) " \
- u_intercon vccd1 vssd1 \
- u_pinmux vccd1 vssd1 \
- u_qspi_master vccd1 vssd1 \
- u_riscv_top vccd1 vssd1 \
- u_tsram0_2kb vccd1 vssd1 \
- u_icache_2kb vccd1 vssd1 \
- u_dcache_2kb vccd1 vssd1 \
- u_mbist vccd1 vssd1 \
- u_sram0_2kb vccd1 vssd1 \
- u_sram1_2kb vccd1 vssd1 \
- u_sram2_2kb vccd1 vssd1 \
- u_sram3_2kb vccd1 vssd1 \
- u_uart_i2c_usb_spi vccd1 vssd1 \
- u_wb_host vccd1 vssd1 "
+#set ::env(FP_PDN_MACRO_HOOKS) " \
+# u_intercon vccd1 vssd1 \
+# u_pinmux vccd1 vssd1 \
+# u_qspi_master vccd1 vssd1 \
+# u_riscv_top vccd1 vssd1 \
+# u_tsram0_2kb vccd1 vssd1 \
+# u_icache_2kb vccd1 vssd1 \
+# u_dcache_2kb vccd1 vssd1 \
+# u_sram0_2kb vccd1 vssd1 \
+# u_sram1_2kb vccd1 vssd1 \
+# u_sram2_2kb vccd1 vssd1 \
+# u_sram3_2kb vccd1 vssd1 \
+# u_uart_i2c_usb_spi vccd1 vssd1 \
+# u_wb_host vccd1 vssd1 "
# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(SYNTH_TOP_LEVEL) 0
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
@@ -200,7 +188,7 @@
set ::env(FP_PDN_VWIDTH) "3.1"
set ::env(FP_PDN_HOFFSET) "10"
-set ::env(FP_PDN_HPITCH) "120"
+set ::env(FP_PDN_HPITCH) "100"
set ::env(FP_PDN_HSPACING) "10"
set ::env(FP_PDN_HWIDTH) "3.1"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 0a134ff..ea9cf65 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,12 +1,14 @@
-u_qspi_master 2225 700 N
-u_uart_i2c_usb_spi 2225 1400 N
-u_pinmux 2225 2300 N
+u_qspi_master 2225 700 N
+u_uart_i2c_usb_spi 2225 1400 N
+u_pinmux 2225 2300 N
-u_riscv_top 950 450 N
-u_dcache_2kb 150 1400 N
-u_icache_2kb 150 800 N
-u_tsram0_2kb 150 200 N
+u_riscv_top.i_core_top_0 150 1500 N
+u_riscv_top.i_core_top_1 950 1500 N
+u_riscv_top.u_mintf 925 700 N
+u_icache_2kb 150 150 N
+u_dcache_2kb 900 150 N
+u_tsram0_2kb 150 800 N
-u_intercon 1850 700 N
-u_wb_host 1450 100 N
+u_intercon 1850 700 N
+u_wb_host 1750 100 N
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index ff38b49..7c2708c 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -75,7 +75,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 350 400"
+set ::env(DIE_AREA) "0 0 350 425"
# If you're going to use multiple power domains, then keep this disabled.
@@ -97,7 +97,7 @@
set ::env(FP_PDN_VWIDTH) 5
set ::env(FP_PDN_HWIDTH) 5
-set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/wb_host/interactive.tcl b/openlane/wb_host/interactive.tcl
deleted file mode 100644
index f59586f..0000000
--- a/openlane/wb_host/interactive.tcl
+++ /dev/null
@@ -1,219 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
- # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
- # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
- # set_def $pdndef
- if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
- set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
- }
-
- run_placement
-}
-
-proc run_cts_step {args} {
- # set_def $::env(opendp_result_file_tag).def
- if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
- set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
- }
-
- run_cts
- run_resizer_timing
-}
-
-proc run_routing_step {args} {
- # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
- # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
- # set_def $resizerdef
- if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
- set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
- }
- run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
- set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
- }
- if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
- run_antenna_check
- heal_antenna_violators; # modifies the routed DEF
- }
-
-}
-
-proc run_power_pins_insertion_step {args} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
- set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
- }
- if { $::env(LVS_INSERT_POWER_PINS) } {
- write_powered_verilog
- set_netlist $::env(lvs_result_file_tag).powered.v
- }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
- set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
- }
- if { $lvs_enabled } {
- run_magic_spice_export
- run_lvs; # requires run_magic_spice_export
- }
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
- if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
- set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
- }
- if { $drc_enabled } {
- run_magic_drc
- run_klayout_drc
- }
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
- if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
- set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
- }
- if { $antenna_check_enabled } {
- run_antenna_check
- }
-}
-
-proc run_flow {args} {
- set script_dir [file dirname [file normalize [info script]]]
-
- set options {
- {-design required}
- {-save_path optional}
- {-no_lvs optional}
- {-no_drc optional}
- {-no_antennacheck optional}
- }
- set flags {-save}
- parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
- prep {*}$args
-
- set LVS_ENABLED 1
- set DRC_ENABLED 1
- set ANTENNACHECK_ENABLED 1
-
- set steps [dict create "synthesis" {run_synthesis "" } \
- "floorplan" {run_floorplan ""} \
- "placement" {run_placement_step ""} \
- "cts" {run_cts_step ""} \
- "routing" {run_routing_step ""}\
- "diode_insertion" {run_diode_insertion_2_5_step ""} \
- "power_pins_insertion" {run_power_pins_insertion_step ""} \
- "gds_magic" {run_magic ""} \
- "gds_drc_klayout" {run_klayout ""} \
- "gds_xor_klayout" {run_klayout_gds_xor ""} \
- "lvs" "run_lvs_step $LVS_ENABLED" \
- "drc" "run_drc_step $DRC_ENABLED" \
- "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
- "cvc" {run_lef_cvc}
- ]
-
- set_if_unset arg_values(-to) "cvc";
-
- if { [info exists ::env(CURRENT_STEP) ] } {
- puts "\[INFO\]:Picking up where last execution left off"
- puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
- } else {
- set ::env(CURRENT_STEP) "synthesis";
- }
- set_if_unset arg_values(-from) $::env(CURRENT_STEP);
- set exe 0;
- dict for {step_name step_exe} $steps {
- if { [ string equal $arg_values(-from) $step_name ] } {
- set exe 1;
- }
-
- if { $exe } {
- # For when it fails
- set ::env(CURRENT_STEP) $step_name
- [lindex $step_exe 0] [lindex $step_exe 1] ;
- }
-
- if { [ string equal $arg_values(-to) $step_name ] } {
- set exe 0:
- break;
- }
-
- }
-
- # for when it resumes
- set steps_as_list [dict keys $steps]
- set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
- set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
- if { [info exists flags_map(-save) ] } {
- if { ! [info exists arg_values(-save_path)] } {
- set arg_values(-save_path) ""
- }
- save_views -lef_path $::env(magic_result_file_tag).lef \
- -def_path $::env(CURRENT_DEF) \
- -gds_path $::env(magic_result_file_tag).gds \
- -mag_path $::env(magic_result_file_tag).mag \
- -maglef_path $::env(magic_result_file_tag).lef.mag \
- -spice_path $::env(magic_result_file_tag).spice \
- -spef_path $::env(CURRENT_SPEF) \
- -verilog_path $::env(CURRENT_NETLIST) \
- -save_path $arg_values(-save_path) \
- -tag $::env(RUN_TAG)
- }
-
-
- calc_total_runtime
- save_state
- generate_final_summary_report
-
- check_timing_violations
-
- puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 540187b..3448c6c 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -4,13 +4,7 @@
#W
-sspim_rst_n 0000 0 4
-qspim_rst_n
-uart_rst_n
-i2cm_rst_n
-usb_rst_n
-bist_rst_n
-usb_clk
+usb_clk 0000 0 4
cfg_clk_ctrl1\[31\]
cfg_clk_ctrl1\[30\]
cfg_clk_ctrl1\[29\]
@@ -30,7 +24,6 @@
cpu_clk 0100 0 2
rtc_clk
-cpu_rst_n
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index bc25fd0..c5f0155 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -118,8 +118,7 @@
set ::env(GLB_RT_ALLOW_CONGESTION) 0
set ::env(GLB_RT_OVERFLOW_ITERS) 200
-set ::env(GLB_RT_MINLAYER) 2
-set ::env(GLB_RT_MAXLAYER) 6
+set ::env(RT_MAX_LAYER) {met4}
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
diff --git a/openlane/wb_interconnect/interactive.tcl b/openlane/wb_interconnect/interactive.tcl
deleted file mode 100644
index a180a5c..0000000
--- a/openlane/wb_interconnect/interactive.tcl
+++ /dev/null
@@ -1,403 +0,0 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-package require openlane;
-
-
-proc run_placement_step {args} {
- # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
- # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
- # set_def $pdndef
- if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
- set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
- }
-
- run_placement
-}
-
-proc run_cts_step {args} {
- # set_def $::env(opendp_result_file_tag).def
- if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
- set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
- }
-
- run_cts
- run_resizer_timing
-}
-
-proc run_routing_step {args} {
- # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
- # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
- # set_def $resizerdef
- if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
- set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
- }
- run_routing
-}
-
-proc run_diode_insertion_2_5_step {args} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
- set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
- }
- if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
- run_antenna_check
- heal_antenna_violators; # modifies the routed DEF
- }
-
-}
-
-proc run_power_pins_insertion_step {args} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
- set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
- }
- if { $::env(LVS_INSERT_POWER_PINS) } {
- write_powered_verilog
- set_netlist $::env(lvs_result_file_tag).powered.v
- }
-
-}
-
-proc run_lvs_step {{ lvs_enabled 1 }} {
- # set_def $::env(tritonRoute_result_file_tag).def
- if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
- set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
- }
- if { $lvs_enabled } {
- run_magic_spice_export
- run_lvs; # requires run_magic_spice_export
- }
-
-}
-
-proc run_drc_step {{ drc_enabled 1 }} {
- if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
- set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
- }
- if { $drc_enabled } {
- run_magic_drc
- run_klayout_drc
- }
-}
-
-proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
- if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
- set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
- }
- if { $antenna_check_enabled } {
- run_antenna_check
- }
-}
-
-proc gen_pdn {args} {
- puts_info "Generating PDN..."
- TIMER::timer_start
-
- set ::env(SAVE_DEF) [index_file $::env(pdn_tmp_file_tag).def]
- set ::env(PGA_RPT_FILE) [index_file $::env(pdn_report_file_tag).pga.rpt]
-
- try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/pdn.tcl \
- |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(pdn_log_file_tag).log 0]
-
-
- TIMER::timer_stop
- exec echo "[TIMER::get_runtime]" >> [index_file $::env(pdn_log_file_tag)_runtime.txt 0]
-
- quit_on_unconnected_pdn_nodes
-
- set_def $::env(SAVE_DEF)
-}
-
-proc run_power_grid_generation {args} {
- if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } {
- # they both must exist and be equal in length
- # current assumption: they cannot have a common ground
- if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } {
- puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined"
- return -code error
- }
- # standard cell power and ground nets are assumed to be the first net
- set ::env(VDD_PIN) [lindex $::env(VDD_NETS) 0]
- set ::env(GND_PIN) [lindex $::env(GND_NETS) 0]
- } elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } {
- set ::env(VDD_NETS) [list]
- set ::env(GND_NETS) [list]
- # get the pins that are in $yosys_tmp_file_tag.pg_define.v
- # that are not in $yosys_result_file_tag.v
- #
- set full_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_tmp_file_tag).pg_define.v]
- puts_info $full_pins
-
- set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_result_file_tag).v]
- puts_info $non_pg_pins
-
- # assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...)
- foreach {vdd gnd} $full_pins {
- if { $vdd ne "" && $vdd ni $non_pg_pins } {
- lappend ::env(VDD_NETS) $vdd
- }
- if { $gnd ne "" && $gnd ni $non_pg_pins } {
- lappend ::env(GND_NETS) $gnd
- }
- }
- } else {
- set ::env(VDD_NETS) $::env(VDD_PIN)
- set ::env(GND_NETS) $::env(GND_PIN)
- }
-
- puts_info "Power planning the following nets"
- puts_info "Power: $::env(VDD_NETS)"
- puts_info "Ground: $::env(GND_NETS)"
-
- if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } {
- puts_err "VDD_NETS and GND_NETS must be of equal lengths"
- return -code error
- }
-
- # internal macros power connections
- if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
- set macro_hooks [dict create]
- set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
- foreach pdn_hook $pdn_hooks {
- set instance_name [lindex $pdn_hook 0]
- set power_net [lindex $pdn_hook 1]
- set ground_net [lindex $pdn_hook 2]
- dict append macro_hooks $instance_name [subst {$power_net $ground_net}]
- set power_net_indx [lsearch $::env(VDD_NETS) $power_net]
- set ground_net_indx [lsearch $::env(GND_NETS) $ground_net]
-
- # make sure that the specified power domains exist.
- if { $power_net_indx == -1 || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } {
- puts_err "Can't find $power_net and $ground_net domain. \
- Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)."
- }
- }
-
- }
-
- # generate multiple power grids per pair of (VDD,GND)
- # offseted by WIDTH + SPACING
- foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
- set ::env(VDD_NET) $vdd
- set ::env(GND_NET) $gnd
- puts_info "Connecting Power: $vdd & gnd to All internal macros."
-
- # internal macros power connections
- set ::env(FP_PDN_MACROS) ""
- if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } {
- # if macros connections to power are explicitly set
- # default behavoir macro pins will be connected to the first power domain
- if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } {
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
- foreach {instance_name hooks} $macro_hooks {
- set power [lindex $hooks 0]
- set ground [lindex $hooks 1]
- if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } {
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
- puts_info "Connecting $instance_name to $power and $ground nets."
- lappend ::env(FP_PDN_MACROS) $instance_name
- }
- }
- }
- } else {
- puts_warn "All internal macros will not be connected to power $vdd & $gnd."
- }
-
- gen_pdn
-
- set ::env(FP_PDN_ENABLE_RAILS) 0
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
-
- # allow failure until open_pdks is up to date...
- catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]}
- catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]}
-
- catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \
- [expr $::env(FP_PDN_CORE_RING_VOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_VWIDTH)\
- +max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
- catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_HWIDTH)+\
- max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
-
- puts "FP_PDN_VOFFSET: $::env(FP_PDN_VOFFSET)"
- puts "FP_PDN_HOFFSET: $::env(FP_PDN_VOFFSET)"
- puts "FP_PDN_CORE_RING_VOFFSET: $::env(FP_PDN_CORE_RING_VOFFSET)"
- puts "FP_PDN_CORE_RING_HOFFSET: $::env(FP_PDN_CORE_RING_HOFFSET)"
- }
- set ::env(FP_PDN_ENABLE_RAILS) 1
-}
-
-
-proc run_floorplan {args} {
- puts_info "Running Floorplanning..."
- # |----------------------------------------------------|
- # |---------------- 2. FLOORPLAN ------------------|
- # |----------------------------------------------------|
- #
- # intial fp
- init_floorplan
-
-
- # place io
- if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
- place_io_ol
- } else {
- if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
- place_io
- global_placement_or
- place_contextualized_io \
- -lef $::env(FP_CONTEXT_LEF) \
- -def $::env(FP_CONTEXT_DEF)
- } else {
- place_io
- }
- }
-
- apply_def_template
-
- if { [info exist ::env(EXTRA_LEFS)] } {
- if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
- file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/macro_placement.cfg
- manual_macro_placement f
- } else {
- global_placement_or
- basic_macro_placement
- }
- }
-
- # tapcell
- tap_decap_or
- scrot_klayout -layout $::env(CURRENT_DEF)
- # power grid generation
- run_power_grid_generation
-}
-
-proc run_flow {args} {
- set script_dir [file dirname [file normalize [info script]]]
-
- set options {
- {-design required}
- {-save_path optional}
- {-no_lvs optional}
- {-no_drc optional}
- {-no_antennacheck optional}
- }
- set flags {-save}
- parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
-
- prep {*}$args
-
- set LVS_ENABLED 1
- set DRC_ENABLED 0
- set ANTENNACHECK_ENABLED 1
-
- set steps [dict create "synthesis" {run_synthesis "" } \
- "floorplan" {run_floorplan ""} \
- "placement" {run_placement_step ""} \
- "cts" {run_cts_step ""} \
- "routing" {run_routing_step ""}\
- "diode_insertion" {run_diode_insertion_2_5_step ""} \
- "power_pins_insertion" {run_power_pins_insertion_step ""} \
- "gds_magic" {run_magic ""} \
- "gds_drc_klayout" {run_klayout ""} \
- "gds_xor_klayout" {run_klayout_gds_xor ""} \
- "lvs" "run_lvs_step $LVS_ENABLED" \
- "drc" "run_drc_step $DRC_ENABLED" \
- "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
- "cvc" {run_lef_cvc}
- ]
-
- set_if_unset arg_values(-to) "cvc";
-
- if { [info exists ::env(CURRENT_STEP) ] } {
- puts "\[INFO\]:Picking up where last execution left off"
- puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
- } else {
- set ::env(CURRENT_STEP) "synthesis";
- }
- set_if_unset arg_values(-from) $::env(CURRENT_STEP);
- set exe 0;
- dict for {step_name step_exe} $steps {
- if { [ string equal $arg_values(-from) $step_name ] } {
- set exe 1;
- }
-
- if { $exe } {
- # For when it fails
- set ::env(CURRENT_STEP) $step_name
- [lindex $step_exe 0] [lindex $step_exe 1] ;
- }
-
- if { [ string equal $arg_values(-to) $step_name ] } {
- set exe 0:
- break;
- }
-
- }
-
- # for when it resumes
- set steps_as_list [dict keys $steps]
- set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
- set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
-
- if { [info exists flags_map(-save) ] } {
- if { ! [info exists arg_values(-save_path)] } {
- set arg_values(-save_path) ""
- }
- save_views -lef_path $::env(magic_result_file_tag).lef \
- -def_path $::env(CURRENT_DEF) \
- -gds_path $::env(magic_result_file_tag).gds \
- -mag_path $::env(magic_result_file_tag).mag \
- -maglef_path $::env(magic_result_file_tag).lef.mag \
- -spice_path $::env(magic_result_file_tag).spice \
- -spef_path $::env(CURRENT_SPEF) \
- -verilog_path $::env(CURRENT_NETLIST) \
- -save_path $arg_values(-save_path) \
- -tag $::env(RUN_TAG)
- }
-
-
- calc_total_runtime
- save_state
- generate_final_summary_report
-
- check_timing_violations
-
- puts_success "Flow Completed Without Fatal Errors."
-
-}
-
-run_flow {*}$argv
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index ae3e4b5..d9fb1bd 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -147,64 +147,14 @@
#W
-ch_data_out\[68\] 0750 0 2
-ch_data_out\[67\]
-ch_data_out\[66\]
-ch_data_out\[65\]
-ch_data_out\[64\]
-ch_data_out\[63\]
-ch_data_out\[62\]
-ch_data_out\[61\]
-ch_data_out\[60\]
-ch_data_out\[59\]
-ch_data_out\[58\]
-ch_data_out\[57\]
-ch_data_out\[56\]
-ch_data_out\[55\]
-ch_data_out\[54\]
-ch_data_out\[53\]
-ch_data_out\[52\]
-ch_data_out\[51\]
-ch_data_out\[50\]
-ch_data_out\[49\]
-ch_data_out\[48\]
-ch_data_out\[47\]
-ch_data_out\[46\]
-ch_data_out\[45\]
-ch_data_out\[44\]
-ch_data_out\[43\]
-ch_data_out\[42\]
-ch_data_out\[41\]
-ch_data_out\[40\]
-ch_data_out\[39\]
-ch_data_out\[38\]
-ch_data_out\[37\]
-ch_data_out\[36\]
-ch_data_out\[35\]
-ch_data_out\[34\]
-ch_data_out\[33\]
-ch_data_out\[32\]
-ch_data_out\[31\]
-ch_data_out\[30\]
-ch_data_out\[29\]
-ch_data_out\[28\]
-ch_data_out\[27\]
-ch_data_out\[26\]
-ch_data_out\[25\]
-ch_data_out\[24\]
-ch_data_out\[23\]
-ch_data_out\[22\]
-ch_data_out\[21\]
-ch_data_out\[20\]
-
-ch_data_out\[3\]
+ch_data_out\[3\] 0000 0 2
ch_data_out\[2\]
ch_data_out\[1\]
ch_data_out\[0\]
ch_clk_out\[0\]
-m1_wbd_stb_i 0950 0 2
+m1_wbd_stb_i 0100 0 2
m1_wbd_we_i
m1_wbd_adr_i\[31\]
m1_wbd_adr_i\[30\]
@@ -311,7 +261,7 @@
m1_wbd_err_o
m1_wbd_cyc_i
-m2_wbd_stb_i 1150 0 2
+m2_wbd_stb_i 250 0 2
m2_wbd_we_i
m2_wbd_adr_i\[31\]
m2_wbd_adr_i\[30\]
@@ -429,7 +379,7 @@
m2_wbd_err_o
m2_wbd_cyc_i
-m3_wbd_stb_i 1350 0 2
+m3_wbd_stb_i 450 0 2
m3_wbd_we_i
m3_wbd_adr_i\[31\]
m3_wbd_adr_i\[30\]
@@ -515,6 +465,55 @@
m3_wbd_err_o
m3_wbd_cyc_i
+ch_data_out\[68\] 0750 0 2
+ch_data_out\[67\]
+ch_data_out\[66\]
+ch_data_out\[65\]
+ch_data_out\[64\]
+ch_data_out\[63\]
+ch_data_out\[62\]
+ch_data_out\[61\]
+ch_data_out\[60\]
+ch_data_out\[59\]
+ch_data_out\[58\]
+ch_data_out\[57\]
+ch_data_out\[56\]
+ch_data_out\[55\]
+ch_data_out\[54\]
+ch_data_out\[53\]
+ch_data_out\[52\]
+ch_data_out\[51\]
+ch_data_out\[50\]
+ch_data_out\[49\]
+ch_data_out\[48\]
+ch_data_out\[47\]
+ch_data_out\[46\]
+ch_data_out\[45\]
+ch_data_out\[44\]
+ch_data_out\[43\]
+ch_data_out\[42\]
+ch_data_out\[41\]
+ch_data_out\[40\]
+ch_data_out\[39\]
+ch_data_out\[38\]
+ch_data_out\[37\]
+ch_data_out\[36\]
+ch_data_out\[35\]
+ch_data_out\[34\]
+ch_data_out\[33\]
+ch_data_out\[32\]
+ch_data_out\[31\]
+ch_data_out\[30\]
+ch_data_out\[29\]
+ch_data_out\[28\]
+ch_data_out\[27\]
+ch_data_out\[26\]
+ch_data_out\[25\]
+ch_data_out\[24\]
+ch_data_out\[23\]
+ch_data_out\[22\]
+ch_data_out\[21\]
+ch_data_out\[20\]
#E
ch_data_out\[19\] 0000 0 2
diff --git a/openlane/ycr2_mintf/base.sdc b/openlane/ycr2_mintf/base.sdc
new file mode 100644
index 0000000..00fe508
--- /dev/null
+++ b/openlane/ycr2_mintf/base.sdc
@@ -0,0 +1,32 @@
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 20.0000 [get_ports {core_clk}]
+create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
+create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {core_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {wb_clk}] -comment {Async Clock group}
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/openlane/ycr2_mintf/config.tcl b/openlane/ycr2_mintf/config.tcl
new file mode 100644
index 0000000..84b97fb
--- /dev/null
+++ b/openlane/ycr2_mintf/config.tcl
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(ROUTING_CORES) "6"
+
+set ::env(DESIGN_NAME) ycr2_mintf
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "wb_clk core_clk rtc_clk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+set ::env(LEC_ENABLE) 0
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/clk_skew_adjust.gv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_router.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_imem_router.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_icache_router.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dcache_router.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_mcore_router.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_tcm.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_timer.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_wb.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_imem_wb.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_intf.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_mintf.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_top.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_tag_fifo.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_top.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ycr_async_wbb.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ycr_arb.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/sync_fifo.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/async_fifo.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ctech_cells.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv \
+ "
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+## Floorplan
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 800 700 "
+
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+set ::env(PL_TARGET_DENSITY) 0.36
+
+
+set ::env(RT_MAX_LAYER) {met4}
+set ::env(GLB_RT_MAXLAYER) "5"
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+
+#Need to cross-check why global timing opimization creating setup vio with hugh hold fix
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
diff --git a/openlane/ycr2_mintf/macro_placement.cfg b/openlane/ycr2_mintf/macro_placement.cfg
new file mode 100644
index 0000000..46c82ae
--- /dev/null
+++ b/openlane/ycr2_mintf/macro_placement.cfg
@@ -0,0 +1,2 @@
+u_icache.u_cmem_2kb 185.000 291.000 FS
+u_dcache.u_cmem_2kb 1185.000 291.000 N
diff --git a/openlane/ycr2_mintf/pin_order.cfg b/openlane/ycr2_mintf/pin_order.cfg
new file mode 100644
index 0000000..cf834b7
--- /dev/null
+++ b/openlane/ycr2_mintf/pin_order.cfg
@@ -0,0 +1,1282 @@
+#BUS_SORT
+#MANUAL_PLACE
+#W
+sram0_clk0 0 0 2
+sram0_csb0
+sram0_web0
+sram0_addr0\[0\]
+sram0_addr0\[1\]
+sram0_addr0\[2\]
+sram0_addr0\[3\]
+sram0_addr0\[4\]
+sram0_addr0\[5\]
+sram0_addr0\[6\]
+sram0_addr0\[7\]
+sram0_addr0\[8\]
+sram0_wmask0\[0\]
+sram0_wmask0\[1\]
+sram0_wmask0\[2\]
+sram0_wmask0\[3\]
+sram0_din0\[0\]
+sram0_din0\[1\]
+sram0_din0\[2\]
+sram0_din0\[3\]
+sram0_din0\[4\]
+sram0_din0\[5\]
+sram0_din0\[6\]
+sram0_din0\[7\]
+sram0_din0\[8\]
+sram0_din0\[9\]
+sram0_din0\[10\]
+sram0_din0\[11\]
+sram0_din0\[12\]
+sram0_din0\[13\]
+sram0_din0\[14\]
+sram0_din0\[15\]
+sram0_din0\[16\]
+sram0_din0\[17\]
+sram0_din0\[18\]
+sram0_din0\[19\]
+sram0_din0\[20\]
+sram0_din0\[21\]
+sram0_din0\[22\]
+sram0_din0\[23\]
+sram0_din0\[24\]
+sram0_din0\[25\]
+sram0_din0\[26\]
+sram0_din0\[27\]
+sram0_din0\[28\]
+sram0_din0\[29\]
+sram0_din0\[30\]
+sram0_din0\[31\]
+
+
+sram0_dout0\[0\] 0100 0 2
+sram0_dout0\[1\]
+sram0_dout0\[2\]
+sram0_dout0\[3\]
+sram0_dout0\[4\]
+sram0_dout0\[5\]
+sram0_dout0\[6\]
+sram0_dout0\[7\]
+sram0_dout0\[8\]
+sram0_dout0\[9\]
+sram0_dout0\[10\]
+sram0_dout0\[11\]
+sram0_dout0\[12\]
+sram0_dout0\[13\]
+sram0_dout0\[14\]
+sram0_dout0\[15\]
+sram0_dout0\[16\]
+sram0_dout0\[17\]
+sram0_dout0\[18\]
+sram0_dout0\[19\]
+sram0_dout0\[20\]
+sram0_dout0\[21\]
+sram0_dout0\[22\]
+sram0_dout0\[23\]
+sram0_dout0\[24\]
+sram0_dout0\[25\]
+sram0_dout0\[26\]
+sram0_dout0\[27\]
+sram0_dout0\[28\]
+sram0_dout0\[29\]
+sram0_dout0\[30\]
+sram0_dout0\[31\]
+
+sram0_clk1 0200 0 2
+sram0_csb1
+sram0_addr1\[8\]
+sram0_addr1\[7\]
+sram0_addr1\[6\]
+sram0_addr1\[5\]
+sram0_addr1\[4\]
+sram0_addr1\[3\]
+sram0_addr1\[2\]
+sram0_addr1\[1\]
+sram0_addr1\[0\]
+
+sram0_dout1\[0\] 0250 0 2
+sram0_dout1\[1\]
+sram0_dout1\[2\]
+sram0_dout1\[3\]
+sram0_dout1\[4\]
+sram0_dout1\[5\]
+sram0_dout1\[6\]
+sram0_dout1\[7\]
+sram0_dout1\[8\]
+sram0_dout1\[9\]
+sram0_dout1\[10\]
+sram0_dout1\[11\]
+sram0_dout1\[12\]
+sram0_dout1\[13\]
+sram0_dout1\[14\]
+sram0_dout1\[15\]
+sram0_dout1\[16\]
+sram0_dout1\[17\]
+sram0_dout1\[18\]
+sram0_dout1\[19\]
+sram0_dout1\[20\]
+sram0_dout1\[21\]
+sram0_dout1\[22\]
+sram0_dout1\[23\]
+sram0_dout1\[24\]
+sram0_dout1\[25\]
+sram0_dout1\[26\]
+sram0_dout1\[27\]
+sram0_dout1\[28\]
+sram0_dout1\[29\]
+sram0_dout1\[30\]
+sram0_dout1\[31\]
+
+
+#S
+icache_mem_clk0
+icache_mem_csb0
+icache_mem_web0
+icache_mem_addr0\[0\]
+icache_mem_addr0\[1\]
+icache_mem_addr0\[2\]
+icache_mem_addr0\[3\]
+icache_mem_addr0\[4\]
+icache_mem_addr0\[5\]
+icache_mem_addr0\[6\]
+icache_mem_addr0\[7\]
+icache_mem_addr0\[8\]
+icache_mem_wmask0\[0\]
+icache_mem_wmask0\[1\]
+icache_mem_wmask0\[2\]
+icache_mem_wmask0\[3\]
+icache_mem_din0\[0\]
+icache_mem_din0\[1\]
+icache_mem_din0\[2\]
+icache_mem_din0\[3\]
+icache_mem_din0\[4\]
+icache_mem_din0\[5\]
+icache_mem_din0\[6\]
+icache_mem_din0\[7\]
+icache_mem_din0\[8\]
+icache_mem_din0\[9\]
+icache_mem_din0\[10\]
+icache_mem_din0\[11\]
+icache_mem_din0\[12\]
+icache_mem_din0\[13\]
+icache_mem_din0\[14\]
+icache_mem_din0\[15\]
+icache_mem_din0\[16\]
+icache_mem_din0\[17\]
+icache_mem_din0\[18\]
+icache_mem_din0\[19\]
+icache_mem_din0\[20\]
+icache_mem_din0\[21\]
+icache_mem_din0\[22\]
+icache_mem_din0\[23\]
+icache_mem_din0\[24\]
+icache_mem_din0\[25\]
+icache_mem_din0\[26\]
+icache_mem_din0\[27\]
+icache_mem_din0\[28\]
+icache_mem_din0\[29\]
+icache_mem_din0\[30\]
+icache_mem_din0\[31\]
+
+icache_mem_clk1 100 0 2
+icache_mem_csb1
+icache_mem_addr1\[8\]
+icache_mem_addr1\[7\]
+icache_mem_addr1\[6\]
+icache_mem_addr1\[5\]
+icache_mem_addr1\[4\]
+icache_mem_addr1\[3\]
+icache_mem_addr1\[2\]
+icache_mem_addr1\[1\]
+icache_mem_addr1\[0\]
+
+icache_mem_dout1\[0\] 150 0 2
+icache_mem_dout1\[1\]
+icache_mem_dout1\[2\]
+icache_mem_dout1\[3\]
+icache_mem_dout1\[4\]
+icache_mem_dout1\[5\]
+icache_mem_dout1\[6\]
+icache_mem_dout1\[7\]
+icache_mem_dout1\[8\]
+icache_mem_dout1\[9\]
+icache_mem_dout1\[10\]
+icache_mem_dout1\[11\]
+icache_mem_dout1\[12\]
+icache_mem_dout1\[13\]
+icache_mem_dout1\[14\]
+icache_mem_dout1\[15\]
+icache_mem_dout1\[16\]
+icache_mem_dout1\[17\]
+icache_mem_dout1\[18\]
+icache_mem_dout1\[19\]
+icache_mem_dout1\[20\]
+icache_mem_dout1\[21\]
+icache_mem_dout1\[22\]
+icache_mem_dout1\[23\]
+icache_mem_dout1\[24\]
+icache_mem_dout1\[25\]
+icache_mem_dout1\[26\]
+icache_mem_dout1\[27\]
+icache_mem_dout1\[28\]
+icache_mem_dout1\[29\]
+icache_mem_dout1\[30\]
+icache_mem_dout1\[31\]
+
+dcache_mem_clk0 400 0 2
+dcache_mem_csb0
+dcache_mem_web0
+dcache_mem_addr0\[0\]
+dcache_mem_addr0\[1\]
+dcache_mem_addr0\[2\]
+dcache_mem_addr0\[3\]
+dcache_mem_addr0\[4\]
+dcache_mem_addr0\[5\]
+dcache_mem_addr0\[6\]
+dcache_mem_addr0\[7\]
+dcache_mem_addr0\[8\]
+dcache_mem_wmask0\[0\]
+dcache_mem_wmask0\[1\]
+dcache_mem_wmask0\[2\]
+dcache_mem_wmask0\[3\]
+dcache_mem_din0\[0\]
+dcache_mem_din0\[1\]
+dcache_mem_din0\[2\]
+dcache_mem_din0\[3\]
+dcache_mem_din0\[4\]
+dcache_mem_din0\[5\]
+dcache_mem_din0\[6\]
+dcache_mem_din0\[7\]
+dcache_mem_din0\[8\]
+dcache_mem_din0\[9\]
+dcache_mem_din0\[10\]
+dcache_mem_din0\[11\]
+dcache_mem_din0\[12\]
+dcache_mem_din0\[13\]
+dcache_mem_din0\[14\]
+dcache_mem_din0\[15\]
+dcache_mem_din0\[16\]
+dcache_mem_din0\[17\]
+dcache_mem_din0\[18\]
+dcache_mem_din0\[19\]
+dcache_mem_din0\[20\]
+dcache_mem_din0\[21\]
+dcache_mem_din0\[22\]
+dcache_mem_din0\[23\]
+dcache_mem_din0\[24\]
+dcache_mem_din0\[25\]
+dcache_mem_din0\[26\]
+dcache_mem_din0\[27\]
+dcache_mem_din0\[28\]
+dcache_mem_din0\[29\]
+dcache_mem_din0\[30\]
+dcache_mem_din0\[31\]
+
+
+dcache_mem_dout0\[0\] 500 0 2
+dcache_mem_dout0\[1\]
+dcache_mem_dout0\[2\]
+dcache_mem_dout0\[3\]
+dcache_mem_dout0\[4\]
+dcache_mem_dout0\[5\]
+dcache_mem_dout0\[6\]
+dcache_mem_dout0\[7\]
+dcache_mem_dout0\[8\]
+dcache_mem_dout0\[9\]
+dcache_mem_dout0\[10\]
+dcache_mem_dout0\[11\]
+dcache_mem_dout0\[12\]
+dcache_mem_dout0\[13\]
+dcache_mem_dout0\[14\]
+dcache_mem_dout0\[15\]
+dcache_mem_dout0\[16\]
+dcache_mem_dout0\[17\]
+dcache_mem_dout0\[18\]
+dcache_mem_dout0\[19\]
+dcache_mem_dout0\[20\]
+dcache_mem_dout0\[21\]
+dcache_mem_dout0\[22\]
+dcache_mem_dout0\[23\]
+dcache_mem_dout0\[24\]
+dcache_mem_dout0\[25\]
+dcache_mem_dout0\[26\]
+dcache_mem_dout0\[27\]
+dcache_mem_dout0\[28\]
+dcache_mem_dout0\[29\]
+dcache_mem_dout0\[30\]
+dcache_mem_dout0\[31\]
+
+dcache_mem_clk1 600 0 2
+dcache_mem_csb1
+dcache_mem_addr1\[8\]
+dcache_mem_addr1\[7\]
+dcache_mem_addr1\[6\]
+dcache_mem_addr1\[5\]
+dcache_mem_addr1\[4\]
+dcache_mem_addr1\[3\]
+dcache_mem_addr1\[2\]
+dcache_mem_addr1\[1\]
+dcache_mem_addr1\[0\]
+
+dcache_mem_dout1\[0\] 650 0 2
+dcache_mem_dout1\[1\]
+dcache_mem_dout1\[2\]
+dcache_mem_dout1\[3\]
+dcache_mem_dout1\[4\]
+dcache_mem_dout1\[5\]
+dcache_mem_dout1\[6\]
+dcache_mem_dout1\[7\]
+dcache_mem_dout1\[8\]
+dcache_mem_dout1\[9\]
+dcache_mem_dout1\[10\]
+dcache_mem_dout1\[11\]
+dcache_mem_dout1\[12\]
+dcache_mem_dout1\[13\]
+dcache_mem_dout1\[14\]
+dcache_mem_dout1\[15\]
+dcache_mem_dout1\[16\]
+dcache_mem_dout1\[17\]
+dcache_mem_dout1\[18\]
+dcache_mem_dout1\[19\]
+dcache_mem_dout1\[20\]
+dcache_mem_dout1\[21\]
+dcache_mem_dout1\[22\]
+dcache_mem_dout1\[23\]
+dcache_mem_dout1\[24\]
+dcache_mem_dout1\[25\]
+dcache_mem_dout1\[26\]
+dcache_mem_dout1\[27\]
+dcache_mem_dout1\[28\]
+dcache_mem_dout1\[29\]
+dcache_mem_dout1\[30\]
+dcache_mem_dout1\[31\]
+riscv_debug\[0\]
+riscv_debug\[1\]
+riscv_debug\[2\]
+riscv_debug\[3\]
+riscv_debug\[4\]
+riscv_debug\[5\]
+riscv_debug\[6\]
+riscv_debug\[7\]
+riscv_debug\[8\]
+riscv_debug\[9\]
+riscv_debug\[10\]
+riscv_debug\[11\]
+riscv_debug\[12\]
+riscv_debug\[13\]
+riscv_debug\[14\]
+riscv_debug\[15\]
+riscv_debug\[16\]
+riscv_debug\[17\]
+riscv_debug\[18\]
+riscv_debug\[19\]
+riscv_debug\[20\]
+riscv_debug\[21\]
+riscv_debug\[22\]
+riscv_debug\[23\]
+riscv_debug\[24\]
+riscv_debug\[25\]
+riscv_debug\[26\]
+riscv_debug\[27\]
+riscv_debug\[28\]
+riscv_debug\[29\]
+riscv_debug\[30\]
+riscv_debug\[31\]
+riscv_debug\[32\]
+riscv_debug\[33\]
+riscv_debug\[34\]
+riscv_debug\[35\]
+riscv_debug\[36\]
+riscv_debug\[37\]
+riscv_debug\[38\]
+riscv_debug\[39\]
+riscv_debug\[40\]
+riscv_debug\[41\]
+riscv_debug\[42\]
+riscv_debug\[43\]
+riscv_debug\[44\]
+riscv_debug\[45\]
+riscv_debug\[46\]
+riscv_debug\[47\]
+riscv_debug\[48\]
+riscv_debug\[49\]
+riscv_debug\[50\]
+riscv_debug\[51\]
+riscv_debug\[52\]
+riscv_debug\[53\]
+riscv_debug\[54\]
+riscv_debug\[55\]
+riscv_debug\[56\]
+riscv_debug\[57\]
+riscv_debug\[58\]
+riscv_debug\[59\]
+riscv_debug\[60\]
+riscv_debug\[61\]
+riscv_debug\[62\]
+riscv_debug\[63\]
+
+wb_rst_n 750 0
+pwrup_rst_n
+rst_n
+core_clk
+rtc_clk
+core_debug_sel\[1\]
+core_debug_sel\[0\]
+cpu_core_rst_n\[1\]
+cpu_core_rst_n\[0\]
+
+
+#E
+cfg_cska_riscv\[3\] 0000 0 2
+cfg_cska_riscv\[2\]
+cfg_cska_riscv\[1\]
+cfg_cska_riscv\[0\]
+wbd_clk_int
+wbd_clk_riscv
+wb_clk
+
+wbd_dmem_stb_o 0100 0 2
+wbd_dmem_we_o
+wbd_dmem_adr_o\[31\]
+wbd_dmem_adr_o\[30\]
+wbd_dmem_adr_o\[29\]
+wbd_dmem_adr_o\[28\]
+wbd_dmem_adr_o\[27\]
+wbd_dmem_adr_o\[26\]
+wbd_dmem_adr_o\[25\]
+wbd_dmem_adr_o\[24\]
+wbd_dmem_adr_o\[23\]
+wbd_dmem_adr_o\[22\]
+wbd_dmem_adr_o\[21\]
+wbd_dmem_adr_o\[20\]
+wbd_dmem_adr_o\[19\]
+wbd_dmem_adr_o\[18\]
+wbd_dmem_adr_o\[17\]
+wbd_dmem_adr_o\[16\]
+wbd_dmem_adr_o\[15\]
+wbd_dmem_adr_o\[14\]
+wbd_dmem_adr_o\[13\]
+wbd_dmem_adr_o\[12\]
+wbd_dmem_adr_o\[11\]
+wbd_dmem_adr_o\[10\]
+wbd_dmem_adr_o\[9\]
+wbd_dmem_adr_o\[8\]
+wbd_dmem_adr_o\[7\]
+wbd_dmem_adr_o\[6\]
+wbd_dmem_adr_o\[5\]
+wbd_dmem_adr_o\[4\]
+wbd_dmem_adr_o\[3\]
+wbd_dmem_adr_o\[2\]
+wbd_dmem_adr_o\[1\]
+wbd_dmem_adr_o\[0\]
+wbd_dmem_sel_o\[3\]
+wbd_dmem_sel_o\[2\]
+wbd_dmem_sel_o\[1\]
+wbd_dmem_sel_o\[0\]
+wbd_dmem_dat_o\[31\]
+wbd_dmem_dat_o\[30\]
+wbd_dmem_dat_o\[29\]
+wbd_dmem_dat_o\[28\]
+wbd_dmem_dat_o\[27\]
+wbd_dmem_dat_o\[26\]
+wbd_dmem_dat_o\[25\]
+wbd_dmem_dat_o\[24\]
+wbd_dmem_dat_o\[23\]
+wbd_dmem_dat_o\[22\]
+wbd_dmem_dat_o\[21\]
+wbd_dmem_dat_o\[20\]
+wbd_dmem_dat_o\[19\]
+wbd_dmem_dat_o\[18\]
+wbd_dmem_dat_o\[17\]
+wbd_dmem_dat_o\[16\]
+wbd_dmem_dat_o\[15\]
+wbd_dmem_dat_o\[14\]
+wbd_dmem_dat_o\[13\]
+wbd_dmem_dat_o\[12\]
+wbd_dmem_dat_o\[11\]
+wbd_dmem_dat_o\[10\]
+wbd_dmem_dat_o\[9\]
+wbd_dmem_dat_o\[8\]
+wbd_dmem_dat_o\[7\]
+wbd_dmem_dat_o\[6\]
+wbd_dmem_dat_o\[5\]
+wbd_dmem_dat_o\[4\]
+wbd_dmem_dat_o\[3\]
+wbd_dmem_dat_o\[2\]
+wbd_dmem_dat_o\[1\]
+wbd_dmem_dat_o\[0\]
+wbd_dmem_dat_i\[31\]
+wbd_dmem_dat_i\[30\]
+wbd_dmem_dat_i\[29\]
+wbd_dmem_dat_i\[28\]
+wbd_dmem_dat_i\[27\]
+wbd_dmem_dat_i\[26\]
+wbd_dmem_dat_i\[25\]
+wbd_dmem_dat_i\[24\]
+wbd_dmem_dat_i\[23\]
+wbd_dmem_dat_i\[22\]
+wbd_dmem_dat_i\[21\]
+wbd_dmem_dat_i\[20\]
+wbd_dmem_dat_i\[19\]
+wbd_dmem_dat_i\[18\]
+wbd_dmem_dat_i\[17\]
+wbd_dmem_dat_i\[16\]
+wbd_dmem_dat_i\[15\]
+wbd_dmem_dat_i\[14\]
+wbd_dmem_dat_i\[13\]
+wbd_dmem_dat_i\[12\]
+wbd_dmem_dat_i\[11\]
+wbd_dmem_dat_i\[10\]
+wbd_dmem_dat_i\[9\]
+wbd_dmem_dat_i\[8\]
+wbd_dmem_dat_i\[7\]
+wbd_dmem_dat_i\[6\]
+wbd_dmem_dat_i\[5\]
+wbd_dmem_dat_i\[4\]
+wbd_dmem_dat_i\[3\]
+wbd_dmem_dat_i\[2\]
+wbd_dmem_dat_i\[1\]
+wbd_dmem_dat_i\[0\]
+wbd_dmem_ack_i
+wbd_dmem_err_i
+
+wb_dcache_stb_o 0250 0 2
+wb_dcache_we_o
+wb_dcache_adr_o\[31\]
+wb_dcache_adr_o\[30\]
+wb_dcache_adr_o\[29\]
+wb_dcache_adr_o\[28\]
+wb_dcache_adr_o\[27\]
+wb_dcache_adr_o\[26\]
+wb_dcache_adr_o\[25\]
+wb_dcache_adr_o\[24\]
+wb_dcache_adr_o\[23\]
+wb_dcache_adr_o\[22\]
+wb_dcache_adr_o\[21\]
+wb_dcache_adr_o\[20\]
+wb_dcache_adr_o\[19\]
+wb_dcache_adr_o\[18\]
+wb_dcache_adr_o\[17\]
+wb_dcache_adr_o\[16\]
+wb_dcache_adr_o\[15\]
+wb_dcache_adr_o\[14\]
+wb_dcache_adr_o\[13\]
+wb_dcache_adr_o\[12\]
+wb_dcache_adr_o\[11\]
+wb_dcache_adr_o\[10\]
+wb_dcache_adr_o\[9\]
+wb_dcache_adr_o\[8\]
+wb_dcache_adr_o\[7\]
+wb_dcache_adr_o\[6\]
+wb_dcache_adr_o\[5\]
+wb_dcache_adr_o\[4\]
+wb_dcache_adr_o\[3\]
+wb_dcache_adr_o\[2\]
+wb_dcache_adr_o\[1\]
+wb_dcache_adr_o\[0\]
+wb_dcache_sel_o\[3\]
+wb_dcache_sel_o\[2\]
+wb_dcache_sel_o\[1\]
+wb_dcache_sel_o\[0\]
+wb_dcache_bl_o\[9\]
+wb_dcache_bl_o\[8\]
+wb_dcache_bl_o\[7\]
+wb_dcache_bl_o\[6\]
+wb_dcache_bl_o\[5\]
+wb_dcache_bl_o\[4\]
+wb_dcache_bl_o\[3\]
+wb_dcache_bl_o\[2\]
+wb_dcache_bl_o\[1\]
+wb_dcache_bl_o\[0\]
+wb_dcache_bry_o
+wb_dcache_dat_o\[31\]
+wb_dcache_dat_o\[30\]
+wb_dcache_dat_o\[29\]
+wb_dcache_dat_o\[28\]
+wb_dcache_dat_o\[27\]
+wb_dcache_dat_o\[26\]
+wb_dcache_dat_o\[25\]
+wb_dcache_dat_o\[24\]
+wb_dcache_dat_o\[23\]
+wb_dcache_dat_o\[22\]
+wb_dcache_dat_o\[21\]
+wb_dcache_dat_o\[20\]
+wb_dcache_dat_o\[19\]
+wb_dcache_dat_o\[18\]
+wb_dcache_dat_o\[17\]
+wb_dcache_dat_o\[16\]
+wb_dcache_dat_o\[15\]
+wb_dcache_dat_o\[14\]
+wb_dcache_dat_o\[13\]
+wb_dcache_dat_o\[12\]
+wb_dcache_dat_o\[11\]
+wb_dcache_dat_o\[10\]
+wb_dcache_dat_o\[9\]
+wb_dcache_dat_o\[8\]
+wb_dcache_dat_o\[7\]
+wb_dcache_dat_o\[6\]
+wb_dcache_dat_o\[5\]
+wb_dcache_dat_o\[4\]
+wb_dcache_dat_o\[3\]
+wb_dcache_dat_o\[2\]
+wb_dcache_dat_o\[1\]
+wb_dcache_dat_o\[0\]
+wb_dcache_dat_i\[31\]
+wb_dcache_dat_i\[30\]
+wb_dcache_dat_i\[29\]
+wb_dcache_dat_i\[28\]
+wb_dcache_dat_i\[27\]
+wb_dcache_dat_i\[26\]
+wb_dcache_dat_i\[25\]
+wb_dcache_dat_i\[24\]
+wb_dcache_dat_i\[23\]
+wb_dcache_dat_i\[22\]
+wb_dcache_dat_i\[21\]
+wb_dcache_dat_i\[20\]
+wb_dcache_dat_i\[19\]
+wb_dcache_dat_i\[18\]
+wb_dcache_dat_i\[17\]
+wb_dcache_dat_i\[16\]
+wb_dcache_dat_i\[15\]
+wb_dcache_dat_i\[14\]
+wb_dcache_dat_i\[13\]
+wb_dcache_dat_i\[12\]
+wb_dcache_dat_i\[11\]
+wb_dcache_dat_i\[10\]
+wb_dcache_dat_i\[9\]
+wb_dcache_dat_i\[8\]
+wb_dcache_dat_i\[7\]
+wb_dcache_dat_i\[6\]
+wb_dcache_dat_i\[5\]
+wb_dcache_dat_i\[4\]
+wb_dcache_dat_i\[3\]
+wb_dcache_dat_i\[2\]
+wb_dcache_dat_i\[1\]
+wb_dcache_dat_i\[0\]
+wb_dcache_ack_i
+wb_dcache_lack_i
+wb_dcache_err_i
+wb_dcache_cyc_o
+
+wb_icache_stb_o 450 0 2
+wb_icache_we_o
+wb_icache_adr_o\[31\]
+wb_icache_adr_o\[30\]
+wb_icache_adr_o\[29\]
+wb_icache_adr_o\[28\]
+wb_icache_adr_o\[27\]
+wb_icache_adr_o\[26\]
+wb_icache_adr_o\[25\]
+wb_icache_adr_o\[24\]
+wb_icache_adr_o\[23\]
+wb_icache_adr_o\[22\]
+wb_icache_adr_o\[21\]
+wb_icache_adr_o\[20\]
+wb_icache_adr_o\[19\]
+wb_icache_adr_o\[18\]
+wb_icache_adr_o\[17\]
+wb_icache_adr_o\[16\]
+wb_icache_adr_o\[15\]
+wb_icache_adr_o\[14\]
+wb_icache_adr_o\[13\]
+wb_icache_adr_o\[12\]
+wb_icache_adr_o\[11\]
+wb_icache_adr_o\[10\]
+wb_icache_adr_o\[9\]
+wb_icache_adr_o\[8\]
+wb_icache_adr_o\[7\]
+wb_icache_adr_o\[6\]
+wb_icache_adr_o\[5\]
+wb_icache_adr_o\[4\]
+wb_icache_adr_o\[3\]
+wb_icache_adr_o\[2\]
+wb_icache_adr_o\[1\]
+wb_icache_adr_o\[0\]
+wb_icache_sel_o\[3\]
+wb_icache_sel_o\[2\]
+wb_icache_sel_o\[1\]
+wb_icache_sel_o\[0\]
+wb_icache_bl_o\[9\]
+wb_icache_bl_o\[8\]
+wb_icache_bl_o\[7\]
+wb_icache_bl_o\[6\]
+wb_icache_bl_o\[5\]
+wb_icache_bl_o\[4\]
+wb_icache_bl_o\[3\]
+wb_icache_bl_o\[2\]
+wb_icache_bl_o\[1\]
+wb_icache_bl_o\[0\]
+wb_icache_bry_o
+wb_icache_dat_i\[31\]
+wb_icache_dat_i\[30\]
+wb_icache_dat_i\[29\]
+wb_icache_dat_i\[28\]
+wb_icache_dat_i\[27\]
+wb_icache_dat_i\[26\]
+wb_icache_dat_i\[25\]
+wb_icache_dat_i\[24\]
+wb_icache_dat_i\[23\]
+wb_icache_dat_i\[22\]
+wb_icache_dat_i\[21\]
+wb_icache_dat_i\[20\]
+wb_icache_dat_i\[19\]
+wb_icache_dat_i\[18\]
+wb_icache_dat_i\[17\]
+wb_icache_dat_i\[16\]
+wb_icache_dat_i\[15\]
+wb_icache_dat_i\[14\]
+wb_icache_dat_i\[13\]
+wb_icache_dat_i\[12\]
+wb_icache_dat_i\[11\]
+wb_icache_dat_i\[10\]
+wb_icache_dat_i\[9\]
+wb_icache_dat_i\[8\]
+wb_icache_dat_i\[7\]
+wb_icache_dat_i\[6\]
+wb_icache_dat_i\[5\]
+wb_icache_dat_i\[4\]
+wb_icache_dat_i\[3\]
+wb_icache_dat_i\[2\]
+wb_icache_dat_i\[1\]
+wb_icache_dat_i\[0\]
+wb_icache_ack_i
+wb_icache_lack_i
+wb_icache_err_i
+wb_icache_cyc_o
+
+
+cpu_intf_rst_n
+
+
+#N
+core0_uid 000 0 2
+cpu_core_rst_n_sync\[0\]
+core0_imem_req_ack
+core0_imem_req
+core0_imem_cmd
+core0_imem_addr\[31\]
+core0_imem_addr\[30\]
+core0_imem_addr\[29\]
+core0_imem_addr\[28\]
+core0_imem_addr\[27\]
+core0_imem_addr\[26\]
+core0_imem_addr\[25\]
+core0_imem_addr\[24\]
+core0_imem_addr\[23\]
+core0_imem_addr\[22\]
+core0_imem_addr\[21\]
+core0_imem_addr\[20\]
+core0_imem_addr\[19\]
+core0_imem_addr\[18\]
+core0_imem_addr\[17\]
+core0_imem_addr\[16\]
+core0_imem_addr\[15\]
+core0_imem_addr\[14\]
+core0_imem_addr\[13\]
+core0_imem_addr\[12\]
+core0_imem_addr\[11\]
+core0_imem_addr\[10\]
+core0_imem_addr\[9\]
+core0_imem_addr\[8\]
+core0_imem_addr\[7\]
+core0_imem_addr\[6\]
+core0_imem_addr\[5\]
+core0_imem_addr\[4\]
+core0_imem_addr\[3\]
+core0_imem_addr\[2\]
+core0_imem_addr\[1\]
+core0_imem_addr\[0\]
+core0_imem_bl\[2\]
+core0_imem_bl\[1\]
+core0_imem_bl\[0\]
+core0_imem_rdata\[31\]
+core0_imem_rdata\[30\]
+core0_imem_rdata\[29\]
+core0_imem_rdata\[28\]
+core0_imem_rdata\[27\]
+core0_imem_rdata\[26\]
+core0_imem_rdata\[25\]
+core0_imem_rdata\[24\]
+core0_imem_rdata\[23\]
+core0_imem_rdata\[22\]
+core0_imem_rdata\[21\]
+core0_imem_rdata\[20\]
+core0_imem_rdata\[19\]
+core0_imem_rdata\[18\]
+core0_imem_rdata\[17\]
+core0_imem_rdata\[16\]
+core0_imem_rdata\[15\]
+core0_imem_rdata\[14\]
+core0_imem_rdata\[13\]
+core0_imem_rdata\[12\]
+core0_imem_rdata\[11\]
+core0_imem_rdata\[10\]
+core0_imem_rdata\[9\]
+core0_imem_rdata\[8\]
+core0_imem_rdata\[7\]
+core0_imem_rdata\[6\]
+core0_imem_rdata\[5\]
+core0_imem_rdata\[4\]
+core0_imem_rdata\[3\]
+core0_imem_rdata\[2\]
+core0_imem_rdata\[1\]
+core0_imem_rdata\[0\]
+core0_imem_resp\[1\]
+core0_imem_resp\[0\]
+
+core0_dmem_req_ack 100 0 2
+core0_dmem_req
+core0_dmem_cmd
+core0_dmem_width\[1\]
+core0_dmem_width\[0\]
+core0_dmem_addr\[31\]
+core0_dmem_addr\[30\]
+core0_dmem_addr\[29\]
+core0_dmem_addr\[28\]
+core0_dmem_addr\[27\]
+core0_dmem_addr\[26\]
+core0_dmem_addr\[25\]
+core0_dmem_addr\[24\]
+core0_dmem_addr\[23\]
+core0_dmem_addr\[22\]
+core0_dmem_addr\[21\]
+core0_dmem_addr\[20\]
+core0_dmem_addr\[19\]
+core0_dmem_addr\[18\]
+core0_dmem_addr\[17\]
+core0_dmem_addr\[16\]
+core0_dmem_addr\[15\]
+core0_dmem_addr\[14\]
+core0_dmem_addr\[13\]
+core0_dmem_addr\[12\]
+core0_dmem_addr\[11\]
+core0_dmem_addr\[10\]
+core0_dmem_addr\[9\]
+core0_dmem_addr\[8\]
+core0_dmem_addr\[7\]
+core0_dmem_addr\[6\]
+core0_dmem_addr\[5\]
+core0_dmem_addr\[4\]
+core0_dmem_addr\[3\]
+core0_dmem_addr\[2\]
+core0_dmem_addr\[1\]
+core0_dmem_addr\[0\]
+core0_dmem_wdata\[31\]
+core0_dmem_wdata\[30\]
+core0_dmem_wdata\[29\]
+core0_dmem_wdata\[28\]
+core0_dmem_wdata\[27\]
+core0_dmem_wdata\[26\]
+core0_dmem_wdata\[25\]
+core0_dmem_wdata\[24\]
+core0_dmem_wdata\[23\]
+core0_dmem_wdata\[22\]
+core0_dmem_wdata\[21\]
+core0_dmem_wdata\[20\]
+core0_dmem_wdata\[19\]
+core0_dmem_wdata\[18\]
+core0_dmem_wdata\[17\]
+core0_dmem_wdata\[16\]
+core0_dmem_wdata\[15\]
+core0_dmem_wdata\[14\]
+core0_dmem_wdata\[13\]
+core0_dmem_wdata\[12\]
+core0_dmem_wdata\[11\]
+core0_dmem_wdata\[10\]
+core0_dmem_wdata\[9\]
+core0_dmem_wdata\[8\]
+core0_dmem_wdata\[7\]
+core0_dmem_wdata\[6\]
+core0_dmem_wdata\[5\]
+core0_dmem_wdata\[4\]
+core0_dmem_wdata\[3\]
+core0_dmem_wdata\[2\]
+core0_dmem_wdata\[1\]
+core0_dmem_wdata\[0\]
+core0_dmem_rdata\[31\]
+core0_dmem_rdata\[30\]
+core0_dmem_rdata\[29\]
+core0_dmem_rdata\[28\]
+core0_dmem_rdata\[27\]
+core0_dmem_rdata\[26\]
+core0_dmem_rdata\[25\]
+core0_dmem_rdata\[24\]
+core0_dmem_rdata\[23\]
+core0_dmem_rdata\[22\]
+core0_dmem_rdata\[21\]
+core0_dmem_rdata\[20\]
+core0_dmem_rdata\[19\]
+core0_dmem_rdata\[18\]
+core0_dmem_rdata\[17\]
+core0_dmem_rdata\[16\]
+core0_dmem_rdata\[15\]
+core0_dmem_rdata\[14\]
+core0_dmem_rdata\[13\]
+core0_dmem_rdata\[12\]
+core0_dmem_rdata\[11\]
+core0_dmem_rdata\[10\]
+core0_dmem_rdata\[9\]
+core0_dmem_rdata\[8\]
+core0_dmem_rdata\[7\]
+core0_dmem_rdata\[6\]
+core0_dmem_rdata\[5\]
+core0_dmem_rdata\[4\]
+core0_dmem_rdata\[3\]
+core0_dmem_rdata\[2\]
+core0_dmem_rdata\[1\]
+core0_dmem_rdata\[0\]
+core0_dmem_resp\[1\]
+core0_dmem_resp\[0\]
+
+core0_debug\[48\] 200 0 2
+core0_debug\[47\]
+core0_debug\[46\]
+core0_debug\[45\]
+core0_debug\[44\]
+core0_debug\[43\]
+core0_debug\[42\]
+core0_debug\[41\]
+core0_debug\[40\]
+core0_debug\[39\]
+core0_debug\[38\]
+core0_debug\[37\]
+core0_debug\[36\]
+core0_debug\[35\]
+core0_debug\[34\]
+core0_debug\[33\]
+core0_debug\[32\]
+core0_debug\[31\]
+core0_debug\[30\]
+core0_debug\[29\]
+core0_debug\[28\]
+core0_debug\[27\]
+core0_debug\[26\]
+core0_debug\[25\]
+core0_debug\[24\]
+core0_debug\[23\]
+core0_debug\[22\]
+core0_debug\[21\]
+core0_debug\[20\]
+core0_debug\[19\]
+core0_debug\[18\]
+core0_debug\[17\]
+core0_debug\[16\]
+core0_debug\[15\]
+core0_debug\[14\]
+core0_debug\[13\]
+core0_debug\[12\]
+core0_debug\[11\]
+core0_debug\[10\]
+core0_debug\[9\]
+core0_debug\[8\]
+core0_debug\[7\]
+core0_debug\[6\]
+core0_debug\[5\]
+core0_debug\[4\]
+core0_debug\[3\]
+core0_debug\[2\]
+core0_debug\[1\]
+core0_debug\[0\]
+
+core1_uid 400 0 2
+cpu_core_rst_n_sync\[1\]
+core1_imem_req_ack
+core1_imem_req
+core1_imem_cmd
+core1_imem_addr\[31\]
+core1_imem_addr\[30\]
+core1_imem_addr\[29\]
+core1_imem_addr\[28\]
+core1_imem_addr\[27\]
+core1_imem_addr\[26\]
+core1_imem_addr\[25\]
+core1_imem_addr\[24\]
+core1_imem_addr\[23\]
+core1_imem_addr\[22\]
+core1_imem_addr\[21\]
+core1_imem_addr\[20\]
+core1_imem_addr\[19\]
+core1_imem_addr\[18\]
+core1_imem_addr\[17\]
+core1_imem_addr\[16\]
+core1_imem_addr\[15\]
+core1_imem_addr\[14\]
+core1_imem_addr\[13\]
+core1_imem_addr\[12\]
+core1_imem_addr\[11\]
+core1_imem_addr\[10\]
+core1_imem_addr\[9\]
+core1_imem_addr\[8\]
+core1_imem_addr\[7\]
+core1_imem_addr\[6\]
+core1_imem_addr\[5\]
+core1_imem_addr\[4\]
+core1_imem_addr\[3\]
+core1_imem_addr\[2\]
+core1_imem_addr\[1\]
+core1_imem_addr\[0\]
+core1_imem_bl\[2\]
+core1_imem_bl\[1\]
+core1_imem_bl\[0\]
+core1_imem_rdata\[31\]
+core1_imem_rdata\[30\]
+core1_imem_rdata\[29\]
+core1_imem_rdata\[28\]
+core1_imem_rdata\[27\]
+core1_imem_rdata\[26\]
+core1_imem_rdata\[25\]
+core1_imem_rdata\[24\]
+core1_imem_rdata\[23\]
+core1_imem_rdata\[22\]
+core1_imem_rdata\[21\]
+core1_imem_rdata\[20\]
+core1_imem_rdata\[19\]
+core1_imem_rdata\[18\]
+core1_imem_rdata\[17\]
+core1_imem_rdata\[16\]
+core1_imem_rdata\[15\]
+core1_imem_rdata\[14\]
+core1_imem_rdata\[13\]
+core1_imem_rdata\[12\]
+core1_imem_rdata\[11\]
+core1_imem_rdata\[10\]
+core1_imem_rdata\[9\]
+core1_imem_rdata\[8\]
+core1_imem_rdata\[7\]
+core1_imem_rdata\[6\]
+core1_imem_rdata\[5\]
+core1_imem_rdata\[4\]
+core1_imem_rdata\[3\]
+core1_imem_rdata\[2\]
+core1_imem_rdata\[1\]
+core1_imem_rdata\[0\]
+core1_imem_resp\[1\]
+core1_imem_resp\[0\]
+
+core1_dmem_req_ack 0500 0 2
+core1_dmem_req
+core1_dmem_cmd
+core1_dmem_width\[1\]
+core1_dmem_width\[0\]
+core1_dmem_addr\[31\]
+core1_dmem_addr\[30\]
+core1_dmem_addr\[29\]
+core1_dmem_addr\[28\]
+core1_dmem_addr\[27\]
+core1_dmem_addr\[26\]
+core1_dmem_addr\[25\]
+core1_dmem_addr\[24\]
+core1_dmem_addr\[23\]
+core1_dmem_addr\[22\]
+core1_dmem_addr\[21\]
+core1_dmem_addr\[20\]
+core1_dmem_addr\[19\]
+core1_dmem_addr\[18\]
+core1_dmem_addr\[17\]
+core1_dmem_addr\[16\]
+core1_dmem_addr\[15\]
+core1_dmem_addr\[14\]
+core1_dmem_addr\[13\]
+core1_dmem_addr\[12\]
+core1_dmem_addr\[11\]
+core1_dmem_addr\[10\]
+core1_dmem_addr\[9\]
+core1_dmem_addr\[8\]
+core1_dmem_addr\[7\]
+core1_dmem_addr\[6\]
+core1_dmem_addr\[5\]
+core1_dmem_addr\[4\]
+core1_dmem_addr\[3\]
+core1_dmem_addr\[2\]
+core1_dmem_addr\[1\]
+core1_dmem_addr\[0\]
+core1_dmem_wdata\[31\]
+core1_dmem_wdata\[30\]
+core1_dmem_wdata\[29\]
+core1_dmem_wdata\[28\]
+core1_dmem_wdata\[27\]
+core1_dmem_wdata\[26\]
+core1_dmem_wdata\[25\]
+core1_dmem_wdata\[24\]
+core1_dmem_wdata\[23\]
+core1_dmem_wdata\[22\]
+core1_dmem_wdata\[21\]
+core1_dmem_wdata\[20\]
+core1_dmem_wdata\[19\]
+core1_dmem_wdata\[18\]
+core1_dmem_wdata\[17\]
+core1_dmem_wdata\[16\]
+core1_dmem_wdata\[15\]
+core1_dmem_wdata\[14\]
+core1_dmem_wdata\[13\]
+core1_dmem_wdata\[12\]
+core1_dmem_wdata\[11\]
+core1_dmem_wdata\[10\]
+core1_dmem_wdata\[9\]
+core1_dmem_wdata\[8\]
+core1_dmem_wdata\[7\]
+core1_dmem_wdata\[6\]
+core1_dmem_wdata\[5\]
+core1_dmem_wdata\[4\]
+core1_dmem_wdata\[3\]
+core1_dmem_wdata\[2\]
+core1_dmem_wdata\[1\]
+core1_dmem_wdata\[0\]
+core1_dmem_rdata\[31\]
+core1_dmem_rdata\[30\]
+core1_dmem_rdata\[29\]
+core1_dmem_rdata\[28\]
+core1_dmem_rdata\[27\]
+core1_dmem_rdata\[26\]
+core1_dmem_rdata\[25\]
+core1_dmem_rdata\[24\]
+core1_dmem_rdata\[23\]
+core1_dmem_rdata\[22\]
+core1_dmem_rdata\[21\]
+core1_dmem_rdata\[20\]
+core1_dmem_rdata\[19\]
+core1_dmem_rdata\[18\]
+core1_dmem_rdata\[17\]
+core1_dmem_rdata\[16\]
+core1_dmem_rdata\[15\]
+core1_dmem_rdata\[14\]
+core1_dmem_rdata\[13\]
+core1_dmem_rdata\[12\]
+core1_dmem_rdata\[11\]
+core1_dmem_rdata\[10\]
+core1_dmem_rdata\[9\]
+core1_dmem_rdata\[8\]
+core1_dmem_rdata\[7\]
+core1_dmem_rdata\[6\]
+core1_dmem_rdata\[5\]
+core1_dmem_rdata\[4\]
+core1_dmem_rdata\[3\]
+core1_dmem_rdata\[2\]
+core1_dmem_rdata\[1\]
+core1_dmem_rdata\[0\]
+core1_dmem_resp\[1\]
+core1_dmem_resp\[0\]
+
+core1_debug\[48\] 0600 0 2
+core1_debug\[47\]
+core1_debug\[46\]
+core1_debug\[45\]
+core1_debug\[44\]
+core1_debug\[43\]
+core1_debug\[42\]
+core1_debug\[41\]
+core1_debug\[40\]
+core1_debug\[39\]
+core1_debug\[38\]
+core1_debug\[37\]
+core1_debug\[36\]
+core1_debug\[35\]
+core1_debug\[34\]
+core1_debug\[33\]
+core1_debug\[32\]
+core1_debug\[31\]
+core1_debug\[30\]
+core1_debug\[29\]
+core1_debug\[28\]
+core1_debug\[27\]
+core1_debug\[26\]
+core1_debug\[25\]
+core1_debug\[24\]
+core1_debug\[23\]
+core1_debug\[22\]
+core1_debug\[21\]
+core1_debug\[20\]
+core1_debug\[19\]
+core1_debug\[18\]
+core1_debug\[17\]
+core1_debug\[16\]
+core1_debug\[15\]
+core1_debug\[14\]
+core1_debug\[13\]
+core1_debug\[12\]
+core1_debug\[11\]
+core1_debug\[10\]
+core1_debug\[9\]
+core1_debug\[8\]
+core1_debug\[7\]
+core1_debug\[6\]
+core1_debug\[5\]
+core1_debug\[4\]
+core1_debug\[3\]
+core1_debug\[2\]
+core1_debug\[1\]
+core1_debug\[0\]
+
+timer_irq 0700 0 2
+timer_val\[63\]
+timer_val\[62\]
+timer_val\[61\]
+timer_val\[60\]
+timer_val\[59\]
+timer_val\[58\]
+timer_val\[57\]
+timer_val\[56\]
+timer_val\[55\]
+timer_val\[54\]
+timer_val\[53\]
+timer_val\[52\]
+timer_val\[51\]
+timer_val\[50\]
+timer_val\[49\]
+timer_val\[48\]
+timer_val\[47\]
+timer_val\[46\]
+timer_val\[45\]
+timer_val\[44\]
+timer_val\[43\]
+timer_val\[42\]
+timer_val\[41\]
+timer_val\[40\]
+timer_val\[39\]
+timer_val\[38\]
+timer_val\[37\]
+timer_val\[36\]
+timer_val\[35\]
+timer_val\[34\]
+timer_val\[33\]
+timer_val\[32\]
+timer_val\[31\]
+timer_val\[30\]
+timer_val\[29\]
+timer_val\[28\]
+timer_val\[27\]
+timer_val\[26\]
+timer_val\[25\]
+timer_val\[24\]
+timer_val\[23\]
+timer_val\[22\]
+timer_val\[21\]
+timer_val\[20\]
+timer_val\[19\]
+timer_val\[18\]
+timer_val\[17\]
+timer_val\[16\]
+timer_val\[15\]
+timer_val\[14\]
+timer_val\[13\]
+timer_val\[12\]
+timer_val\[11\]
+timer_val\[10\]
+timer_val\[9\]
+timer_val\[8\]
+timer_val\[7\]
+timer_val\[6\]
+timer_val\[5\]
+timer_val\[4\]
+timer_val\[3\]
+timer_val\[2\]
+timer_val\[1\]
+timer_val\[0\]
+
+pwrup_rst_n_sync
+rst_n_sync
+test_mode
+test_rst_n
+
diff --git a/openlane/ycr_core/base.sdc b/openlane/ycr_core/base.sdc
new file mode 100644
index 0000000..51d4ab8
--- /dev/null
+++ b/openlane/ycr_core/base.sdc
@@ -0,0 +1,26 @@
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 20.0000 [get_ports {clk}]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/openlane/ycr_core/config.tcl b/openlane/ycr_core/config.tcl
new file mode 100644
index 0000000..a1aa12a
--- /dev/null
+++ b/openlane/ycr_core/config.tcl
@@ -0,0 +1,92 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(ROUTING_CORES) "6"
+
+set ::env(DESIGN_NAME) ycr_core_top
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "clk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+set ::env(LEC_ENABLE) 0
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_top.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_core_top.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_dm.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_tapc_synchronizer.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_clk_ctrl.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_scu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_tapc.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_tapc_shift_reg.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_dmi.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ifu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_idu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_exu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mprf.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_csr.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ialu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mul.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_div.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_lsu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_tdu.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_ipic.sv \
+ "
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+## Floorplan
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 700 850 "
+
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+set ::env(PL_TARGET_DENSITY) 0.36
+
+
+set ::env(RT_MAX_LAYER) {met4}
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+
+#Need to cross-check why global timing opimization creating setup vio with hugh hold fix
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+
diff --git a/openlane/ycr_core/macro_placement.cfg b/openlane/ycr_core/macro_placement.cfg
new file mode 100644
index 0000000..8ec6301
--- /dev/null
+++ b/openlane/ycr_core/macro_placement.cfg
@@ -0,0 +1,2 @@
+u_icache.u_cmem_2kb 285.000 291.000 FS
+u_dcache.u_cmem_2kb 1185.000 291.000 N
diff --git a/openlane/ycr_core/pin_order.cfg b/openlane/ycr_core/pin_order.cfg
new file mode 100644
index 0000000..c4f8e53
--- /dev/null
+++ b/openlane/ycr_core/pin_order.cfg
@@ -0,0 +1,357 @@
+#BUS_SORT
+#MANUAL_PLACE
+#S
+core_fuse_mhartid_i\[0\] 0000 00 2
+cpu_rst_n
+imem2core_req_ack_i
+core2imem_req_o
+core2imem_cmd_o
+core2imem_addr_o\[31\]
+core2imem_addr_o\[30\]
+core2imem_addr_o\[29\]
+core2imem_addr_o\[28\]
+core2imem_addr_o\[27\]
+core2imem_addr_o\[26\]
+core2imem_addr_o\[25\]
+core2imem_addr_o\[24\]
+core2imem_addr_o\[23\]
+core2imem_addr_o\[22\]
+core2imem_addr_o\[21\]
+core2imem_addr_o\[20\]
+core2imem_addr_o\[19\]
+core2imem_addr_o\[18\]
+core2imem_addr_o\[17\]
+core2imem_addr_o\[16\]
+core2imem_addr_o\[15\]
+core2imem_addr_o\[14\]
+core2imem_addr_o\[13\]
+core2imem_addr_o\[12\]
+core2imem_addr_o\[11\]
+core2imem_addr_o\[10\]
+core2imem_addr_o\[9\]
+core2imem_addr_o\[8\]
+core2imem_addr_o\[7\]
+core2imem_addr_o\[6\]
+core2imem_addr_o\[5\]
+core2imem_addr_o\[4\]
+core2imem_addr_o\[3\]
+core2imem_addr_o\[2\]
+core2imem_addr_o\[1\]
+core2imem_addr_o\[0\]
+core2imem_bl_o\[2\]
+core2imem_bl_o\[1\]
+core2imem_bl_o\[0\]
+imem2core_rdata_i\[31\]
+imem2core_rdata_i\[30\]
+imem2core_rdata_i\[29\]
+imem2core_rdata_i\[28\]
+imem2core_rdata_i\[27\]
+imem2core_rdata_i\[26\]
+imem2core_rdata_i\[25\]
+imem2core_rdata_i\[24\]
+imem2core_rdata_i\[23\]
+imem2core_rdata_i\[22\]
+imem2core_rdata_i\[21\]
+imem2core_rdata_i\[20\]
+imem2core_rdata_i\[19\]
+imem2core_rdata_i\[18\]
+imem2core_rdata_i\[17\]
+imem2core_rdata_i\[16\]
+imem2core_rdata_i\[15\]
+imem2core_rdata_i\[14\]
+imem2core_rdata_i\[13\]
+imem2core_rdata_i\[12\]
+imem2core_rdata_i\[11\]
+imem2core_rdata_i\[10\]
+imem2core_rdata_i\[9\]
+imem2core_rdata_i\[8\]
+imem2core_rdata_i\[7\]
+imem2core_rdata_i\[6\]
+imem2core_rdata_i\[5\]
+imem2core_rdata_i\[4\]
+imem2core_rdata_i\[3\]
+imem2core_rdata_i\[2\]
+imem2core_rdata_i\[1\]
+imem2core_rdata_i\[0\]
+imem2core_resp_i\[1\]
+imem2core_resp_i\[0\]
+
+dmem2core_req_ack_i 0100 0 2
+core2dmem_req_o
+core2dmem_cmd_o
+core2dmem_width_o\[1\]
+core2dmem_width_o\[0\]
+core2dmem_addr_o\[31\]
+core2dmem_addr_o\[30\]
+core2dmem_addr_o\[29\]
+core2dmem_addr_o\[28\]
+core2dmem_addr_o\[27\]
+core2dmem_addr_o\[26\]
+core2dmem_addr_o\[25\]
+core2dmem_addr_o\[24\]
+core2dmem_addr_o\[23\]
+core2dmem_addr_o\[22\]
+core2dmem_addr_o\[21\]
+core2dmem_addr_o\[20\]
+core2dmem_addr_o\[19\]
+core2dmem_addr_o\[18\]
+core2dmem_addr_o\[17\]
+core2dmem_addr_o\[16\]
+core2dmem_addr_o\[15\]
+core2dmem_addr_o\[14\]
+core2dmem_addr_o\[13\]
+core2dmem_addr_o\[12\]
+core2dmem_addr_o\[11\]
+core2dmem_addr_o\[10\]
+core2dmem_addr_o\[9\]
+core2dmem_addr_o\[8\]
+core2dmem_addr_o\[7\]
+core2dmem_addr_o\[6\]
+core2dmem_addr_o\[5\]
+core2dmem_addr_o\[4\]
+core2dmem_addr_o\[3\]
+core2dmem_addr_o\[2\]
+core2dmem_addr_o\[1\]
+core2dmem_addr_o\[0\]
+core2dmem_wdata_o\[31\]
+core2dmem_wdata_o\[30\]
+core2dmem_wdata_o\[29\]
+core2dmem_wdata_o\[28\]
+core2dmem_wdata_o\[27\]
+core2dmem_wdata_o\[26\]
+core2dmem_wdata_o\[25\]
+core2dmem_wdata_o\[24\]
+core2dmem_wdata_o\[23\]
+core2dmem_wdata_o\[22\]
+core2dmem_wdata_o\[21\]
+core2dmem_wdata_o\[20\]
+core2dmem_wdata_o\[19\]
+core2dmem_wdata_o\[18\]
+core2dmem_wdata_o\[17\]
+core2dmem_wdata_o\[16\]
+core2dmem_wdata_o\[15\]
+core2dmem_wdata_o\[14\]
+core2dmem_wdata_o\[13\]
+core2dmem_wdata_o\[12\]
+core2dmem_wdata_o\[11\]
+core2dmem_wdata_o\[10\]
+core2dmem_wdata_o\[9\]
+core2dmem_wdata_o\[8\]
+core2dmem_wdata_o\[7\]
+core2dmem_wdata_o\[6\]
+core2dmem_wdata_o\[5\]
+core2dmem_wdata_o\[4\]
+core2dmem_wdata_o\[3\]
+core2dmem_wdata_o\[2\]
+core2dmem_wdata_o\[1\]
+core2dmem_wdata_o\[0\]
+dmem2core_rdata_i\[31\]
+dmem2core_rdata_i\[30\]
+dmem2core_rdata_i\[29\]
+dmem2core_rdata_i\[28\]
+dmem2core_rdata_i\[27\]
+dmem2core_rdata_i\[26\]
+dmem2core_rdata_i\[25\]
+dmem2core_rdata_i\[24\]
+dmem2core_rdata_i\[23\]
+dmem2core_rdata_i\[22\]
+dmem2core_rdata_i\[21\]
+dmem2core_rdata_i\[20\]
+dmem2core_rdata_i\[19\]
+dmem2core_rdata_i\[18\]
+dmem2core_rdata_i\[17\]
+dmem2core_rdata_i\[16\]
+dmem2core_rdata_i\[15\]
+dmem2core_rdata_i\[14\]
+dmem2core_rdata_i\[13\]
+dmem2core_rdata_i\[12\]
+dmem2core_rdata_i\[11\]
+dmem2core_rdata_i\[10\]
+dmem2core_rdata_i\[9\]
+dmem2core_rdata_i\[8\]
+dmem2core_rdata_i\[7\]
+dmem2core_rdata_i\[6\]
+dmem2core_rdata_i\[5\]
+dmem2core_rdata_i\[4\]
+dmem2core_rdata_i\[3\]
+dmem2core_rdata_i\[2\]
+dmem2core_rdata_i\[1\]
+dmem2core_rdata_i\[0\]
+dmem2core_resp_i\[1\]
+dmem2core_resp_i\[0\]
+
+core_debug\[48\] 0200 0 2
+core_debug\[47\]
+core_debug\[46\]
+core_debug\[45\]
+core_debug\[44\]
+core_debug\[43\]
+core_debug\[42\]
+core_debug\[41\]
+core_debug\[40\]
+core_debug\[39\]
+core_debug\[38\]
+core_debug\[37\]
+core_debug\[36\]
+core_debug\[35\]
+core_debug\[34\]
+core_debug\[33\]
+core_debug\[32\]
+core_debug\[31\]
+core_debug\[30\]
+core_debug\[29\]
+core_debug\[28\]
+core_debug\[27\]
+core_debug\[26\]
+core_debug\[25\]
+core_debug\[24\]
+core_debug\[23\]
+core_debug\[22\]
+core_debug\[21\]
+core_debug\[20\]
+core_debug\[19\]
+core_debug\[18\]
+core_debug\[17\]
+core_debug\[16\]
+core_debug\[15\]
+core_debug\[14\]
+core_debug\[13\]
+core_debug\[12\]
+core_debug\[11\]
+core_debug\[10\]
+core_debug\[9\]
+core_debug\[8\]
+core_debug\[7\]
+core_debug\[6\]
+core_debug\[5\]
+core_debug\[4\]
+core_debug\[3\]
+core_debug\[2\]
+core_debug\[1\]
+core_debug\[0\]
+
+core_irq_mtimer_i 0300 0 2
+core_mtimer_val_i\[63\]
+core_mtimer_val_i\[62\]
+core_mtimer_val_i\[61\]
+core_mtimer_val_i\[60\]
+core_mtimer_val_i\[59\]
+core_mtimer_val_i\[58\]
+core_mtimer_val_i\[57\]
+core_mtimer_val_i\[56\]
+core_mtimer_val_i\[55\]
+core_mtimer_val_i\[54\]
+core_mtimer_val_i\[53\]
+core_mtimer_val_i\[52\]
+core_mtimer_val_i\[51\]
+core_mtimer_val_i\[50\]
+core_mtimer_val_i\[49\]
+core_mtimer_val_i\[48\]
+core_mtimer_val_i\[47\]
+core_mtimer_val_i\[46\]
+core_mtimer_val_i\[45\]
+core_mtimer_val_i\[44\]
+core_mtimer_val_i\[43\]
+core_mtimer_val_i\[42\]
+core_mtimer_val_i\[41\]
+core_mtimer_val_i\[40\]
+core_mtimer_val_i\[39\]
+core_mtimer_val_i\[38\]
+core_mtimer_val_i\[37\]
+core_mtimer_val_i\[36\]
+core_mtimer_val_i\[35\]
+core_mtimer_val_i\[34\]
+core_mtimer_val_i\[33\]
+core_mtimer_val_i\[32\]
+core_mtimer_val_i\[31\]
+core_mtimer_val_i\[30\]
+core_mtimer_val_i\[29\]
+core_mtimer_val_i\[28\]
+core_mtimer_val_i\[27\]
+core_mtimer_val_i\[26\]
+core_mtimer_val_i\[25\]
+core_mtimer_val_i\[24\]
+core_mtimer_val_i\[23\]
+core_mtimer_val_i\[22\]
+core_mtimer_val_i\[21\]
+core_mtimer_val_i\[20\]
+core_mtimer_val_i\[19\]
+core_mtimer_val_i\[18\]
+core_mtimer_val_i\[17\]
+core_mtimer_val_i\[16\]
+core_mtimer_val_i\[15\]
+core_mtimer_val_i\[14\]
+core_mtimer_val_i\[13\]
+core_mtimer_val_i\[12\]
+core_mtimer_val_i\[11\]
+core_mtimer_val_i\[10\]
+core_mtimer_val_i\[9\]
+core_mtimer_val_i\[8\]
+core_mtimer_val_i\[7\]
+core_mtimer_val_i\[6\]
+core_mtimer_val_i\[5\]
+core_mtimer_val_i\[4\]
+core_mtimer_val_i\[3\]
+core_mtimer_val_i\[2\]
+core_mtimer_val_i\[1\]
+core_mtimer_val_i\[0\]
+
+pwrup_rst_n
+rst_n
+test_mode
+test_rst_n
+
+
+core_fuse_mhartid_i\[31\]
+core_fuse_mhartid_i\[30\]
+core_fuse_mhartid_i\[29\]
+core_fuse_mhartid_i\[28\]
+core_fuse_mhartid_i\[27\]
+core_fuse_mhartid_i\[26\]
+core_fuse_mhartid_i\[25\]
+core_fuse_mhartid_i\[24\]
+core_fuse_mhartid_i\[23\]
+core_fuse_mhartid_i\[22\]
+core_fuse_mhartid_i\[21\]
+core_fuse_mhartid_i\[20\]
+core_fuse_mhartid_i\[19\]
+core_fuse_mhartid_i\[18\]
+core_fuse_mhartid_i\[17\]
+core_fuse_mhartid_i\[16\]
+core_fuse_mhartid_i\[15\]
+core_fuse_mhartid_i\[14\]
+core_fuse_mhartid_i\[13\]
+core_fuse_mhartid_i\[12\]
+core_fuse_mhartid_i\[11\]
+core_fuse_mhartid_i\[10\]
+core_fuse_mhartid_i\[9\]
+core_fuse_mhartid_i\[8\]
+core_fuse_mhartid_i\[7\]
+core_fuse_mhartid_i\[6\]
+core_fuse_mhartid_i\[5\]
+core_fuse_mhartid_i\[4\]
+core_fuse_mhartid_i\[3\]
+core_fuse_mhartid_i\[2\]
+core_fuse_mhartid_i\[1\]
+
+core_irq_lines_i\[15\]
+core_irq_lines_i\[14\]
+core_irq_lines_i\[13\]
+core_irq_lines_i\[12\]
+core_irq_lines_i\[11\]
+core_irq_lines_i\[10\]
+core_irq_lines_i\[9\]
+core_irq_lines_i\[8\]
+core_irq_lines_i\[7\]
+core_irq_lines_i\[6\]
+core_irq_lines_i\[5\]
+core_irq_lines_i\[4\]
+core_irq_lines_i\[3\]
+core_irq_lines_i\[2\]
+core_irq_lines_i\[1\]
+core_irq_lines_i\[0\]
+core_irq_soft_i
+
+clk
+core_rst_n_o
+core_rdc_qlfy_o
diff --git a/signoff/pinmux/PDK_SOURCES b/signoff/pinmux/PDK_SOURCES
index ca3684a..22e7dc1 100644
--- a/signoff/pinmux/PDK_SOURCES
+++ b/signoff/pinmux/PDK_SOURCES
@@ -1,6 +1,3 @@
--ne openlane
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index 7337820..422cccf 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h16m12s,-1,46109.09090909091,0.2475,23054.545454545456,27.07,714.13,5706,0,0,0,0,0,0,-1,1,0,-1,-1,434666,61807,0.0,-0.01,-1,0.0,-1,0.0,-0.03,-1,0.0,-1,320204079.0,5.99,43.88,33.8,11.89,0.3,-1,3574,8564,543,5532,0,0,0,4202,0,0,0,0,0,0,0,4,1343,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h7m46s0ms,0h5m1s0ms,43806.06060606061,0.2475,21903.030303030304,26.1,891.37,5421,0,0,0,0,0,0,0,-1,0,-1,-1,427475,54258,0.0,-0.31,-1,0.0,0.0,0.0,-0.96,-1,0.0,0.0,341607677.0,0.0,56.96,41.66,30.97,18.6,-1,3480,8519,562,5601,0,0,0,4063,123,107,40,77,933,109,14,285,1086,1034,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim/PDK_SOURCES b/signoff/qspim/PDK_SOURCES
index ca3684a..22e7dc1 100644
--- a/signoff/qspim/PDK_SOURCES
+++ b/signoff/qspim/PDK_SOURCES
@@ -1,6 +1,3 @@
--ne openlane
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv
index eafe299..335f6f1 100644
--- a/signoff/qspim/final_summary_report.csv
+++ b/signoff/qspim/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h18m13s,-1,69139.39393939394,0.2475,34569.69696969697,39.57,778.62,8556,0,0,0,0,0,0,-1,1,0,-1,-1,423083,80674,-0.2,-5.37,-1,0.0,-1,-6.1,-2269.63,-1,0.0,-1,266384048.0,0.0,40.72,38.22,6.38,1.41,-1,7371,11035,803,4466,0,0,0,8344,0,0,0,0,0,0,0,4,2003,2524,22,388,3234,0,3622,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.42,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/qspim,qspim_top,qspim,flow completed,0h12m4s0ms,0h8m46s0ms,65664.64646464646,0.2475,32832.32323232323,37.94,1000.87,8126,0,0,0,0,0,0,0,-1,0,-1,-1,392720,69830,-0.58,-5.13,-1,0.0,0.0,-34.73,-2037.41,-1,0.0,0.0,257576668.0,0.0,48.93,48.14,17.63,18.71,-1,7367,11031,803,4466,0,0,0,8341,263,96,194,115,1413,214,34,1460,1553,1517,18,388,3234,0,3622,100.0,10.0,10,AREA 0,4,50,1,100,100,0.42,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi/PDK_SOURCES b/signoff/uart_i2cm_usb_spi/PDK_SOURCES
index ca3684a..22e7dc1 100644
--- a/signoff/uart_i2cm_usb_spi/PDK_SOURCES
+++ b/signoff/uart_i2cm_usb_spi/PDK_SOURCES
@@ -1,6 +1,3 @@
--ne openlane
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/uart_i2cm_usb_spi/final_summary_report.csv b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
index 82f2b7b..ab09edd 100644
--- a/signoff/uart_i2cm_usb_spi/final_summary_report.csv
+++ b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h13m36s,-1,63977.14285714286,0.35,31988.57142857143,37.54,836.07,11196,0,0,0,0,0,0,-1,1,0,-1,-1,434083,97891,-4.52,-4.86,-1,-4.69,-1,-141.37,-151.91,-1,-139.26,-1,264395920.0,0.39,30.63,28.98,0.99,0.4,-1,8563,12970,1541,5891,0,0,0,9737,0,0,0,0,0,0,0,4,2730,2694,26,498,4643,0,5141,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow completed,0h21m12s0ms,0h16m10s0ms,69377.14285714286,0.35,34688.57142857143,39.46,1340.21,12141,0,0,0,0,0,0,0,-1,0,-1,-1,562021,101968,-3.48,-3.71,-1,-3.61,-3.64,-107.08,-112.91,-1,-117.02,-116.69,361088707.0,0.0,49.42,49.35,17.1,19.4,-1,8563,12956,1538,5867,0,0,0,9739,384,231,256,254,2189,356,86,774,2441,2349,19,498,4643,0,5141,73.31378299120234,13.64,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index a731e6b..6910b9d 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h49m56s0ms,0h3m54s0ms,-2.0,-1,-1,-1,556.96,14,0,0,0,0,0,0,-1,0,1,-1,-1,1417872,9018,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,6.67,6.71,1.05,1.33,-1,313,2877,313,2877,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,120,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h43m48s0ms,0h4m4s0ms,-2.0,-1,-1,-1,589.75,11,0,0,0,0,0,0,-1,0,0,-1,-1,1906026,14065,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.76,7.73,2.42,0.84,0.0,318,3364,318,3364,0,0,0,11,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,100,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index ca3684a..22e7dc1 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES
@@ -1,6 +1,3 @@
--ne openlane
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 7be1787..6a37170 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h10m23s,-1,51962.5,0.16,25981.25,34.69,645.3,4157,0,0,0,0,0,0,0,5,0,0,-1,329531,47752,0.0,-0.23,-1,0.0,-1,0.0,-26.36,-1,0.0,-1,265017619.0,4.63,61.49,19.26,29.21,0.09,-1,3490,6163,1024,3553,0,0,0,3793,0,0,0,0,0,0,0,4,1233,1205,17,130,2043,0,2173,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m54s0ms,0h4m3s0ms,60517.64705882353,0.14875,30258.823529411766,36.67,777.48,4501,0,0,0,0,0,0,0,4,0,0,-1,207083,36502,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,156702042.0,0.0,46.57,48.25,3.69,11.24,-1,3461,6134,1009,3538,0,0,0,3773,372,52,74,184,652,130,23,458,1014,989,11,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index ca3684a..22e7dc1 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1,6 +1,3 @@
--ne openlane
-8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
--ne skywater-pdk
-c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
--ne open_pdks
-14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index 5f2f6ea..481675a 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h18m24s,-1,19852.173913043476,0.46,9926.086956521738,9.27,726.88,4566,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,848196,51567,-0.9,-9.3,-1,-1.34,-1,-99.69,-2508.48,-1,-173.72,-1,745063608.0,0.0,15.97,52.54,2.07,42.24,0.0,1776,5292,252,3767,0,0,0,2682,0,0,0,0,0,0,0,4,1192,1079,18,1674,5873,0,7547,90.9090909090909,11,10,AREA 0,2,50,1,153.6,153.18,0.3,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h35m55s0ms,0h32m6s0ms,22860.869565217392,0.46,11430.434782608696,9.82,1061.57,5258,0,0,0,0,0,0,0,-1,0,-1,-1,900638,55837,0.0,-2.26,-1,-1.76,-2.22,0.0,-101.82,-1,-197.22,-286.21,832828329.0,0.0,24.44,49.29,2.25,39.09,-1,1460,4695,237,3471,0,0,0,2321,146,4,12,55,280,29,6,550,919,860,20,1674,5873,0,7547,81.8330605564648,12.22,10,AREA 0,2,50,1,120,120,0.3,0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/user_uart/simx.fst b/verilog/dv/user_uart/simx.fst
new file mode 100644
index 0000000..766079e
--- /dev/null
+++ b/verilog/dv/user_uart/simx.fst
Binary files differ
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index c1c1a56..bb53fb1 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -59,6 +59,8 @@
output logic i2cm_rst_n ,
output logic usb_rst_n ,
+ output logic [1:0] cfg_riscv_debug_sel,
+
// Reg Bus Interface Signal
input logic reg_cs,
input logic reg_wr,
@@ -281,6 +283,8 @@
.i2cm_rst_n (i2cm_rst_n ),
.usb_rst_n (usb_rst_n ),
+ .cfg_riscv_debug_sel (cfg_riscv_debug_sel ),
+
// Reg read/write Interface Inputs
.reg_cs (reg_cs ),
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 1e7ad9f..5794be8 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -73,6 +73,7 @@
input logic i2cm_intr,
output logic [9:0] cfg_pulse_1us,
+ output logic [1:0] cfg_riscv_debug_sel,
//---------------------------------------------------
// 6 PWM Configuration
@@ -347,7 +348,8 @@
.data_out (reg_3 )
);
-assign cfg_pulse_1us = reg_3[9:0];
+assign cfg_pulse_1us = reg_3[9:0];
+assign cfg_riscv_debug_sel = reg_3[31:30];
//-----------------------------------------------------------------------
// Logic for gpio_data_in
//-----------------------------------------------------------------------
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index f08cd4c..c8e4874 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -560,6 +560,7 @@
wire [3:0] spi_csn ;
+wire [1:0] cfg_riscv_debug_sel ;
/////////////////////////////////////////////////////////
// Clock Skew Ctrl
@@ -654,6 +655,7 @@
.cpu_intf_rst_n (cpu_intf_rst_n ),
.cpu_core_rst_n (cpu_core_rst_n ),
.riscv_debug (riscv_debug ),
+ .core_debug_sel (cfg_riscv_debug_sel ),
// Clock
.core_clk (cpu_clk ),
@@ -1132,6 +1134,8 @@
.i2cm_rst_n (i2c_rst_n ),
.usb_rst_n (usb_rst_n ),
+ .cfg_riscv_debug_sel (cfg_riscv_debug_sel ),
+
// Reg Bus Interface Signal
.reg_cs (wbd_glbl_stb_o ),
.reg_wr (wbd_glbl_we_o ),
diff --git a/verilog/rtl/yifive/ycr2c b/verilog/rtl/yifive/ycr2c
index d2ab5c6..5ed3623 160000
--- a/verilog/rtl/yifive/ycr2c
+++ b/verilog/rtl/yifive/ycr2c
@@ -1 +1 @@
-Subproject commit d2ab5c6787943530e98b18dfc3a92bdbe97756e5
+Subproject commit 5ed36234610007cd65e054f1f89ce6f1db7b188c
