spi cs config update to match with arduino requirement
diff --git a/README.md b/README.md
index 9197bf1..5f73675 100644
--- a/README.md
+++ b/README.md
@@ -685,8 +685,8 @@
make verify-user_uart_master - standalone user uart master test
make verify-user_sram_exec - standalone riscv core-0 test with executing code from data memory
make verify-riscv_regress - standalone riscv compliance test suite
- make verify-arudino_risc_boot - standalone riscv core-0 boot using arduino tool set
- make verify-arudino_hello_world - standalone riscv core-0 hello world test using arduino tool set
+ make verify-arduino_risc_boot - standalone riscv core-0 boot using arduino tool set
+ make verify-arduino_hello_world - standalone riscv core-0 hello world test using arduino tool set
make verify-user_mcore - standalone riscv multi-core test
make verify-user_sram_exec RISC_CORE=1 - standalone riscv core-1 test with executing code from data memory
make verify-user_risc_boot RISC_CORE=1 - standalone user risc core-1 boot test
@@ -694,8 +694,8 @@
make verify-user_uart1 RISC_CORE=1 - Standalone user uart test using user risc core-1
make verify-user_aes RISC_CORE=1 - standalone aes test with risc core-1
make verify-user_cache_bypass RISC_CORE=1 - standalone icache and dcache bypass test with risc core-1
- make verify-arudino_risc_boot RISC_CORE=1 - standalone riscv core-1 boot using arduino tool set
- make verify-arudino_hello_world RISC_CORE=1 - standalone riscv core-1 hello world test using arduino tool set
+ make verify-arduino_risc_boot RISC_CORE=1 - standalone riscv core-1 boot using arduino tool set
+ make verify-arduino_hello_world RISC_CORE=1 - standalone riscv core-1 hello world test using arduino tool set
make verify-user_uart SIM=RTL DUMP=OFF - Standalone user uart-0 test using user risc core with waveform dump off
make verify-user_uart SIM=RTL DUMP=ON - Standalone user uart-0 test using user risc core with waveform dump on
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 9645d12..c469d16 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h53m42s0ms,0h3m56s0ms,-2.0,-1,-1,-1,578.62,13,0,0,0,0,0,0,-1,0,0,-1,-1,1415980,10509,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.37,6.1,1.48,2.78,0.0,367,3710,367,3710,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h51m28s0ms,0h3m44s0ms,-2.0,-1,-1,-1,557.84,13,0,0,0,0,0,0,-1,0,0,-1,-1,1416054,10511,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.38,6.15,1.46,2.65,0.0,367,3710,367,3710,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index 02e4326..950b657 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -51,12 +51,12 @@
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}]
-set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
-set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}]
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[1]}]
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}]
set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}]
diff --git a/verilog/dv/user_aes/user_aes_tb.v b/verilog/dv/user_aes/user_aes_tb.v
index 3d18ba5..3c46014 100644
--- a/verilog/dv/user_aes/user_aes_tb.v
+++ b/verilog/dv/user_aes/user_aes_tb.v
@@ -163,6 +163,9 @@
`endif
initial begin
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
uart_data_bit = 2'b11;
uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
uart_stick_parity = 0; // 1: force even parity
@@ -184,8 +187,14 @@
repeat (2) @(posedge clock);
#1;
- // Remove all the reset
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ end
repeat (100) @(posedge clock); // wait for Processor Get Ready
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index b1e5ba9..1d2a372 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -282,8 +282,8 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h1306_2022);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_6000);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0807_2022);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_7000);
end
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index e0f8219..e41e0d2 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -146,7 +146,7 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h01);
// Enable I2C Multi Functional Ports
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h4000);
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h8000);
// Remove i2m reset
wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h010);
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
index 1e81542..c8e3f5c 100644
--- a/verilog/dv/user_sspi/user_sspi_tb.v
+++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -140,7 +140,9 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
// Enable SPI Multi Functional Ports
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h3C00);
+ // wire cfg_spim_enb = cfg_multi_func_sel[10];
+ // wire [3:0] cfg_spim_cs_enb = cfg_multi_func_sel[14:11];
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h7C00);
repeat (2) @(posedge clock);
#1;
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index b9949c5..2f1ba44 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -37,6 +37,11 @@
//// 0.2 - 6 April 2021, Dinesh A ////
//// 1. SSPI CS# increased from 1 to 4 ////
// 2. UART I/F increase from 1 to 2 ////
+//// 0.3 - 8 July 2022, Dinesh A ////
+//// In ardunio, SPI chip select are control through ////
+//// GPIO, So we have moved the Auto generated SPI CS ////
+//// different config bit. I2C config position moved from////
+//// bit[14] to bit [15] ////
//////////////////////////////////////////////////////////////////////
module pinmux (
@@ -548,8 +553,9 @@
assign cfg_pwm_enb = cfg_multi_func_sel[5:0];
wire [1:0] cfg_int_enb = cfg_multi_func_sel[7:6];
wire [1:0] cfg_uart_enb = cfg_multi_func_sel[9:8];
-wire [3:0] cfg_spim_enb = cfg_multi_func_sel[13:10];
-wire cfg_i2cm_enb = cfg_multi_func_sel[14];
+wire cfg_spim_enb = cfg_multi_func_sel[10];
+wire [3:0] cfg_spim_cs_enb = cfg_multi_func_sel[14:11];
+wire cfg_i2cm_enb = cfg_multi_func_sel[15];
wire [7:0] cfg_port_a_dir_sel = cfg_gpio_dir_sel[7:0];
wire [7:0] cfg_port_b_dir_sel = cfg_gpio_dir_sel[15:8];
@@ -618,7 +624,7 @@
//Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
port_b_in[3] = digital_io_in[14];
- if(cfg_spim_enb[0]) spim_mosi = digital_io_in[14];
+ if(cfg_spim_enb) spim_mosi = digital_io_in[14];
//Pin-18 PB4/MISO digital_io[15]
port_b_in[4] = digital_io_in[15];
@@ -692,12 +698,12 @@
//Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8]
if(cfg_pwm_enb[1]) digital_io_out[8] = pwm_wfm[1];
- else if(cfg_spim_enb[3]) digital_io_out[8] = spim_ssn[3];
+ else if(cfg_spim_cs_enb[3]) digital_io_out[8] = spim_ssn[3];
else if(cfg_port_d_dir_sel[5]) digital_io_out[8] = port_d_out[5];
//Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2]
if(cfg_pwm_enb[2]) digital_io_out[9] = pwm_wfm[2];
- else if(cfg_spim_enb[2]) digital_io_out[9] = spim_ssn[2];
+ else if(cfg_spim_cs_enb[2]) digital_io_out[9] = spim_ssn[2];
else if(cfg_port_d_dir_sel[6]) digital_io_out[9] = port_d_out[6];
@@ -709,12 +715,12 @@
//Pin-15 PB1/SS[1]/OC1A(PWM3) digital_io[12]
if(cfg_pwm_enb[3]) digital_io_out[12] = pwm_wfm[3];
- else if(cfg_spim_enb[1]) digital_io_out[12] = spim_ssn[1];
+ else if(cfg_spim_cs_enb[1]) digital_io_out[12] = spim_ssn[1];
else if(cfg_port_b_dir_sel[1]) digital_io_out[12] = port_b_out[1];
//Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13]
if(cfg_pwm_enb[4]) digital_io_out[13] = pwm_wfm[4];
- else if(cfg_spim_enb[0]) digital_io_out[13] = spim_ssn[0];
+ else if(cfg_spim_cs_enb[0]) digital_io_out[13] = spim_ssn[0];
else if(cfg_port_b_dir_sel[2]) digital_io_out[13] = port_b_out[2];
//Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
@@ -722,11 +728,11 @@
else if(cfg_port_b_dir_sel[3]) digital_io_out[14] = port_b_out[3];
//Pin-18 PB4/MISO digital_io[15]
- if(cfg_spim_enb[0]) digital_io_out[15] = spim_miso;
+ if(cfg_spim_enb) digital_io_out[15] = spim_miso;
else if(cfg_port_b_dir_sel[4]) digital_io_out[15] = port_b_out[4];
//Pin-19 PB5/SCK digital_io[16]
- if(cfg_spim_enb[0]) digital_io_out[16] = spim_sck;
+ if(cfg_spim_enb) digital_io_out[16] = spim_sck;
else if(cfg_port_b_dir_sel[5]) digital_io_out[16] = port_b_out[5];
//Pin-23 PC0/ADC0 digital_io[18]/analog_io[11]
@@ -808,12 +814,12 @@
//Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8]
if(cfg_pwm_enb[1]) digital_io_oen[8] = 1'b0;
- else if(cfg_spim_enb[3]) digital_io_oen[8] = 1'b0;
+ else if(cfg_spim_cs_enb[3]) digital_io_oen[8] = 1'b0;
else if(cfg_port_d_dir_sel[5]) digital_io_oen[8] = 1'b0;
//Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2]
if(cfg_pwm_enb[2]) digital_io_oen[9] = 1'b0;
- else if(cfg_spim_enb[2]) digital_io_oen[9] = 1'b0;
+ else if(cfg_spim_cs_enb[2]) digital_io_oen[9] = 1'b0;
else if(cfg_port_d_dir_sel[6]) digital_io_oen[9] = 1'b0;
//Pin-13 PD7/A1N1 digital_io[10]/analog_io[3]
@@ -824,25 +830,25 @@
//Pin-15 PB1/SS[1]/OC1A(PWM3) digital_io[12]
if(cfg_pwm_enb[3]) digital_io_oen[12] = 1'b0;
- else if(cfg_spim_enb[1]) digital_io_oen[12] = 1'b0;
+ else if(cfg_spim_cs_enb[1]) digital_io_oen[12] = 1'b0;
else if(cfg_port_b_dir_sel[1]) digital_io_oen[12] = 1'b0;
//Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13]
if(cfg_pwm_enb[4]) digital_io_oen[13] = 1'b0;
- else if(cfg_spim_enb[0]) digital_io_oen[13] = 1'b0;
+ else if(cfg_spim_cs_enb[0]) digital_io_oen[13] = 1'b0;
else if(cfg_port_b_dir_sel[2]) digital_io_oen[13] = 1'b0;
//Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
- if(cfg_spim_enb[0]) digital_io_oen[14] = 1'b1;
+ if(cfg_spim_enb) digital_io_oen[14] = 1'b1;
else if(cfg_pwm_enb[5]) digital_io_oen[14] = 1'b0;
else if(cfg_port_b_dir_sel[3]) digital_io_oen[14] = 1'b0;
//Pin-18 PB4/MISO digital_io[15]
- if(cfg_spim_enb[0]) digital_io_oen[15] = 1'b0;
+ if(cfg_spim_enb) digital_io_oen[15] = 1'b0;
else if(cfg_port_b_dir_sel[4]) digital_io_oen[15] = 1'b0;
//Pin-19 PB5/SCK digital_io[16]
- if(cfg_spim_enb[0]) digital_io_oen[16] = 1'b0;
+ if(cfg_spim_enb) digital_io_oen[16] = 1'b0;
else if(cfg_port_b_dir_sel[5]) digital_io_oen[16] = 1'b0;
//Pin-23 PC0/ADC0 digital_io[18]/analog_io[11]
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index d4e056c..8ad8bd2 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -716,7 +716,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h1306_2022) u_reg_23 (
+gen_32b_reg #(32'h0807_2022) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -729,9 +729,9 @@
);
//-----------------------------------------
-// Software Reg-3: Poject Revison 4.6 = 0004600
+// Software Reg-3: Poject Revison 4.7 = 0004700
// ----------------------------------------
-gen_32b_reg #(32'h0004_6000) u_reg_24 (
+gen_32b_reg #(32'h0004_7000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index bf93048..16297b2 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -206,9 +206,12 @@
//// core logic are timing optimized to 100mhz ////
//// 4.4 May 29 2022, Dinesh A ////
//// 1. Digital PLL integrated and clock debug signal add ////
-//// @digitial io [33] port
+//// @digitial io [33] port ////
//// 4.6 June 13 2022, Dinesh A ////
//// 1. icache and dcache bypass config addded ////
+//// 4.7 July 08 2022, Dinesh A ////
+//// Pinmux changes to support SPI CS port matching to ////
+//// arduino ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
