| commit | e91bdedbf75a1da30d41bcb8be7eb4ae1bf74b1f | [log] [tgz] |
|---|---|---|
| author | matt venn <matt@mattvenn.net> | Wed Aug 31 22:13:18 2022 +0200 |
| committer | Matt Venn <matt@mattvenn.net> | Thu Sep 01 12:44:37 2022 +0200 |
| tree | 3c68d3073c36a2fbb8dcb88258c1af6fbec357b9 | |
| parent | f80cf3d2ad3b5d777cc868292d77da07eb8e9c70 [diff] |
switch sel
diff --git a/verilog/dv/scan_controller_int/test_scan_controller.py b/verilog/dv/scan_controller_int/test_scan_controller.py index 1dcdf71..44b0906 100644 --- a/verilog/dv/scan_controller_int/test_scan_controller.py +++ b/verilog/dv/scan_controller_int/test_scan_controller.py
@@ -7,7 +7,7 @@ clock = Clock(dut.clk, 25, units="ns") # 40M cocotb.fork(clock.start()) - dut.driver_sel.value = 0b01 # internal + dut.driver_sel.value = 0b10 # internal dut.set_clk_div.value = 0 dut.inputs.value = 0 dut.active_sel.value = 0