switch sel

verilog/dv/scan_controller_int/test_scan_controller.py

diff --git a/verilog/dv/scan_controller_int/test_scan_controller.py b/verilog/dv/scan_controller_int/test_scan_controller.py
index 1dcdf71..44b0906 100644
--- a/verilog/dv/scan_controller_int/test_scan_controller.py
+++ b/verilog/dv/scan_controller_int/test_scan_controller.py
@@ -7,7 +7,7 @@
     clock = Clock(dut.clk, 25, units="ns") # 40M
     cocotb.fork(clock.start())
    
-    dut.driver_sel.value = 0b01 # internal
+    dut.driver_sel.value = 0b10 # internal
     dut.set_clk_div.value = 0
     dut.inputs.value = 0
     dut.active_sel.value = 0