wip
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 37d192d..237b352 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,4 +1,5 @@
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/rtl/cells.v
-v $(USER_PROJECT_VERILOG)/rtl/scan_controller/scan_controller.v
-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_339501025136214612.v
-v $(USER_PROJECT_VERILOG)/rtl/user_module_339501025136214612.v
