build index
diff --git a/INFO.md b/INFO.md new file mode 100644 index 0000000..6368f48 --- /dev/null +++ b/INFO.md
@@ -0,0 +1,69 @@ +# Instructions to build + +## Fetch all the projects + + ./configure.py --update-projects + +## Configure Caravel + + ./configure.py --update-caravel + +## Build the GDS + + make user_project_wrapper + +## Simulation + +There is a testbench that you can use to check the scan chain and controller is working. +The default of 498 projects takes a very long time to simulate, so I advise overriding the configuration first: + + # rebuild config with only 20 projects + ./configure.py --update-caravel --limit 20 + +Then run the test: + + cd verilog/dv/scan_controller + # you will also need to set your PDK_ROOT environment variable + make test_scan_controller + +You should get a VCD dump with a reset applied to input 1 for 2 clocks, and then 10 clocks applied to input 0. + + gtkwave test_scan_controller.gtkw + +You can set the design that is active by changing the test_scan_controller.py file, update the assignment to active_select. + +## Clocking + +Assuming: + +* 10MHz input clock, +* 8 ins & 8 outs +* 2 clock cycles to push one bit through the scan chain (scan clock is half input clock rate) +* 500 designs + +So the max refresh rate is 10MHz / (16 * 2 * 500) = 750Hz. + +## Clock divider + +The set_clk_div input will capture what is set on the input pins and use this as a divider for an internal slow clock that can be provided to the first input bit. + +The slow clock is only enabled if the set_clk_div is set, and the resulting clock is output on the slow_clk pin. + +As the refresh rate is 750Hz (see above) and the input clock is 10MHz, we add the input to 13, to create an adjustable divider between 14 and 22 bits. This results in an adjustable slow clock between ~600Hz & ~2Hz. + +## Dev notes + +* PDN hang issues https://github.com/The-OpenROAD-Project/OpenLane/issues/1173 +* Also discovered PDN hangs if extra lefs/defs are not deduplicated +* with PDN set so dense, tapeout job fails with density checks +* with unused PDN straps turned off, precheck fails +* copied the erased version (just power rings) and deleted the first digital power rings, copy pasted that over final gds +* precheck fails with missing power ports +* manually added missing power ports to gl verilog of user_project_wrapper +* precheck passes. Will try tapeout job +* tapeout job failed with DRC, was because outer power ring was too thin. I think due to configuration rather than being cutoff for precheck +* updated missing_power_rings with correct rings and repeated, this time tapeout passes +* Tim suggests doing this as a module/cell to make it easier to reproduce +* Maximo suggests editing pdn_cfg.tcl and using the -nets option with add_pdn_stripe to force only 1st voltage domain +* This worked, see the new openlane/user_project_wrapper/pdn_cfg.tcl config +
diff --git a/README.md b/README.md index 26065b8..285f27f 100644 --- a/README.md +++ b/README.md
@@ -2,75 +2,56 @@ # TinyTapeout -See https://tinytapeout.com for more information on the project and how to get involved. +* See https://tinytapeout.com for more information on the project and how to get involved. +* See [INFO](INFO.md) for how the project is built and technical project notes. + +# GDS layout of all projects  -# Instructions to build +# Project Index -## Fetch all the projects - - ./configure.py --update-projects - -## Configure Caravel - - ./configure.py --update-caravel - -## Build the GDS - - make user_project_wrapper - -## Simulation - -There is a testbench that you can use to check the scan chain and controller is working. -The default of 498 projects takes a very long time to simulate, so I advise overriding the configuration first: - - # rebuild config with only 20 projects - ./configure.py --update-caravel --limit 20 - -Then run the test: - - cd verilog/dv/scan_controller - # you will also need to set your PDK_ROOT environment variable - make test_scan_controller - -You should get a VCD dump with a reset applied to input 1 for 2 clocks, and then 10 clocks applied to input 0. - - gtkwave test_scan_controller.gtkw - -You can set the design that is active by changing the test_scan_controller.py file, update the assignment to active_select. - -## Clocking - -Assuming: - -* 10MHz input clock, -* 8 ins & 8 outs -* 2 clock cycles to push one bit through the scan chain (scan clock is half input clock rate) -* 500 designs - -So the max refresh rate is 10MHz / (16 * 2 * 500) = 750Hz. - -## Clock divider - -The set_clk_div input will capture what is set on the input pins and use this as a divider for an internal slow clock that can be provided to the first input bit. - -The slow clock is only enabled if the set_clk_div is set, and the resulting clock is output on the slow_clk pin. - -As the refresh rate is 750Hz (see above) and the input clock is 10MHz, we add the input to 13, to create an adjustable divider between 14 and 22 bits. This results in an adjustable slow clock between ~600Hz & ~2Hz. - -## Dev notes - -* PDN hang issues https://github.com/The-OpenROAD-Project/OpenLane/issues/1173 -* Also discovered PDN hangs if extra lefs/defs are not deduplicated -* with PDN set so dense, tapeout job fails with density checks -* with unused PDN straps turned off, precheck fails -* copied the erased version (just power rings) and deleted the first digital power rings, copy pasted that over final gds -* precheck fails with missing power ports -* manually added missing power ports to gl verilog of user_project_wrapper -* precheck passes. Will try tapeout job -* tapeout job failed with DRC, was because outer power ring was too thin. I think due to configuration rather than being cutoff for precheck -* updated missing_power_rings with correct rings and repeated, this time tapeout passes -* Tim suggests doing this as a module/cell to make it easier to reproduce -* Maximo suggests editing pdn_cfg.tcl and using the -nets option with add_pdn_stripe to force only 1st voltage domain -* This worked, see the new openlane/user_project_wrapper/pdn_cfg.tcl config +* https://wokwi.com/projects/339501025136214612 https://github.com/mattvenn/wokwi_filler +* https://wokwi.com/projects/334445762078310996 https://github.com/mattvenn/wokwi-verilog-gds-test +* https://wokwi.com/projects/335404063203000914 https://github.com/mattvenn/animation_tinytapeout_demo +* https://wokwi.com/projects/339439899388150354 https://github.com/mattvenn/wokwi_inverters +* https://wokwi.com/projects/339502597164499540 https://github.com/wokwi/tiny-tapeout-test-simple +* https://wokwi.com/projects/339732875283792466 https://github.com/omerk/tinytapeout-demo1 +* https://wokwi.com/projects/339865743461974612 https://github.com/mattvenn/tinytapeout-7seg-decoder +* https://wokwi.com/projects/339898704941023827 https://github.com/omerk/tinytapeout-verilog-test +* https://wokwi.com/projects/340218629792465491 https://github.com/gregdavill/tinytapeout_spin0 +* https://wokwi.com/projects/340318610245288530 https://github.com/mole99/wokwi-1bit-alu +* https://wokwi.com/projects/340285391309374034 https://github.com/ericsmi/tinytapeout_popcnt.git +* https://wokwi.com/projects/340661930553246290 https://github.com/krasin/wokwi-guess-my-number +* https://wokwi.com/projects/340805072482992722 https://github.com/mattvenn/tinytapeout-7seg-seconds-counter +* https://wokwi.com/projects/341136771628663380 https://github.com/johshoff/barrelshifter-wokwi-gds +* https://wokwi.com/projects/339800239192932947 https://github.com/pretentious7/tinytapeout +* https://wokwi.com/projects/341154161238213203 https://github.com/GuzTech/wokwi-ripple-carry-adder +* https://wokwi.com/projects/341159915403870803 https://github.com/kbeckmann/tinytapeout_kbeckmann1 +* https://wokwi.com/projects/341154068332282450 https://github.com/H-S-S-11/tinytapeout-verilog-test +* https://wokwi.com/projects/341160201697624660 https://github.com/skerr92/tinytapeout_frequency_div +* https://wokwi.com/projects/341163800289870419 https://github.com/argunda/tinytapeout_dualedgedetector +* https://wokwi.com/projects/341160271679586899 https://github.com/libokuohai/tinytapeout-2022-08 +* https://wokwi.com/projects/341161378978988626 https://github.com/jglim/tinytapeout_bcd-dec +* https://wokwi.com/projects/341152580068442706 https://github.com/jglim/tinytapeout_bcd-7seg +* https://wokwi.com/projects/341155178824598098 https://github.com/tkuester/wokwi-directghost +* https://wokwi.com/projects/341167691532337747 https://github.com/shahzaibk23/tinytapeout-barrel-shifter +* https://wokwi.com/projects/341178154799333971 https://github.com/tcptomato/tinytapeout +* https://wokwi.com/projects/341178481588044372 https://github.com/DaveyPocket/chaser +* https://wokwi.com/projects/341176884318437971 https://github.com/GuzTech/tinytapeout-4x4-multiplier +* https://wokwi.com/projects/341182944314917460 https://github.com/derhexenmeister/tinytapeout_nco +* https://wokwi.com/projects/341188777753969234 https://github.com/mbalestrini/tinytapeout_rgb_lut_test +* https://wokwi.com/projects/341194143598379604 https://github.com/derhexenmeister/tinytapeout_updwnbcd +* https://wokwi.com/projects/341205508016833108 https://github.com/bradysalz/pll_tiny_tapeout_demo +* https://wokwi.com/projects/341162950004834900 https://github.com/pramitpal/tinytapeout_pramit +* https://wokwi.com/projects/341202178192441940 https://github.com/gregdavill/tinytapeout-verilog-fifo +* https://wokwi.com/projects/341191836498395731 https://github.com/gregdavill/tinytapeout-wokwi-74x1G00 +* https://wokwi.com/projects/341192113929585235 https://github.com/gregdavill/tinytapeout-wokwi-74x1G02 +* https://wokwi.com/projects/341192621088047698 https://github.com/gregdavill/tinytapeout-wokwi-74xG198 +* https://wokwi.com/projects/340579111348994642 https://github.com/gregdavill/tinytapeout-verilog-7seg-clock +* https://wokwi.com/projects/341224613878956628 https://github.com/alanvgreen/tinytapeout4bitadder +* https://wokwi.com/projects/341235973870322258 https://github.com/benlaurie/twistedringcounter +* https://wokwi.com/projects/341235575572922964 https://github.com/sureshsugumar/tinytapeout_counter +* https://wokwi.com/projects/341164910646919762 https://github.com/daniestevez/tinytapeout-verilog +* https://wokwi.com/projects/341233739099013714 https://github.com/pkuligowski/tinytapeout_tmr +* https://wokwi.com/projects/341240110454407762 https://github.com/chiplet/tinytapeout-snake
diff --git a/README_init.md b/README_init.md new file mode 100644 index 0000000..b130a3d --- /dev/null +++ b/README_init.md
@@ -0,0 +1,13 @@ +[](https://github.com/mattvenn/tinytapeout-mpw7/actions/workflows/tinytapeout.yaml) + +# TinyTapeout + +* See https://tinytapeout.com for more information on the project and how to get involved. +* See [INFO](INFO.md) for how the project is built and technical project notes. + +# GDS layout of all projects + + + +# Project Index +
diff --git a/configure.py b/configure.py index 3d35a39..b56125b 100755 --- a/configure.py +++ b/configure.py
@@ -31,10 +31,13 @@ assert len(set(self.wokwi_ids)) == len(self.wokwi_ids) def update_cache(self): - from project_urls import project_urls self.wokwi_ids = [] - for url in [filler_project_url] + project_urls: - self.wokwi_ids.append(self.install_artifacts(url)) + for url in self.get_project_urls(): + wokwi_id = self.install_artifacts(url) + if wokwi_id in self.wokwi_ids: + logging.error("wokwi id already exists!") + exit(1) + self.wokwi_ids.append(wokwi_id) # cache it with open(Projects.projects_db, 'wb') as fh: @@ -83,6 +86,17 @@ except IndexError: return [] + def get_wokwi_ids(self): + return self.wokwi_ids + + @classmethod + def build_wokwi_url(Project, wokwi_id): + return "https://wokwi.com/projects/{}".format(wokwi_id) + + def get_project_urls(self): + from project_urls import project_urls + return [filler_project_url] + project_urls + # the latest artifact isn't necessarily the one related to the latest commit, as github # could have taken longer to process an older commit than a newer one. # so iterate through commits and return the artifact that matches @@ -346,6 +360,15 @@ for verilog in verilog_files: fh.write('-v $(USER_PROJECT_VERILOG)/rtl/{}\n'.format(verilog)) + def build_docs(self): + logging.info("building doc index") + with open("README_init.md") as fh: + readme = fh.read() + with open("README.md", 'w') as fh: + fh.write(readme) + for wokwi_id, project_url in zip(self.projects.get_wokwi_ids(), self.projects.get_project_urls()): + fh.write("* {} {}\n".format(Projects.build_wokwi_url(wokwi_id), project_url)) + if __name__ == '__main__': parser = argparse.ArgumentParser(description="TinyTapeout") @@ -380,3 +403,4 @@ if args.update_caravel: caravel.create_macro_config() caravel.instantiate() + caravel.build_docs()
diff --git a/openlane/user_project_wrapper/extra_lef_gds.tcl b/openlane/user_project_wrapper/extra_lef_gds.tcl index 9d28f57..fbf7190 100644 --- a/openlane/user_project_wrapper/extra_lef_gds.tcl +++ b/openlane/user_project_wrapper/extra_lef_gds.tcl
@@ -26,7 +26,24 @@ $script_dir/../../lef/scan_wrapper_341155178824598098.lef \ $script_dir/../../lef/scan_wrapper_341167691532337747.lef \ $script_dir/../../lef/scan_wrapper_341178154799333971.lef \ -$script_dir/../../lef/scan_wrapper_341178481588044372.lef" +$script_dir/../../lef/scan_wrapper_341178481588044372.lef \ +$script_dir/../../lef/scan_wrapper_341176884318437971.lef \ +$script_dir/../../lef/scan_wrapper_341182944314917460.lef \ +$script_dir/../../lef/scan_wrapper_341188777753969234.lef \ +$script_dir/../../lef/scan_wrapper_341194143598379604.lef \ +$script_dir/../../lef/scan_wrapper_341205508016833108.lef \ +$script_dir/../../lef/scan_wrapper_341162950004834900.lef \ +$script_dir/../../lef/scan_wrapper_341202178192441940.lef \ +$script_dir/../../lef/scan_wrapper_341191836498395731.lef \ +$script_dir/../../lef/scan_wrapper_341192113929585235.lef \ +$script_dir/../../lef/scan_wrapper_341192621088047698.lef \ +$script_dir/../../lef/scan_wrapper_340579111348994642.lef \ +$script_dir/../../lef/scan_wrapper_341224613878956628.lef \ +$script_dir/../../lef/scan_wrapper_341235973870322258.lef \ +$script_dir/../../lef/scan_wrapper_341235575572922964.lef \ +$script_dir/../../lef/scan_wrapper_341164910646919762.lef \ +$script_dir/../../lef/scan_wrapper_341233739099013714.lef \ +$script_dir/../../lef/scan_wrapper_341240110454407762.lef" set ::env(EXTRA_GDS_FILES) "\ $script_dir/../../gds/scan_controller.gds \ $script_dir/../../gds/scan_wrapper_339501025136214612.gds \ @@ -55,4 +72,21 @@ $script_dir/../../gds/scan_wrapper_341155178824598098.gds \ $script_dir/../../gds/scan_wrapper_341167691532337747.gds \ $script_dir/../../gds/scan_wrapper_341178154799333971.gds \ -$script_dir/../../gds/scan_wrapper_341178481588044372.gds" +$script_dir/../../gds/scan_wrapper_341178481588044372.gds \ +$script_dir/../../gds/scan_wrapper_341176884318437971.gds \ +$script_dir/../../gds/scan_wrapper_341182944314917460.gds \ +$script_dir/../../gds/scan_wrapper_341188777753969234.gds \ +$script_dir/../../gds/scan_wrapper_341194143598379604.gds \ +$script_dir/../../gds/scan_wrapper_341205508016833108.gds \ +$script_dir/../../gds/scan_wrapper_341162950004834900.gds \ +$script_dir/../../gds/scan_wrapper_341202178192441940.gds \ +$script_dir/../../gds/scan_wrapper_341191836498395731.gds \ +$script_dir/../../gds/scan_wrapper_341192113929585235.gds \ +$script_dir/../../gds/scan_wrapper_341192621088047698.gds \ +$script_dir/../../gds/scan_wrapper_340579111348994642.gds \ +$script_dir/../../gds/scan_wrapper_341224613878956628.gds \ +$script_dir/../../gds/scan_wrapper_341235973870322258.gds \ +$script_dir/../../gds/scan_wrapper_341235575572922964.gds \ +$script_dir/../../gds/scan_wrapper_341164910646919762.gds \ +$script_dir/../../gds/scan_wrapper_341233739099013714.gds \ +$script_dir/../../gds/scan_wrapper_341240110454407762.gds"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index ad6b3c2..579319c 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -26,23 +26,23 @@ scan_wrapper_341167691532337747_24 920 215 N scan_wrapper_341178154799333971_25 1060 215 N scan_wrapper_341178481588044372_26 1200 215 N -scan_wrapper_339501025136214612_27 1340 215 N -scan_wrapper_339501025136214612_28 1480 215 N -scan_wrapper_339501025136214612_29 1620 215 N -scan_wrapper_339501025136214612_30 1760 215 N -scan_wrapper_339501025136214612_31 1900 215 N -scan_wrapper_339501025136214612_32 2040 215 N -scan_wrapper_339501025136214612_33 2180 215 N -scan_wrapper_339501025136214612_34 2320 215 N -scan_wrapper_339501025136214612_35 2460 215 N -scan_wrapper_339501025136214612_36 2600 215 N -scan_wrapper_339501025136214612_37 2740 215 N -scan_wrapper_339501025136214612_38 80 350 N -scan_wrapper_339501025136214612_39 220 350 N -scan_wrapper_339501025136214612_40 360 350 N -scan_wrapper_339501025136214612_41 500 350 N -scan_wrapper_339501025136214612_42 640 350 N -scan_wrapper_339501025136214612_43 780 350 N +scan_wrapper_341176884318437971_27 1340 215 N +scan_wrapper_341182944314917460_28 1480 215 N +scan_wrapper_341188777753969234_29 1620 215 N +scan_wrapper_341194143598379604_30 1760 215 N +scan_wrapper_341205508016833108_31 1900 215 N +scan_wrapper_341162950004834900_32 2040 215 N +scan_wrapper_341202178192441940_33 2180 215 N +scan_wrapper_341191836498395731_34 2320 215 N +scan_wrapper_341192113929585235_35 2460 215 N +scan_wrapper_341192621088047698_36 2600 215 N +scan_wrapper_340579111348994642_37 2740 215 N +scan_wrapper_341224613878956628_38 80 350 N +scan_wrapper_341235973870322258_39 220 350 N +scan_wrapper_341235575572922964_40 360 350 N +scan_wrapper_341164910646919762_41 500 350 N +scan_wrapper_341233739099013714_42 640 350 N +scan_wrapper_341240110454407762_43 780 350 N scan_wrapper_339501025136214612_44 920 350 N scan_wrapper_339501025136214612_45 1060 350 N scan_wrapper_339501025136214612_46 1200 350 N
diff --git a/openlane/user_project_wrapper/macro_power.tcl b/openlane/user_project_wrapper/macro_power.tcl index beca8bb..65d3f8c 100644 --- a/openlane/user_project_wrapper/macro_power.tcl +++ b/openlane/user_project_wrapper/macro_power.tcl
@@ -27,23 +27,23 @@ scan_wrapper_341167691532337747_24 vccd1 vssd1 vccd1 vssd1, \ scan_wrapper_341178154799333971_25 vccd1 vssd1 vccd1 vssd1, \ scan_wrapper_341178481588044372_26 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_27 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_28 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_29 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_30 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_31 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_32 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_33 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_34 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_35 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_36 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_37 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_38 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_39 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_40 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_41 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_42 vccd1 vssd1 vccd1 vssd1, \ - scan_wrapper_339501025136214612_43 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341176884318437971_27 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341182944314917460_28 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341188777753969234_29 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341194143598379604_30 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341205508016833108_31 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341162950004834900_32 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341202178192441940_33 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341191836498395731_34 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341192113929585235_35 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341192621088047698_36 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_340579111348994642_37 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341224613878956628_38 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341235973870322258_39 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341235575572922964_40 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341164910646919762_41 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341233739099013714_42 vccd1 vssd1 vccd1 vssd1, \ + scan_wrapper_341240110454407762_43 vccd1 vssd1 vccd1 vssd1, \ scan_wrapper_339501025136214612_44 vccd1 vssd1 vccd1 vssd1, \ scan_wrapper_339501025136214612_45 vccd1 vssd1 vccd1 vssd1, \ scan_wrapper_339501025136214612_46 vccd1 vssd1 vccd1 vssd1, \
diff --git a/project_urls.py b/project_urls.py index c9cf08b..a50a96b 100644 --- a/project_urls.py +++ b/project_urls.py
@@ -38,11 +38,9 @@ 'https://github.com/gregdavill/tinytapeout-wokwi-74xG198', 'https://github.com/gregdavill/tinytapeout-verilog-7seg-clock', 'https://github.com/alanvgreen/tinytapeout4bitadder', - 'https://github.com/tcptomato/tinytapeout', 'https://github.com/benlaurie/twistedringcounter', 'https://github.com/sureshsugumar/tinytapeout_counter', 'https://github.com/daniestevez/tinytapeout-verilog', 'https://github.com/pkuligowski/tinytapeout_tmr', 'https://github.com/chiplet/tinytapeout-snake', - 'https://github.com/SMSajadi99', ]
diff --git a/projects.pkl b/projects.pkl index 86fe327..e3611f4 100644 --- a/projects.pkl +++ b/projects.pkl Binary files differ
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index 4018cc2..86598e5 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -55,3 +55,37 @@ -v $(USER_PROJECT_VERILOG)/rtl/user_module_341178154799333971.v -v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341178481588044372.v -v $(USER_PROJECT_VERILOG)/rtl/user_module_341178481588044372.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341176884318437971.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341176884318437971.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341182944314917460.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341182944314917460.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341188777753969234.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341188777753969234.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341194143598379604.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341194143598379604.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341205508016833108.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341205508016833108.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341162950004834900.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341162950004834900.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341202178192441940.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341202178192441940.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341191836498395731.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341191836498395731.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341192113929585235.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341192113929585235.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341192621088047698.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341192621088047698.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_340579111348994642.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_340579111348994642.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341224613878956628.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341224613878956628.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341235973870322258.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341235973870322258.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341235575572922964.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341235575572922964.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341164910646919762.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341164910646919762.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341233739099013714.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341233739099013714.v +-v $(USER_PROJECT_VERILOG)/rtl/scan_wrapper_341240110454407762.v +-v $(USER_PROJECT_VERILOG)/rtl/user_module_341240110454407762.v
diff --git a/verilog/rtl/user_project_includes.v b/verilog/rtl/user_project_includes.v index 515ba78..63e5179 100644 --- a/verilog/rtl/user_project_includes.v +++ b/verilog/rtl/user_project_includes.v
@@ -26,3 +26,20 @@ `include "scan_wrapper_341167691532337747.v" `include "scan_wrapper_341178154799333971.v" `include "scan_wrapper_341178481588044372.v" +`include "scan_wrapper_341176884318437971.v" +`include "scan_wrapper_341182944314917460.v" +`include "scan_wrapper_341188777753969234.v" +`include "scan_wrapper_341194143598379604.v" +`include "scan_wrapper_341205508016833108.v" +`include "scan_wrapper_341162950004834900.v" +`include "scan_wrapper_341202178192441940.v" +`include "scan_wrapper_341191836498395731.v" +`include "scan_wrapper_341192113929585235.v" +`include "scan_wrapper_341192621088047698.v" +`include "scan_wrapper_340579111348994642.v" +`include "scan_wrapper_341224613878956628.v" +`include "scan_wrapper_341235973870322258.v" +`include "scan_wrapper_341235575572922964.v" +`include "scan_wrapper_341164910646919762.v" +`include "scan_wrapper_341233739099013714.v" +`include "scan_wrapper_341240110454407762.v"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 53c0ba7..140d199 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -411,7 +411,7 @@ .latch_enable_out(latch[27]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_27 ( + scan_wrapper_341176884318437971 #(.NUM_IOS(8)) scan_wrapper_341176884318437971_27 ( .clk_in (clk [27]), .data_in (data [27]), .scan_select_in (scan [27]), @@ -422,7 +422,7 @@ .latch_enable_out(latch[28]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_28 ( + scan_wrapper_341182944314917460 #(.NUM_IOS(8)) scan_wrapper_341182944314917460_28 ( .clk_in (clk [28]), .data_in (data [28]), .scan_select_in (scan [28]), @@ -433,7 +433,7 @@ .latch_enable_out(latch[29]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_29 ( + scan_wrapper_341188777753969234 #(.NUM_IOS(8)) scan_wrapper_341188777753969234_29 ( .clk_in (clk [29]), .data_in (data [29]), .scan_select_in (scan [29]), @@ -444,7 +444,7 @@ .latch_enable_out(latch[30]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_30 ( + scan_wrapper_341194143598379604 #(.NUM_IOS(8)) scan_wrapper_341194143598379604_30 ( .clk_in (clk [30]), .data_in (data [30]), .scan_select_in (scan [30]), @@ -455,7 +455,7 @@ .latch_enable_out(latch[31]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_31 ( + scan_wrapper_341205508016833108 #(.NUM_IOS(8)) scan_wrapper_341205508016833108_31 ( .clk_in (clk [31]), .data_in (data [31]), .scan_select_in (scan [31]), @@ -466,7 +466,7 @@ .latch_enable_out(latch[32]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_32 ( + scan_wrapper_341162950004834900 #(.NUM_IOS(8)) scan_wrapper_341162950004834900_32 ( .clk_in (clk [32]), .data_in (data [32]), .scan_select_in (scan [32]), @@ -477,7 +477,7 @@ .latch_enable_out(latch[33]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_33 ( + scan_wrapper_341202178192441940 #(.NUM_IOS(8)) scan_wrapper_341202178192441940_33 ( .clk_in (clk [33]), .data_in (data [33]), .scan_select_in (scan [33]), @@ -488,7 +488,7 @@ .latch_enable_out(latch[34]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_34 ( + scan_wrapper_341191836498395731 #(.NUM_IOS(8)) scan_wrapper_341191836498395731_34 ( .clk_in (clk [34]), .data_in (data [34]), .scan_select_in (scan [34]), @@ -499,7 +499,7 @@ .latch_enable_out(latch[35]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_35 ( + scan_wrapper_341192113929585235 #(.NUM_IOS(8)) scan_wrapper_341192113929585235_35 ( .clk_in (clk [35]), .data_in (data [35]), .scan_select_in (scan [35]), @@ -510,7 +510,7 @@ .latch_enable_out(latch[36]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_36 ( + scan_wrapper_341192621088047698 #(.NUM_IOS(8)) scan_wrapper_341192621088047698_36 ( .clk_in (clk [36]), .data_in (data [36]), .scan_select_in (scan [36]), @@ -521,7 +521,7 @@ .latch_enable_out(latch[37]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_37 ( + scan_wrapper_340579111348994642 #(.NUM_IOS(8)) scan_wrapper_340579111348994642_37 ( .clk_in (clk [37]), .data_in (data [37]), .scan_select_in (scan [37]), @@ -532,7 +532,7 @@ .latch_enable_out(latch[38]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_38 ( + scan_wrapper_341224613878956628 #(.NUM_IOS(8)) scan_wrapper_341224613878956628_38 ( .clk_in (clk [38]), .data_in (data [38]), .scan_select_in (scan [38]), @@ -543,7 +543,7 @@ .latch_enable_out(latch[39]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_39 ( + scan_wrapper_341235973870322258 #(.NUM_IOS(8)) scan_wrapper_341235973870322258_39 ( .clk_in (clk [39]), .data_in (data [39]), .scan_select_in (scan [39]), @@ -554,7 +554,7 @@ .latch_enable_out(latch[40]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_40 ( + scan_wrapper_341235575572922964 #(.NUM_IOS(8)) scan_wrapper_341235575572922964_40 ( .clk_in (clk [40]), .data_in (data [40]), .scan_select_in (scan [40]), @@ -565,7 +565,7 @@ .latch_enable_out(latch[41]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_41 ( + scan_wrapper_341164910646919762 #(.NUM_IOS(8)) scan_wrapper_341164910646919762_41 ( .clk_in (clk [41]), .data_in (data [41]), .scan_select_in (scan [41]), @@ -576,7 +576,7 @@ .latch_enable_out(latch[42]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_42 ( + scan_wrapper_341233739099013714 #(.NUM_IOS(8)) scan_wrapper_341233739099013714_42 ( .clk_in (clk [42]), .data_in (data [42]), .scan_select_in (scan [42]), @@ -587,7 +587,7 @@ .latch_enable_out(latch[43]) ); - scan_wrapper_339501025136214612 #(.NUM_IOS(8)) scan_wrapper_339501025136214612_43 ( + scan_wrapper_341240110454407762 #(.NUM_IOS(8)) scan_wrapper_341240110454407762_43 ( .clk_in (clk [43]), .data_in (data [43]), .scan_select_in (scan [43]),