Update project_urls.py

add @omerk verilog submission
1 file changed
tree: 6f31d30a6f5fca64be25536335bf8f53f4ab27b3
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. configure.py
  14. LICENSE
  15. lint.sh
  16. Makefile
  17. missing_power_rings.gds
  18. powerring.lyp
  19. project_urls.py
  20. projects.pkl
  21. README.md
  22. requirements.txt
  23. tinytapeout.png
  24. upw_post.v
  25. upw_pre.v
README.md

tinytapeout

TinyTapeout

See https://tinytapeout.com for more information on the project and how to get involved.

tiny tapeout

Instructions to build

Fetch all the projects

./configure --update-projects

Configure Caravel

./configure --update-caravel

Build the GDS

make user_project_wrapper

Dev notes

  • PDN hang issues https://github.com/The-OpenROAD-Project/OpenLane/issues/1173
  • Also discovered PDN hangs if extra lefs/defs are not deduplicated
  • with PDN set so dense, tapeout job fails with density checks
  • with unused PDN straps turned off, precheck fails
  • copied the erased version (just power rings) and deleted the first digital power rings, copy pasted that over final gds
  • precheck fails with missing power ports
  • manually added missing power ports to gl verilog of user_project_wrapper
  • precheck passes. Will try tapeout job
  • tapeout job failed with DRC, was because outer power ring was too thin. I think due to configuration rather than being cutoff for precheck
  • updated missing_power_rings with correct rings and repeated, this time tapeout passes
  • Tim suggests doing this as a module/cell to make it easier to reproduce
  • Maximo suggests editing pdn_cfg.tcl and using the -nets option with add_pdn_stripe to force only 1st voltage domain
  • This worked, see the new openlane/user_project_wrapper/pdn_cfg.tcl config