| commit | 6f20cc3c7dbf4feb056c8d6682e27cd9ae9e78fe | [log] [tgz] |
|---|---|---|
| author | matt venn <matt@mattvenn.net> | Sun Aug 28 20:45:23 2022 +0200 |
| committer | matt venn <matt@mattvenn.net> | Sun Aug 28 20:45:23 2022 +0200 |
| tree | a1b810a6db5dd4503e223336caac66b1e7285d44 | |
| parent | 08495406d0b1eef05fefac71bb9f745032f6695a [diff] |
new designs
See https://tinytapeout.com for more information on the project and how to get involved.
./configure.py --update-projects
./configure.py --update-caravel
make user_project_wrapper
There is a testbench that you can use to check the scan chain and controller is working. The default of 498 projects takes a very long time to simulate, so I advise overriding the configuration first:
# rebuild config with only 20 projects ./configure.py --update-caravel --limit 20
Then run the test:
cd verilog/dv/scan_controller # you will also need to set your PDK_ROOT environment variable make test_scan_controller
You should get a VCD dump with a reset applied to input 1 for 2 clocks, and then 10 clocks applied to input 0.
gtkwave test_scan_controller.gtkw
You can set the design that is active by changing the test_scan_controller.py file, update the assignment to active_select.
Assuming:
So the max refresh rate is 10MHz / (16 * 2 * 500) = 750Hz.
The set_clk_div input will capture what is set on the input pins and use this as a divider for an internal slow clock that can be provided to the first input bit.
The slow clock is only enabled if the set_clk_div is set, and the resulting clock is output on the slow_clk pin.
As the refresh rate is 750Hz (see above) and the input clock is 10MHz, we add the input to 13, to create an adjustable divider between 14 and 22 bits. This results in an adjustable slow clock between ~600Hz & ~2Hz.
