fix ext scan test
diff --git a/verilog/dv/scan_controller_ext/scan_controller.c b/verilog/dv/scan_controller_ext/scan_controller.c index 6edea7e..797bcfd 100644 --- a/verilog/dv/scan_controller_ext/scan_controller.c +++ b/verilog/dv/scan_controller_ext/scan_controller.c
@@ -51,9 +51,12 @@ outputs (io_out[36:29]), ext_scan_clk = inputs[0]; ext_scan_data_in = inputs[1]; - ext_scan_data_out = outputs[0] + ext_scan_clk_in = outputs[0] + ext_scan_data_in = outputs[1] ext_scan_select = inputs[2]; ext_scan_latch_en = inputs[3]; + + assign outputs = driver_sel[1] ? aio_output_reg : {6'b0, ext_scan_data_in, ext_scan_clk_in}; */ reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_NOPULL; // clk @@ -61,7 +64,8 @@ reg_mprj_io_23 = GPIO_MODE_USER_STD_INPUT_NOPULL; // scan reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_NOPULL; // latch - reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT; // data out + reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT; // clk out + reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT; // data out // outputs for testbench control reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; // fw ready
diff --git a/verilog/dv/scan_controller_ext/scan_controller.hex b/verilog/dv/scan_controller_ext/scan_controller.hex index 4dd92e8..d81258e 100755 --- a/verilog/dv/scan_controller_ext/scan_controller.hex +++ b/verilog/dv/scan_controller_ext/scan_controller.hex
@@ -12,7 +12,7 @@ 03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 2D 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 06 C6 2E 63 0C B5 00 83 26 06 00 23 20 D5 00 13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 @@ -51,9 +51,11 @@ 13 07 20 40 23 A0 E7 00 B7 07 00 26 93 87 47 08 13 07 20 40 23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00 13 07 87 80 23 A0 E7 00 B7 07 00 26 -93 87 47 05 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 13 07 10 00 23 A0 E7 00 13 00 00 00 -B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE -B7 07 00 26 93 87 C7 00 83 A6 07 00 B7 07 00 26 -93 87 C7 00 37 17 00 00 33 E7 E6 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +93 87 C7 09 37 27 00 00 13 07 87 80 23 A0 E7 00 +B7 07 00 26 93 87 47 05 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 13 07 10 00 23 A0 E7 00 +13 00 00 00 B7 07 00 26 03 A7 07 00 93 07 10 00 +E3 0A F7 FE B7 07 00 26 93 87 C7 00 83 A6 07 00 +B7 07 00 26 93 87 C7 00 37 17 00 00 33 E7 E6 00 +23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00
diff --git a/verilog/dv/scan_controller_ext/scan_controller_ext.gtkw b/verilog/dv/scan_controller_ext/scan_controller_ext.gtkw index c4a3411..64a7b90 100644 --- a/verilog/dv/scan_controller_ext/scan_controller_ext.gtkw +++ b/verilog/dv/scan_controller_ext/scan_controller_ext.gtkw
@@ -1,22 +1,22 @@ [*] -[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI -[*] Sun Aug 28 03:59:31 2022 +[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI +[*] Fri Sep 2 12:46:11 2022 [*] [dumpfile] "/home/matt/work/asic-workshop/shuttle7/tinytapeout-mpw7/verilog/dv/scan_controller_ext/scan_controller_tb.vcd" -[dumpfile_mtime] "Sun Aug 28 03:59:25 2022" -[dumpfile_size] 357948 +[dumpfile_mtime] "Fri Sep 2 12:44:13 2022" +[dumpfile_size] 381427 [savefile] "/home/matt/work/asic-workshop/shuttle7/tinytapeout-mpw7/verilog/dv/scan_controller_ext/scan_controller_ext.gtkw" -[timestart] 365159000 -[size] 1848 1016 +[timestart] 384490000 +[size] 2235 1105 [pos] -1 -1 -*-18.000000 366175000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-21.299999 396812500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] scan_controller_tb. [treeopen] scan_controller_tb.uut. [treeopen] scan_controller_tb.uut.mprj. [sst_width] 423 -[signals_width] 261 +[signals_width] 475 [sst_expanded] 1 -[sst_vpaned_height] 254 +[sst_vpaned_height] 280 @28 scan_controller_tb.clk scan_controller_tb.driver_sel[1:0] @@ -25,22 +25,23 @@ @800200 -scan chain @28 -scan_controller_tb.uut.mprj.scan_controller.scan_clk +scan_controller_tb.uut.mprj.scan_controller.scan_clk_in +scan_controller_tb.uut.mprj.scan_controller.scan_clk_out scan_controller_tb.uut.mprj.scan_controller.scan_data_in scan_controller_tb.uut.mprj.scan_controller.scan_data_out scan_controller_tb.uut.mprj.scan_controller.scan_latch_en -scan_controller_tb.uut.mprj.scan_controller.scan_select @1000200 -scan chain @800200 -ext scan chain -@29 +@1000200 +-ext scan chain +@28 scan_controller_tb.ext_clk +scan_controller_tb.ext_clk_out scan_controller_tb.ext_data_in scan_controller_tb.ext_data_out scan_controller_tb.ext_latch scan_controller_tb.ext_scan -@1000200 --ext scan chain [pattern_trace] 1 [pattern_trace] 0
diff --git a/verilog/dv/scan_controller_ext/scan_controller_tb.v b/verilog/dv/scan_controller_ext/scan_controller_tb.v index 9b02c87..13f5270 100644 --- a/verilog/dv/scan_controller_ext/scan_controller_tb.v +++ b/verilog/dv/scan_controller_ext/scan_controller_tb.v
@@ -37,7 +37,8 @@ ///// convenience signals that match what the cocotb test modules are looking for // change to suit your project. Here's how we can make some nicer named signals for inputs & outputs wire fw_ready = mprj_io[12]; - wire ext_data_out = mprj_io[29]; + wire ext_clk_out = mprj_io[29]; + wire ext_data_out = mprj_io[30]; wire [1:0] driver_sel; wire ext_clk, ext_latch, ext_scan, ext_data_in;
diff --git a/verilog/dv/scan_controller_ext/test_scan_controller.py b/verilog/dv/scan_controller_ext/test_scan_controller.py index 40af416..ef469be 100644 --- a/verilog/dv/scan_controller_ext/test_scan_controller.py +++ b/verilog/dv/scan_controller_ext/test_scan_controller.py
@@ -58,14 +58,13 @@ dut.ext_scan.value = 0 # drive the data out - for i in range(8): + for i in range(8*20): dut.ext_clk.value = 1 await ClockCycles(dut.clk, 1) dut.ext_clk.value = 0 await ClockCycles(dut.clk, 1) - print(dut.ext_data_out.value) - if i < 4: + if i in [152, 153, 154, 155]: assert(dut.ext_data_out.value == 1) - else: + elif i in [156, 157, 158, 159]: assert(dut.ext_data_out.value == 0)