ready signal and reset for clock div
diff --git a/verilog/rtl/scan_controller/scan_controller.v b/verilog/rtl/scan_controller/scan_controller.v
index e1d75a8..df298c9 100644
--- a/verilog/rtl/scan_controller/scan_controller.v
+++ b/verilog/rtl/scan_controller/scan_controller.v
@@ -427,8 +427,10 @@
assign active = set_sync[2];
// Latch divider
- always @(posedge clk)
- if (set_now)
+ always @(posedge clk or posedge reset)
+ if (reset)
+ compare <= 0;
+ else if (set_now)
compare <= divider;
// Compare
