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@@ -1,14 +1,71 @@
-# Instructions to build
+# Technical info
-## Fetch all the projects
+## Clocking
+
+Assuming:
+
+* 100MHz input clock
+* 8 ins & 8 outs
+* 2 clock cycles to push one bit through the scan chain (scan clock is half input clock rate)
+* 500 designs
+* scan controller can do a read/write cycle in one refresh
+
+So the max refresh rate is 100MHz / (8 * 2 * 500) = 12500Hz.
+
+## Clock divider
+
+The set_clk_div input will capture what is set on the input pins and use this as a divider for an internal slow clock that can be provided to the first input bit.
+
+The slow clock is only enabled if the set_clk_div is set, and the resulting clock is connected to input0 and also output on the slow_clk pin.
+
+The slow clock is synced with the scan rate. A divider of 0 mean it toggles the input0 every scan. Divider of 1 toggles it every 2 cycles.
+So the resultant slow clock frequency is scan_rate / (2 * (N+1)).
+
+## Pinout
+
+ PIN NAME DESCRIPTION
+ 20:12 active_select 9 bit input to set which design is active
+ 28:21 inputs 8 inputs
+ 36:29 outputs 8 outputs
+ 37 ready goes high for one cycle everytime the scanchain is refreshed
+ 10 slow_clk slow clock from internal clock divider
+ 11 set_clk_div enable clock divider
+ 9:8 driver_sel which scan chain driver: 00 = external, 01 = logic analyzer, 1x = internal
+
+ 21 ext_scan_clk_out for external driver, clk input
+ 22 ext_scan_data_out data input
+ 23 ext_scan_select scan select
+ 24 ext_scan_latch_en latch
+ 29 ext_scan_clk_in clk output from end of chain
+ 30 ext_scan_data_in data output from end of chain
+
+## Scan controller configuration
+
+The scan controller allows a configurable delay on the latch and scan select pulses. TODO.
+
+## Scan chain structure
+
+
+
+
+
+[read wavedrom diagram](https://wavedrom.com/editor.html?%7Bsignal%3A%20%5B%0A%20%20%7Bname%3A%20%27clk%27%2C%20wave%3A%20%27p.....%27%7D%2C%0A%20%20%7Bname%3A%20%27scan%20en%27%2C%20wave%3A%20%27010...%27%7D%2C%0A%20%20%7Bname%3A%20%27latch%27%2C%20wave%3A%20%270.....%27%7D%2C%0A%20%20%7Bname%3A%20%27data%20o%27%2C%20wave%3A%20%27x.....%27%7D%2C%0A%20%20%7Bname%3A%20%27data%20i%27%2C%20wave%3A%20%270.1010%27%7D%2C%0A%5D%2C%0Ahead%3A%7B%0A%20%20%20text%3A%27Capture%20outputs%201010%27%2C%0A%20%20%20tick%3A0%2C%0A%20%20%20every%3A1%0A%20%7D%7D%0A)
+
+
+
+[load wavedrom diagram](https://wavedrom.com/editor.html?%7Bsignal%3A%20%5B%0A%20%20%7Bname%3A%20%27clk%27%2C%20wave%3A%20%27p...l.%27%7D%2C%0A%20%20%7Bname%3A%20%27scan%20en%27%2C%20wave%3A%20%270.....%27%7D%2C%0A%20%20%7Bname%3A%20%27latch%27%2C%20wave%3A%20%270...10%27%7D%2C%0A%20%20%7Bname%3A%20%27data%20o%27%2C%20wave%3A%20%2701010.%27%7D%2C%0A%20%20%7Bname%3A%20%27data%20i%27%2C%20wave%3A%20%27x.....%27%7D%2C%0A%0A%5D%2C%0Ahead%3A%7B%0A%20%20%20text%3A%27Load%20inputs%20with%200101%27%2C%0A%20%20%20tick%3A0%2C%0A%20%20%20every%3A1%0A%20%7D%7D%0A)
+
+## Instructions to build
+
+### Fetch all the projects
./configure.py --update-projects
-## Configure Caravel
+### Configure Caravel
./configure.py --update-caravel
-## Build the GDS
+### Build the GDS
make user_project_wrapper
@@ -53,55 +110,6 @@
cd verilog/dv/scan_controller_la
make coco_test
-## Clocking
-
-Assuming:
-
-* 100MHz input clock
-* 8 ins & 8 outs
-* 2 clock cycles to push one bit through the scan chain (scan clock is half input clock rate)
-* 500 designs
-
-So the max refresh rate is 100MHz / (16 * 2 * 500) = 6250Hz.
-
-## Clock divider
-
-The set_clk_div input will capture what is set on the input pins and use this as a divider for an internal slow clock that can be provided to the first input bit.
-
-The slow clock is only enabled if the set_clk_div is set, and the resulting clock is output on the slow_clk pin.
-
-As the refresh rate is 6250Hz (see above) and the input clock is 100MHz, we add the input to 13, to create an adjustable divider between 14 and 22 bits. This results in an adjustable slow clock between ~4800Hz & ~16Hz.
-
-## Pinout
-
- PIN NAME DESCRIPTION
- 20:12 active_select 9 bit input to set which design is active
- 28:21 inputs 8 inputs
- 36:29 outputs 8 outputs
- 37 ready goes high for one cycle everytime the scanchain is refreshed
- 10 slow_clk slow clock from internal clock divider
- 11 set_clk_div enable clock divider
- 9:8 driver_sel which scan chain driver: 00 = external, 01 = logic analyzer, 1x = internal
-
- 21 ext_scan_clk_out for external driver, clk input
- 22 ext_scan_data_out data input
- 23 ext_scan_select scan select
- 24 ext_scan_latch_en latch
- 29 ext_scan_clk_in clk output from end of chain
- 30 ext_scan_data_in data output from end of chain
-
-## Scan chain structure
-
-
-
-
-
-[read wavedrom diagram](https://wavedrom.com/editor.html?%7Bsignal%3A%20%5B%0A%20%20%7Bname%3A%20%27clk%27%2C%20wave%3A%20%27p.....%27%7D%2C%0A%20%20%7Bname%3A%20%27scan%20en%27%2C%20wave%3A%20%27010...%27%7D%2C%0A%20%20%7Bname%3A%20%27latch%27%2C%20wave%3A%20%270.....%27%7D%2C%0A%20%20%7Bname%3A%20%27data%20o%27%2C%20wave%3A%20%27x.....%27%7D%2C%0A%20%20%7Bname%3A%20%27data%20i%27%2C%20wave%3A%20%270.1010%27%7D%2C%0A%5D%2C%0Ahead%3A%7B%0A%20%20%20text%3A%27Capture%20outputs%201010%27%2C%0A%20%20%20tick%3A0%2C%0A%20%20%20every%3A1%0A%20%7D%7D%0A)
-
-
-
-[load wavedrom diagram](https://wavedrom.com/editor.html?%7Bsignal%3A%20%5B%0A%20%20%7Bname%3A%20%27clk%27%2C%20wave%3A%20%27p...l.%27%7D%2C%0A%20%20%7Bname%3A%20%27scan%20en%27%2C%20wave%3A%20%270.....%27%7D%2C%0A%20%20%7Bname%3A%20%27latch%27%2C%20wave%3A%20%270...10%27%7D%2C%0A%20%20%7Bname%3A%20%27data%20o%27%2C%20wave%3A%20%2701010.%27%7D%2C%0A%20%20%7Bname%3A%20%27data%20i%27%2C%20wave%3A%20%27x.....%27%7D%2C%0A%0A%5D%2C%0Ahead%3A%7B%0A%20%20%20text%3A%27Load%20inputs%20with%200101%27%2C%0A%20%20%20tick%3A0%2C%0A%20%20%20every%3A1%0A%20%7D%7D%0A)
-
## Dev notes
* PDN hang issues https://github.com/The-OpenROAD-Project/OpenLane/issues/1173
@@ -117,4 +125,3 @@
* Tim suggests doing this as a module/cell to make it easier to reproduce
* Maximo suggests editing pdn_cfg.tcl and using the -nets option with add_pdn_stripe to force only 1st voltage domain
* This worked, see the new openlane/user_project_wrapper/pdn_cfg.tcl config
-
