| OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO ODB-0222] Reading LEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef |
| [INFO ODB-0223] Created 13 technology layers |
| [INFO ODB-0224] Created 60 technology vias |
| [INFO ODB-0225] Created 229 library cells |
| [INFO ODB-0226] Finished LEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef |
| Reading netlist... |
| [INFO]: Setting output delay to: 6.0 |
| [INFO]: Setting input delay to: 6.0 |
| [INFO]: Setting load to: 0.07291 |
| [INFO]: Setting clock uncertainty to: 0.25 |
| [INFO]: Setting clock transition to: 0.15 |
| [INFO]: Setting timing derate to: 0.5 % |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.19 0.68 0.68 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.01 fsm_plant_opt.state_water_synth_2 (net) |
| 0.19 0.00 0.68 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 0.46 0.33 1.01 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 4 0.02 _002_ (net) |
| 0.46 0.00 1.01 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.14 0.09 1.11 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 fsm_plant_opt.tmp3555 (net) |
| 0.14 0.00 1.11 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.11 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.09 0.34 library hold time |
| 0.34 data required time |
| ----------------------------------------------------------------------------- |
| 0.34 data required time |
| -1.11 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.77 slack (MET) |
| |
| |
| Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.19 0.68 0.68 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.01 fsm_plant_opt.state_temperature_synth_1 (net) |
| 0.19 0.00 0.68 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1) |
| 0.22 0.17 0.85 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1) |
| 1 0.00 _033_ (net) |
| 0.22 0.00 0.85 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.16 0.12 0.97 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.00 _041_ (net) |
| 0.16 0.00 0.97 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.16 0.13 1.10 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 1 0.00 _045_ (net) |
| 0.16 0.00 1.10 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.11 0.09 1.19 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 fsm_plant_opt.tmp2410 (net) |
| 0.11 0.00 1.19 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.19 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.09 0.34 library hold time |
| 0.34 data required time |
| ----------------------------------------------------------------------------- |
| 0.34 data required time |
| -1.19 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.85 slack (MET) |
| |
| |
| Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.24 0.76 0.76 ^ _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.01 fsm_plant_opt.state_temperature_synth_2 (net) |
| 0.24 0.00 0.76 ^ _070_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.29 0.23 0.99 v _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 4 0.02 _012_ (net) |
| 0.29 0.00 0.99 v _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand4_1) |
| 0.19 0.22 1.21 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand4_1) |
| 1 0.00 _017_ (net) |
| 0.19 0.00 1.21 ^ _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 0.16 0.28 1.48 ^ _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 1 0.00 _018_ (net) |
| 0.16 0.00 1.48 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.10 0.09 1.57 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 fsm_plant_opt.tmp2409 (net) |
| 0.10 0.00 1.57 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.57 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.10 0.35 library hold time |
| 0.35 data required time |
| ----------------------------------------------------------------------------- |
| 0.35 data required time |
| -1.57 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.23 slack (MET) |
| |
| |
| Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.19 0.68 0.68 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.01 fsm_plant_opt.state_water_synth_2 (net) |
| 0.19 0.00 0.68 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 0.46 0.33 1.01 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 4 0.02 _002_ (net) |
| 0.46 0.00 1.01 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.19 0.19 1.21 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 2 0.01 _048_ (net) |
| 0.19 0.00 1.21 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 0.10 0.24 1.45 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 1 0.00 _057_ (net) |
| 0.10 0.00 1.45 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.13 0.24 1.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2 0.01 fsm_plant_opt.tmp3554 (net) |
| 0.13 0.00 1.69 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.69 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.09 0.34 library hold time |
| 0.34 data required time |
| ----------------------------------------------------------------------------- |
| 0.34 data required time |
| -1.69 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.35 slack (MET) |
| |
| |
| Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.19 0.68 0.68 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.01 fsm_plant_opt.state_water_synth_2 (net) |
| 0.19 0.00 0.68 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 0.46 0.33 1.01 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 4 0.02 _002_ (net) |
| 0.46 0.00 1.01 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 0.31 0.23 1.25 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1) |
| 3 0.01 _008_ (net) |
| 0.31 0.00 1.25 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 0.11 0.33 1.58 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 1 0.00 _054_ (net) |
| 0.11 0.00 1.58 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.09 0.21 1.80 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 1 0.00 fsm_plant_opt.tmp2411 (net) |
| 0.09 0.00 1.80 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.80 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.10 0.35 library hold time |
| 0.35 data required time |
| ----------------------------------------------------------------------------- |
| 0.35 data required time |
| -1.80 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.45 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: wbs_we_i (input port clocked by wb_clk_i) |
| Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 6.00 6.00 ^ input external delay |
| 0.33 0.17 6.17 ^ wbs_we_i (in) |
| 4 0.02 wbs_we_i (net) |
| 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 2 0.01 _003_ (net) |
| 0.19 0.00 6.34 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1) |
| 0.76 0.42 6.76 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1) |
| 2 0.01 _014_ (net) |
| 0.76 0.00 6.76 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.33 0.40 7.16 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _015_ (net) |
| 0.33 0.00 7.16 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 0.27 0.56 7.72 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 2 0.01 _036_ (net) |
| 0.27 0.00 7.72 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.24 0.21 7.93 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _052_ (net) |
| 0.24 0.00 7.93 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.27 0.21 8.15 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.00 _053_ (net) |
| 0.27 0.00 8.15 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 0.17 0.49 8.64 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 1 0.00 _054_ (net) |
| 0.17 0.00 8.64 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.10 0.21 8.85 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 1 0.00 fsm_plant_opt.tmp2411 (net) |
| 0.10 0.00 8.85 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 8.85 data arrival time |
| |
| 0.15 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock network delay (ideal) |
| -0.25 29.75 clock uncertainty |
| 0.00 29.75 clock reconvergence pessimism |
| 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.20 29.55 library setup time |
| 29.55 data required time |
| ----------------------------------------------------------------------------- |
| 29.55 data required time |
| -8.85 data arrival time |
| ----------------------------------------------------------------------------- |
| 20.70 slack (MET) |
| |
| |
| Startpoint: wbs_we_i (input port clocked by wb_clk_i) |
| Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 6.00 6.00 ^ input external delay |
| 0.33 0.17 6.17 ^ wbs_we_i (in) |
| 4 0.02 wbs_we_i (net) |
| 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 2 0.01 _003_ (net) |
| 0.19 0.00 6.34 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.21 0.36 6.71 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _004_ (net) |
| 0.21 0.00 6.71 v _078_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1) |
| 1.02 0.57 7.28 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1) |
| 3 0.01 _020_ (net) |
| 1.02 0.00 7.28 ^ _079_/A3 (gf180mcu_fd_sc_mcu7t5v0__and3_1) |
| 0.19 0.44 7.71 ^ _079_/Z (gf180mcu_fd_sc_mcu7t5v0__and3_1) |
| 1 0.00 _021_ (net) |
| 0.19 0.00 7.71 ^ _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.19 0.13 7.84 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.00 _026_ (net) |
| 0.19 0.00 7.84 v _089_/I1 (gf180mcu_fd_sc_mcu7t5v0__mux2_2) |
| 0.13 0.39 8.23 v _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2) |
| 1 0.00 _030_ (net) |
| 0.13 0.00 8.23 v _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.27 0.19 8.42 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 fsm_plant_opt.tmp2409 (net) |
| 0.27 0.00 8.42 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 8.42 data arrival time |
| |
| 0.15 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock network delay (ideal) |
| -0.25 29.75 clock uncertainty |
| 0.00 29.75 clock reconvergence pessimism |
| 29.75 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.23 29.52 library setup time |
| 29.52 data required time |
| ----------------------------------------------------------------------------- |
| 29.52 data required time |
| -8.42 data arrival time |
| ----------------------------------------------------------------------------- |
| 21.11 slack (MET) |
| |
| |
| Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_oeb[0] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.27 0.86 0.86 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.01 fsm_plant_opt.state_temperature_synth_1 (net) |
| 0.27 0.00 0.86 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.31 0.26 1.11 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _011_ (net) |
| 0.31 0.00 1.11 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.60 0.44 1.55 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 4 0.02 _012_ (net) |
| 0.60 0.00 1.55 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.27 0.19 1.74 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 2 0.01 _028_ (net) |
| 0.27 0.00 1.74 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 1.40 0.90 2.63 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 1 0.07 io_oeb[0] (net) |
| 1.40 0.00 2.63 ^ io_oeb[0] (out) |
| 2.63 data arrival time |
| |
| 0.15 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock network delay (ideal) |
| -0.25 29.75 clock uncertainty |
| 0.00 29.75 clock reconvergence pessimism |
| -6.00 23.75 output external delay |
| 23.75 data required time |
| ----------------------------------------------------------------------------- |
| 23.75 data required time |
| -2.63 data arrival time |
| ----------------------------------------------------------------------------- |
| 21.12 slack (MET) |
| |
| |
| Startpoint: wbs_we_i (input port clocked by wb_clk_i) |
| Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 6.00 6.00 ^ input external delay |
| 0.33 0.17 6.17 ^ wbs_we_i (in) |
| 4 0.02 wbs_we_i (net) |
| 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 2 0.01 _003_ (net) |
| 0.19 0.00 6.34 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.21 0.36 6.71 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _004_ (net) |
| 0.21 0.00 6.71 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1) |
| 0.29 0.54 7.25 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1) |
| 4 0.02 _005_ (net) |
| 0.29 0.00 7.25 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.43 0.32 7.57 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.01 _027_ (net) |
| 0.43 0.00 7.57 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.17 0.12 7.69 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 1 0.00 _056_ (net) |
| 0.17 0.00 7.69 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 0.10 0.28 7.96 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1) |
| 1 0.00 _057_ (net) |
| 0.10 0.00 7.96 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.13 0.27 8.23 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2 0.01 fsm_plant_opt.tmp3554 (net) |
| 0.13 0.00 8.23 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.20 0.16 8.39 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.00 fsm_plant_opt.tmp3553 (net) |
| 0.20 0.00 8.39 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 8.39 data arrival time |
| |
| 0.15 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock network delay (ideal) |
| -0.25 29.75 clock uncertainty |
| 0.00 29.75 clock reconvergence pessimism |
| 29.75 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.22 29.53 library setup time |
| 29.53 data required time |
| ----------------------------------------------------------------------------- |
| 29.53 data required time |
| -8.39 data arrival time |
| ----------------------------------------------------------------------------- |
| 21.14 slack (MET) |
| |
| |
| Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_oeb[1] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.27 0.86 0.86 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.01 fsm_plant_opt.state_temperature_synth_1 (net) |
| 0.27 0.00 0.86 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.31 0.26 1.11 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 4 0.02 _011_ (net) |
| 0.31 0.00 1.11 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.60 0.44 1.55 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 4 0.02 _012_ (net) |
| 0.60 0.00 1.55 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 0.27 0.19 1.74 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1) |
| 2 0.01 _028_ (net) |
| 0.27 0.00 1.74 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__inv_1) |
| 1.33 0.87 2.61 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__inv_1) |
| 2 0.08 io_oeb[1] (net) |
| 1.33 0.00 2.61 ^ io_oeb[1] (out) |
| 2.61 data arrival time |
| |
| 0.15 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock network delay (ideal) |
| -0.25 29.75 clock uncertainty |
| 0.00 29.75 clock reconvergence pessimism |
| -6.00 23.75 output external delay |
| 23.75 data required time |
| ----------------------------------------------------------------------------- |
| 23.75 data required time |
| -2.61 data arrival time |
| ----------------------------------------------------------------------------- |
| 21.14 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: wbs_we_i (input port clocked by wb_clk_i) |
| Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 6.00 6.00 ^ input external delay |
| 0.33 0.17 6.17 ^ wbs_we_i (in) |
| 4 0.02 wbs_we_i (net) |
| 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1) |
| 2 0.01 _003_ (net) |
| 0.19 0.00 6.34 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1) |
| 0.76 0.42 6.76 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1) |
| 2 0.01 _014_ (net) |
| 0.76 0.00 6.76 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.33 0.40 7.16 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.02 _015_ (net) |
| 0.33 0.00 7.16 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 0.27 0.56 7.72 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 2 0.01 _036_ (net) |
| 0.27 0.00 7.72 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.24 0.21 7.93 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _052_ (net) |
| 0.24 0.00 7.93 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.27 0.21 8.15 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.00 _053_ (net) |
| 0.27 0.00 8.15 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 0.17 0.49 8.64 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1) |
| 1 0.00 _054_ (net) |
| 0.17 0.00 8.64 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.10 0.21 8.85 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 1 0.00 fsm_plant_opt.tmp2411 (net) |
| 0.10 0.00 8.85 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 8.85 data arrival time |
| |
| 0.15 30.00 30.00 clock wb_clk_i (rise edge) |
| 0.00 30.00 clock network delay (ideal) |
| -0.25 29.75 clock uncertainty |
| 0.00 29.75 clock reconvergence pessimism |
| 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| -0.20 29.55 library setup time |
| 29.55 data required time |
| ----------------------------------------------------------------------------- |
| 29.55 data required time |
| -8.85 data arrival time |
| ----------------------------------------------------------------------------- |
| 20.70 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| |
| =========================================================================== |
| max slew violation count 0 |
| max fanout violation count 0 |
| max cap violation count 0 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 20.70 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 0.77 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _125_/CLK ^ |
| 0.05 |
| _125_/CLK ^ |
| 0.05 0.00 0.00 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 1.09e-04 4.05e-06 1.22e-09 1.13e-04 69.1% |
| Combinational 2.28e-05 2.75e-05 1.09e-08 5.04e-05 30.9% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 1.31e-04 3.16e-05 1.21e-08 1.63e-04 100.0% |
| 80.6% 19.4% 0.0% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 2070 u^2 100% utilization. |
| area_report_end |
| [WARNING] Did not save OpenROAD database! |
| Writing SDF to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/synthesis/plant_example.sdf... |
