| Netgen 1.5.242 compiled on Wed Nov 16 22:54:20 UTC 2022 |
| Warning: netgen command 'format' use fully-qualified name '::netgen::format' |
| Warning: netgen command 'global' use fully-qualified name '::netgen::global' |
| Generating JSON file result |
| Reading netlist file /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/signoff/user_project_wrapper.spice |
| Reading netlist file /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff/19-user_project_wrapper.pnl.v |
| Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match. |
| Creating placeholder cell definition for module plant_example. |
| Reading setup file /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl |
| Comparison output logged to file /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/22-user_project_wrapper.lef.lvs.log |
| Logging to file "/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/22-user_project_wrapper.lef.lvs.log" enabled |
| |
| Contents of circuit 1: Circuit: 'plant_example' |
| Circuit plant_example contains 0 device instances. |
| Circuit contains 0 nets, and 123 disconnected pins. |
| Contents of circuit 2: Circuit: 'plant_example' |
| Circuit plant_example contains 0 device instances. |
| Circuit contains 0 nets. |
| |
| Circuit plant_example contains no devices. |
| |
| Contents of circuit 1: Circuit: 'user_project_wrapper' |
| Circuit user_project_wrapper contains 1 device instances. |
| Class: plant_example instances: 1 |
| Circuit contains 123 nets, and 295 disconnected pins. |
| Contents of circuit 2: Circuit: 'user_project_wrapper' |
| Circuit user_project_wrapper contains 1 device instances. |
| Class: plant_example instances: 1 |
| Circuit contains 123 nets, and 295 disconnected pins. |
| |
| Circuit 1 contains 1 devices, Circuit 2 contains 1 devices. |
| Circuit 1 contains 123 nets, Circuit 2 contains 123 nets. |
| |
| |
| Final result: |
| Circuits match uniquely. |
| . |
| Logging to file "/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/22-user_project_wrapper.lef.lvs.log" disabled |
| LVS Done. |
