sdc/OQPSK_PS_RCOSINE2.sdc

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# Created by write_sdc
# Mon Dec  5 00:08:44 2022
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current_design OQPSK_PS_RCOSINE2
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# Timing Constraints
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create_clock -name CLK -period 100.0000 [get_ports {CLK}]
set_clock_transition 0.1500 [get_clocks {CLK}]
set_clock_uncertainty 0.2500 CLK
set_propagated_clock [get_clocks {CLK}]
set_input_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {BitIn}]
set_input_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {EN}]
set_input_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {RST}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[0]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[10]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[11]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[12]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[1]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[2]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[3]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[4]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[5]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[6]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[7]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[8]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {I[9]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[0]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[10]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[11]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[12]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[1]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[2]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[3]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[4]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[5]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[6]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[7]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[8]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {Q[9]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addI[0]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addI[1]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addI[2]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addI[3]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addI[4]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addI[5]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addQ[0]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addQ[1]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addQ[2]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addQ[3]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addQ[4]}]
set_output_delay 20.0000 -clock [get_clocks {CLK}] -add_delay [get_ports {addQ[5]}]
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# Environment
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set_load -pin_load 0.0729 [get_ports {I[12]}]
set_load -pin_load 0.0729 [get_ports {I[11]}]
set_load -pin_load 0.0729 [get_ports {I[10]}]
set_load -pin_load 0.0729 [get_ports {I[9]}]
set_load -pin_load 0.0729 [get_ports {I[8]}]
set_load -pin_load 0.0729 [get_ports {I[7]}]
set_load -pin_load 0.0729 [get_ports {I[6]}]
set_load -pin_load 0.0729 [get_ports {I[5]}]
set_load -pin_load 0.0729 [get_ports {I[4]}]
set_load -pin_load 0.0729 [get_ports {I[3]}]
set_load -pin_load 0.0729 [get_ports {I[2]}]
set_load -pin_load 0.0729 [get_ports {I[1]}]
set_load -pin_load 0.0729 [get_ports {I[0]}]
set_load -pin_load 0.0729 [get_ports {Q[12]}]
set_load -pin_load 0.0729 [get_ports {Q[11]}]
set_load -pin_load 0.0729 [get_ports {Q[10]}]
set_load -pin_load 0.0729 [get_ports {Q[9]}]
set_load -pin_load 0.0729 [get_ports {Q[8]}]
set_load -pin_load 0.0729 [get_ports {Q[7]}]
set_load -pin_load 0.0729 [get_ports {Q[6]}]
set_load -pin_load 0.0729 [get_ports {Q[5]}]
set_load -pin_load 0.0729 [get_ports {Q[4]}]
set_load -pin_load 0.0729 [get_ports {Q[3]}]
set_load -pin_load 0.0729 [get_ports {Q[2]}]
set_load -pin_load 0.0729 [get_ports {Q[1]}]
set_load -pin_load 0.0729 [get_ports {Q[0]}]
set_load -pin_load 0.0729 [get_ports {addI[5]}]
set_load -pin_load 0.0729 [get_ports {addI[4]}]
set_load -pin_load 0.0729 [get_ports {addI[3]}]
set_load -pin_load 0.0729 [get_ports {addI[2]}]
set_load -pin_load 0.0729 [get_ports {addI[1]}]
set_load -pin_load 0.0729 [get_ports {addI[0]}]
set_load -pin_load 0.0729 [get_ports {addQ[5]}]
set_load -pin_load 0.0729 [get_ports {addQ[4]}]
set_load -pin_load 0.0729 [get_ports {addQ[3]}]
set_load -pin_load 0.0729 [get_ports {addQ[2]}]
set_load -pin_load 0.0729 [get_ports {addQ[1]}]
set_load -pin_load 0.0729 [get_ports {addQ[0]}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {BitIn}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_4 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {CLK}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {EN}]
set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {RST}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
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# Design Rules
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set_max_fanout 4.0000 [current_design]