tapeout/outputs/drc/drc_run_2022_12_13_03_29_36.log - third_party/shuttle/gf180mcu/mpw-000/slot-036 - Git at Google

 12-Dec-2022 19:29:36 | INFO    | Your Klayout version is: KLayout 0.28
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['comp.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['contact.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['dnwell.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['drc_bjt.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['dualgate.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['dummy_exclude.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['efuse.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['esd.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['geom.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['hres.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['lres.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['lvpwell.drc']
 12-Dec-2022 19:29:40 | INFO    | ## Generating template with for the following rule tables: ['lvs_bjt.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['main.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['mcell.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['metal1.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['metal2.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['metal3.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['metal4.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['metal5.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['metaltop.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['mim.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['nat.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['nplus.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['otp_mk.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['poly2.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['pplus.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['pres.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['sab.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['sram.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['tail.drc']
 12-Dec-2022 19:29:41 | INFO    | ## Generating template with for the following rule tables: ['via1.drc']
 12-Dec-2022 19:29:42 | INFO    | ## Generating template with for the following rule tables: ['via2.drc']
 12-Dec-2022 19:29:42 | INFO    | ## Generating template with for the following rule tables: ['via3.drc']
 12-Dec-2022 19:29:42 | INFO    | ## Generating template with for the following rule tables: ['via4.drc']
 12-Dec-2022 19:29:42 | INFO    | ## Generating template with for the following rule tables: ['via5.drc']
 12-Dec-2022 19:29:42 | INFO    | ## Generating template with for the following rule tables: ['ymtp_mk.drc']
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design comp on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design contact on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design dnwell on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design drc_bjt on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design dualgate on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design dummy_exclude on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design efuse on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design esd on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design geom on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design hres on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design lres on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design lvpwell on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design lvs_bjt on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design main on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design mcell on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metal1 on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metal2 on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metal3 on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metal4 on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metal5 on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metaltop on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design mim on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design nat on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design nplus on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design otp_mk on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design poly2 on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design pplus on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design pres on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design sab on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design sram on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design tail on cell caravel_18005f3a:
 12-Dec-2022 19:29:42 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design via1 on cell caravel_18005f3a:
 12-Dec-2022 19:32:04 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design via2 on cell caravel_18005f3a:
 12-Dec-2022 19:32:06 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design via3 on cell caravel_18005f3a:
 12-Dec-2022 19:32:06 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design via4 on cell caravel_18005f3a:
 12-Dec-2022 19:32:06 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design via5 on cell caravel_18005f3a:
 12-Dec-2022 19:32:11 | INFO    | Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design ymtp_mk on cell caravel_18005f3a:
 12-Dec-2022 20:30:07 | INFO    | Klayout DRC run is clean. GDS has no DRC violations.
	12-Dec-2022 19:29:36 \| INFO \| Your Klayout version is: KLayout 0.28
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['comp.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['contact.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['dnwell.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['drc_bjt.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['dualgate.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['dummy_exclude.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['efuse.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['esd.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['geom.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['hres.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['lres.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['lvpwell.drc']
	12-Dec-2022 19:29:40 \| INFO \| ## Generating template with for the following rule tables: ['lvs_bjt.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['main.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['mcell.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['metal1.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['metal2.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['metal3.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['metal4.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['metal5.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['metaltop.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['mim.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['nat.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['nplus.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['otp_mk.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['poly2.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['pplus.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['pres.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['sab.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['sram.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['tail.drc']
	12-Dec-2022 19:29:41 \| INFO \| ## Generating template with for the following rule tables: ['via1.drc']
	12-Dec-2022 19:29:42 \| INFO \| ## Generating template with for the following rule tables: ['via2.drc']
	12-Dec-2022 19:29:42 \| INFO \| ## Generating template with for the following rule tables: ['via3.drc']
	12-Dec-2022 19:29:42 \| INFO \| ## Generating template with for the following rule tables: ['via4.drc']
	12-Dec-2022 19:29:42 \| INFO \| ## Generating template with for the following rule tables: ['via5.drc']
	12-Dec-2022 19:29:42 \| INFO \| ## Generating template with for the following rule tables: ['ymtp_mk.drc']
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design comp on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design contact on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design dnwell on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design drc_bjt on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design dualgate on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design dummy_exclude on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design efuse on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design esd on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design geom on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design hres on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design lres on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design lvpwell on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design lvs_bjt on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design main on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design mcell on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metal1 on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metal2 on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metal3 on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metal4 on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metal5 on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design metaltop on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design mim on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design nat on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design nplus on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design otp_mk on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design poly2 on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design pplus on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design pres on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design sab on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design sram on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design tail on cell caravel_18005f3a:
	12-Dec-2022 19:29:42 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design via1 on cell caravel_18005f3a:
	12-Dec-2022 19:32:04 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design via2 on cell caravel_18005f3a:
	12-Dec-2022 19:32:06 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design via3 on cell caravel_18005f3a:
	12-Dec-2022 19:32:06 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design via4 on cell caravel_18005f3a:
	12-Dec-2022 19:32:06 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design via5 on cell caravel_18005f3a:
	12-Dec-2022 19:32:11 \| INFO \| Running Global Foundries 180nm MCU /mnt/shuttles/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/oas/caravel_18005f3a.oas checks on design ymtp_mk on cell caravel_18005f3a:
	12-Dec-2022 20:30:07 \| INFO \| Klayout DRC run is clean. GDS has no DRC violations.