tapeout/outputs/drc/caravel_18005f3a_dualgate.lyrdb

<?xml version="1.0" encoding="utf-8"?>
<report-database>
 <description>DRC Run Report at</description>
 <original-file/>
 <generator>drc: script='/mnt/shuttles/shuttle/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/drc/dualgate.drc'</generator>
 <top-cell>caravel_18005f3a</top-cell>
 <tags>
 </tags>
 <categories>
  <category>
   <name>DV.1</name>
   <description>DV.1 : Min. Dualgate enclose DNWELL. : 0.5µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.2</name>
   <description>DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.3</name>
   <description>DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.5</name>
   <description>DV.5 : Min. Dualgate width. : 0.7µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.6</name>
   <description>DV.6 : Min. Dualgate enclose COMP (except substrate tap). : 0.24µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.7</name>
   <description>DV.7 : COMP (except substrate tap) can not be partially overlapped by Dualgate.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.8</name>
   <description>DV.8 : Min Dualgate enclose Poly2. : 0.4µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DV.9</name>
   <description>DV.9 : 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.</description>
   <categories>
   </categories>
  </category>
 </categories>
 <cells>
  <cell>
   <name>caravel_18005f3a</name>
   <variant/>
   <references>
   </references>
  </cell>
 </cells>
 <items>
 </items>
</report-database>