forgot 'wire' in verilog

verilog/rtl/top.v

diff --git a/verilog/rtl/top.v b/verilog/rtl/top.v
index 65715ba..4c533ab 100644
--- a/verilog/rtl/top.v
+++ b/verilog/rtl/top.v
@@ -19,6 +19,7 @@
   assign io_out[7] = xnor_y;
   //assign io_out[6:0] = ... ; // notused
 
+  wire xnor_y;
 
   // connect modules