| --- |
| # TinyTapeout project information |
| project: |
| wokwi_id: 0 # If using wokwi, set this to your project's ID |
| source_files: # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here |
| - verilog/rtl/regfile_top.v |
| - verilog/rtl/xnor1.v |
| - verilog/rtl/regfile16x4.v |
| top_module: "rolfmobile99_top" # put the name of your top module here, make it unique by prepending your github username |
| |
| # As everyone will have access to all designs, try to make it easy for someone new to your design to know what |
| # it does and how to operate it. |
| # |
| # Here is an example: https://github.com/mattvenn/tinytapeout_m_segments/blob/main/info.yaml |
| # |
| # This info will be automatically collected and used to make a datasheet for the chip. |
| documentation: |
| author: "Rolf Widenfelt" # Your name |
| discord: "" # Your discord handle - make sure to include the # part as well |
| title: "16 x 4-bit dual port register file + XNOR" # Project title |
| description: "A dual port register file + XNOR test gate" # Short description of what your project does |
| how_it_works: "" # Longer description of how the project works |
| how_to_test: "" # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed |
| external_hw: "" # Describe any external hardware needed |
| language: "verilog" # other examples include Verilog, Amaranth, VHDL, etc |
| doc_link: "" # URL to longer form documentation, eg the README.md in your repository |
| clock_hz: 0 # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0. |
| picture: "" # relative path to a picture in your repository |
| inputs: # a description of what the inputs do |
| - clock |
| - reset |
| - xnor_a # inputs for XNOR gate |
| - xnor_b |
| - en1 # inputs for regfile |
| - en2 |
| - wrEn |
| - rdAddr1_3 |
| - rdAddr1_2 |
| - rdAddr1_1 |
| - rdAddr1_0 |
| - rdAddr2_3 |
| - rdAddr2_2 |
| - rdAddr2_1 |
| - rdAddr2_0 |
| - dataIn_3 |
| - dataIn_2 |
| - dataIn_1 |
| - dataIn_0 |
| outputs: |
| - xnor_y # output for XNOR gate |
| - dataBusA_3 # outputs for regfile |
| - dataBusA_2 |
| - dataBusA_1 |
| - dataBusA_0 |
| - dataBusB_3 |
| - dataBusB_2 |
| - dataBusB_1 |
| - dataBusB_0 |