commit c5e44076b6422bac941145765bbdc9a990ca732d
author Dagois Maximilien <mdagois@google.com> Mon Dec 05 14:20:22 2022 +0900
committer Dagois Maximilien <mdagois@google.com> Mon Dec 05 14:20:22 2022 +0900
tree 9c395dd9e13d6dd457bcb599b2ce1f29abc12f46
parent 99c4d9ba3ae102845a72a4ada47776a746461608

LFSR cleanup

verilog/rtl/user_module.x

diff --git a/verilog/rtl/user_module.x b/verilog/rtl/user_module.x
index 835b915..155d4ad 100644
--- a/verilog/rtl/user_module.x
+++ b/verilog/rtl/user_module.x
@@ -1,11 +1,4 @@
 fn lfsr8(n: u8) -> u8 {
-    //let bit3 = (n >> 3) as u1;
-    //let bit4 = (n >> 4) as u1;
-    //let bit5 = (n >> 5) as u1;
-    //let bit7 = (n >> 7) as u1;
-    //let new_bit = (bit3 ^ bit4 ^ bit5 ^ bit7) as u8;
-    //(n << 1) | new_bit
-
     n[0+:u7] ++ (n[3+:u1] ^ n[4+:u1] ^ n[5+:u1] ^ n[7+:u1])
 }