verilog/rtl: add top

verilog/rtl/top.v

diff --git a/verilog/rtl/top.v b/verilog/rtl/top.v
new file mode 100644
index 0000000..4082415
--- /dev/null
+++ b/verilog/rtl/top.v
@@ -0,0 +1,6 @@
+module top(
+  input wire [7:0] io_in,
+  output wire [7:0] io_out
+);
+  user_module user_module0(io_in, io_out);
+endmodule