| commit | a8b5ee38f89354b27d20ca69b2b236b1b5b01575 | [log] [tgz] |
|---|---|---|
| author | Johan Euphrosine <proppy@google.com> | Sat Dec 03 02:47:17 2022 +0900 |
| committer | GitHub <noreply@github.com> | Sat Dec 03 02:47:17 2022 +0900 |
| tree | 14707315e01f4843c0132148d3100c0d3db2394b | |
| parent | fb7683ea02ccc775ae801b5038d96e97d2f99df8 [diff] |
verilog/rtl: add top
diff --git a/verilog/rtl/top.v b/verilog/rtl/top.v new file mode 100644 index 0000000..4082415 --- /dev/null +++ b/verilog/rtl/top.v
@@ -0,0 +1,6 @@ +module top( + input wire [7:0] io_in, + output wire [7:0] io_out +); + user_module user_module0(io_in, io_out); +endmodule