verilog/rtl/user_module_opt.ir

package user_module

file_number 0 "fake_file.x"

top fn __user_module__user_module(io_in: bits[8]) -> bits[8] {
  bit_slice.28: bits[1] = bit_slice(io_in, start=3, width=1, id=28, pos=[(0,1,18)])
  bit_slice.29: bits[1] = bit_slice(io_in, start=4, width=1, id=29, pos=[(0,1,29)])
  bit_slice.30: bits[1] = bit_slice(io_in, start=5, width=1, id=30, pos=[(0,1,40)])
  bit_slice.31: bits[1] = bit_slice(io_in, start=7, width=1, id=31, pos=[(0,1,51)])
  bit_slice.32: bits[7] = bit_slice(io_in, start=0, width=7, id=32, pos=[(0,1,5)])
  xor.33: bits[1] = xor(bit_slice.28, bit_slice.29, bit_slice.30, bit_slice.31, id=33, pos=[(0,1,48)])
  ret concat.34: bits[8] = concat(bit_slice.32, xor.33, id=34, pos=[(0,1,13)])
}