| commit | 872758b02bb0570d3a593e8c84c75f7cd82a6ef9 | [log] [tgz] |
|---|---|---|
| author | AbdulMoizSheikh1 <119680153+AbdulMoizSheikh1@users.noreply.github.com> | Sun Dec 04 23:30:07 2022 +0500 |
| committer | GitHub <noreply@github.com> | Sun Dec 04 23:30:07 2022 +0500 |
| tree | 3a845a9e5eb96d3388f0ccb0dc6560d27acfdfe6 | |
| parent | b475d062bb87fc72da4268bbbc1a020ebf062f72 [diff] |
Create REadme.md
diff --git a/Verilog_Code/REadme.md b/Verilog_Code/REadme.md new file mode 100644 index 0000000..3cd0758 --- /dev/null +++ b/Verilog_Code/REadme.md
@@ -0,0 +1,2 @@ +The verilog code for the project. +Due credits to the respective authors have been given