commit f6a949c73bcab4e1d74c63ffd4b8a0db0f0dc2ad
author DAR <dar@browndeertechnology.com> Tue Dec 06 01:59:16 2022 -0500
committer DAR <dar@browndeertechnology.com> Tue Dec 06 01:59:16 2022 -0500
tree 30ce9cda727b45b533be41cf958f248126323397
parent 5178731f05a41739f1c700de60f2ca76f78e7716

syntax error

verilog/rtl/pyramiden_core.v

diff --git a/verilog/rtl/pyramiden_core.v b/verilog/rtl/pyramiden_core.v
index 052249d..5d82136 100644
--- a/verilog/rtl/pyramiden_core.v
+++ b/verilog/rtl/pyramiden_core.v
@@ -285,7 +285,7 @@
    assign dmem_dout	= des_dout[36:21];
 
    assign des_din[13:0]		= imem_addr;
-	ssign des_din[15:14]		= 2'd0;
+	assign des_din[15:14]		= 2'd0;
    assign des_din[31:16]	= dmem_addr;
    assign des_din[47:32]	= dmem_din;
    assign des_din[63:48]	= 16'd0;