fixed readme
diff --git a/README.md b/README.md index 96b8997..23fe686 100644 --- a/README.md +++ b/README.md
@@ -1,5 +1,5 @@ -# Pyramiden Core - 16-bit RV16U Microcore processor +# Pyramiden Core - 16-bit RV16U Microcore Processor This is a CPU core based on the RISC-V ISA reduced in size to support 16-bit data and memory operations with 21-bit instructions and 16 registers. @@ -10,12 +10,13 @@ for the chip employs a simple serdes to accomodate the limited I/O pins available. This reduces the effective processor clock by 8x in order to synchronize the instruction and data memory interfaces. This was a compromise -that evolved as a solution to interface to the larger I/O interface of the -processor core. +that evolved as a solution to interface the chip to the larger I/O interface +of the processor core. ## I/O Pins - inputs: +Inputs: + - clock - reset - enable @@ -36,26 +37,27 @@ - serdes input bit 11 - serdes input bit 12 - outputs: - - halt - - dmem_we - - dmem_en - - serdes output bit 0 - - serdes output bit 1 - - serdes output bit 2 - - serdes output bit 3 - - serdes output bit 4 - - serdes output bit 5 - - serdes output bit 6 - - serdes output bit 7 - - serdes output bit 8 - - serdes output bit 9 - - serdes output bit 10 - - serdes output bit 11 - - serdes output bit 12 - - serdes output bit 13 - - serdes output bit 14 - - serdes output bit 15 +Outputs: + +- halt +- dmem_we +- dmem_en +- serdes output bit 0 +- serdes output bit 1 +- serdes output bit 2 +- serdes output bit 3 +- serdes output bit 4 +- serdes output bit 5 +- serdes output bit 6 +- serdes output bit 7 +- serdes output bit 8 +- serdes output bit 9 +- serdes output bit 10 +- serdes output bit 11 +- serdes output bit 12 +- serdes output bit 13 +- serdes output bit 14 +- serdes output bit 15 # Tiny User Project @@ -78,36 +80,3 @@ 1. [Submit](https://platform.efabless.com/projects/create?project_definition=Open+MPW&shuttle=GFMPW-0) your project github repository to the next [Open MPW shuttle](https://platform.efabless.com/shuttles/GFMPW-0). - - - - ---- -# TinyTapeout project information -project: - wokwi_id: 0 # If using wokwi, set this to your project's ID - source_files: # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. Source files must be in ./src - - verilog/rtl/pyramiden_core.v - - verilog/rtl/des.v - - verilog/rtl/registers.v - top_module: "pyramiden_core" # put the name of your top module here, make it unique by prepending your github username - -# As everyone will have access to all designs, try to make it easy for someone new to your design to know what -# it does and how to operate it. -# -# Here is an example: https://github.com/mattvenn/tinytapeout_m_segments/blob/main/info.yaml -# -# This info will be automatically collected and used to make a datasheet for the chip. -documentation: - author: "David Richie" # Your name - discord: "" # Your discord handle - title: "RV16U - 16-bit RISC-V Microcore Processor" # Project title - description: "16-bit processor based on RISC-V ISA" # Short description of what your project does - how_it_works: "Executes reduced RISC-V based ISA" # Longer description of how the project works - how_to_test: "Requires interfacing to external memory" # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed - external_hw: "" # Describe any external hardware needed - language: "verilog" # other examples include Verilog, Amaranth, VHDL, etc - doc_link: "" # URL to longer form documentation, eg the README.md in your repository - clock_hz: 1000 # Clock frequency in Hz (if required) - picture: "" # relative path to a picture in your repository -