fixed io_oeb

verilog/rtl/tiny_user_project.v

diff --git a/verilog/rtl/tiny_user_project.v b/verilog/rtl/tiny_user_project.v
index eca8d6e..42ee2f6 100644
--- a/verilog/rtl/tiny_user_project.v
+++ b/verilog/rtl/tiny_user_project.v
@@ -45,8 +45,8 @@
     io_out[37:19]
 );
 // all output enabled
-assign io_oeb[37:19] = 8'b0;
+assign io_oeb[37:19] = 'd0;
 
 endmodule	// tiny_user_project
 
-`default_nettype wire
\ No newline at end of file
+`default_nettype wire

verilog/rtl/tiny_user_project.v.jinja2

diff --git a/verilog/rtl/tiny_user_project.v.jinja2 b/verilog/rtl/tiny_user_project.v.jinja2
index c5035fd..cc4708b 100644
--- a/verilog/rtl/tiny_user_project.v.jinja2
+++ b/verilog/rtl/tiny_user_project.v.jinja2
@@ -45,8 +45,8 @@
     io_out[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}]
 );
 // all output enabled
-assign io_oeb[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}] = 8'b0;
+assign io_oeb[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}] = 'd0;
 
 endmodule	// tiny_user_project
 
-`default_nettype wire
\ No newline at end of file
+`default_nettype wire