attempt to use more IO pins

diff --git a/configure.py b/configure.py
index 9730dd4..28a8a9c 100755
--- a/configure.py
+++ b/configure.py

@@ -11,7 +11,8 @@
 import re
 import jinja2
 
-GPIO_VALID_RANGE = [8, 36]
+#GPIO_VALID_RANGE = [8, 36]
+GPIO_VALID_RANGE = [0, 38]
 
 def load_yaml(yaml_file):
     with open(yaml_file, "r") as stream:

diff --git a/openlane/tiny_user_project/config.json b/openlane/tiny_user_project/config.json
index 2482e3e..eca2e9a 100644
--- a/openlane/tiny_user_project/config.json
+++ b/openlane/tiny_user_project/config.json

@@ -2,8 +2,9 @@
     "DESIGN_NAME": "tiny_user_project",
     "DESIGN_IS_CORE": 0,
     "VERILOG_FILES": [
-        "dir::../../verilog/rtl/user_module.v",
-        "dir::../../verilog/rtl/cells.v",
+        "dir::../../verilog/rtl/pyramiden_core.v",
+        "dir::../../verilog/rtl/des.v",
+        "dir::../../verilog/rtl/registers.v",
         "dir::../../verilog/rtl/defines.v",
         "dir::../../verilog/rtl/tiny_user_project.v"
     ],
@@ -13,7 +14,7 @@
     "FP_SIZING": "absolute",
     "DIE_AREA": "0 0 600 680",
     "PL_BASIC_PLACEMENT": 0,
-    "PL_TARGET_DENSITY": 0.70,
+    "PL_TARGET_DENSITY": 0.7,
     "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
     "VDD_NETS": [
         "vdd"
@@ -40,4 +41,4 @@
         "RT_MAX_LAYER": "Metal4",
         "SYNTH_MAX_FANOUT": 4
     }
-}
+}
\ No newline at end of file

diff --git a/verilog/rtl/tiny_user_project.v b/verilog/rtl/tiny_user_project.v
index 81063e0..c2bb34f 100644
--- a/verilog/rtl/tiny_user_project.v
+++ b/verilog/rtl/tiny_user_project.v

@@ -40,12 +40,12 @@
 );
 
 // pass input and output pins defined in user_defines.v
-browndeer_rv8u mod (
-    io_in[16:8],
-    io_out[24:17]
+pyramiden_core mod (
+    io_in[19:0],
+    io_out[37:20]
 );
 // all output enabled
-assign io_oeb[24:17] = 8'b0;
+assign io_oeb[37:20] = 8'b0;
 
 endmodule	// tiny_user_project
 

diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v
index 27fd5af..9ddfbf0 100644
--- a/verilog/rtl/user_defines.v
+++ b/verilog/rtl/user_defines.v

@@ -53,9 +53,9 @@
 // tiny_user_project i/o
 // generated by configure.py
 
-`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
 `define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
 `define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
 `define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
@@ -65,26 +65,26 @@
 `define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
 `define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
 `define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
-`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_OUTPUT
-`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_OUTPUT
-`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
 `define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_USER_STD_OUTPUT
 `define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_USER_STD_OUTPUT
 `define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_USER_STD_OUTPUT
 `define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_USER_STD_OUTPUT
 `define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_USER_STD_OUTPUT
-`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
-`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_OUTPUT
 
-`endif // __USER_DEFINES_H
\ No newline at end of file
+`endif // __USER_DEFINES_H