another try at locating the verilog files

info.yaml

diff --git a/info.yaml b/info.yaml
index 4b2738b..99c6ae6 100644
--- a/info.yaml
+++ b/info.yaml
@@ -3,9 +3,9 @@
 project:
   wokwi_id:    0        # If using wokwi, set this to your project's ID
   source_files:        # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. Source files must be in ./src
-    - browndeer_rv8u.v
-    - des.v
-    - registers.v
+    - verilog/rtl/browndeer_rv8u.v
+    - verilog/rtl/des.v
+    - verilog/rtl/registers.v
   top_module:  "browndeer_rv8u"      # put the name of your top module here, make it unique by prepending your github username
 
 # As everyone will have access to all designs, try to make it easy for someone new to your design to know what

verilog/rtl/browndeer_rv8u.v

diff --git a/browndeer_rv8u.v b/verilog/rtl/browndeer_rv8u.v
similarity index 100%
rename from browndeer_rv8u.v
rename to verilog/rtl/browndeer_rv8u.v

verilog/rtl/des.v

diff --git a/des.v b/verilog/rtl/des.v
similarity index 100%
rename from des.v
rename to verilog/rtl/des.v

verilog/rtl/registers.v

diff --git a/registers.v b/verilog/rtl/registers.v
similarity index 100%
rename from registers.v
rename to verilog/rtl/registers.v