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// Copyright 2022 Google LLC.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
// tiny_user_project top module instance
// generated by configure.py
module tiny_user_project(
`ifdef USE_POWER_PINS
inout vdd, // User area 5.0V supply
inout vss, // User area ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [63:0] la_data_in,
output [63:0] la_data_out,
input [63:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
// Independent clock (on independent integer divider)
input user_clock2,
// User maskable interrupt signals
output [2:0] user_irq
);
// pass input and output pins defined in user_defines.v
{{ module_name }} mod (
io_in[{{ io_in_range[1] - 1 }}:{{ io_in_range[0] }}],
io_out[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}]
);
// all output enabled
assign io_oeb[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}] = 'd0;
endmodule // tiny_user_project
`default_nettype wire