trying to fix the routing issue

openlane/tiny_user_project/config.json

diff --git a/openlane/tiny_user_project/config.json b/openlane/tiny_user_project/config.json
index eca2e9a..d31594c 100644
--- a/openlane/tiny_user_project/config.json
+++ b/openlane/tiny_user_project/config.json
@@ -14,6 +14,8 @@
     "FP_SIZING": "absolute",
     "DIE_AREA": "0 0 600 680",
     "PL_BASIC_PLACEMENT": 0,
+    "PL_RANDOM_GLB_PLACEMENT": 0,
+    "PL_ROUTABILITY_DRIVEN": 1,
     "PL_TARGET_DENSITY": 0.7,
     "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
     "VDD_NETS": [

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index d4e4d14..64d9a6e 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -69,7 +69,8 @@
 
 # The following is because there are no std cells in the example wrapper project.
 set ::env(SYNTH_ELABORATE_ONLY) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+#set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+set ::env(PL_ROUTABILITY_DRIVEN) 1
 
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0