fixed tiny_user_project interface

verilog/rtl/tiny_user_project.v

diff --git a/verilog/rtl/tiny_user_project.v b/verilog/rtl/tiny_user_project.v
index 42ee2f6..1bf0a88 100644
--- a/verilog/rtl/tiny_user_project.v
+++ b/verilog/rtl/tiny_user_project.v
@@ -42,10 +42,10 @@
 // pass input and output pins defined in user_defines.v
 pyramiden_core mod (
     io_in[18:0],
-    io_out[37:19]
+    io_out[18:0]
 );
 // all output enabled
-assign io_oeb[37:19] = 'd0;
+assign io_oeb[18:0] = 19'd0;
 
 endmodule	// tiny_user_project
 

verilog/rtl/tiny_user_project.v.jinja2

diff --git a/verilog/rtl/tiny_user_project.v.jinja2 b/verilog/rtl/tiny_user_project.v.jinja2
index cc4708b..ab6098e 100644
--- a/verilog/rtl/tiny_user_project.v.jinja2
+++ b/verilog/rtl/tiny_user_project.v.jinja2
@@ -41,11 +41,11 @@
 
 // pass input and output pins defined in user_defines.v
 {{ module_name }} mod (
-    io_in[{{ io_in_range[1] - 1 }}:{{ io_in_range[0] }}],
-    io_out[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}]
+    io_in[18:0],
+    io_out[18:0]
 );
 // all output enabled
-assign io_oeb[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}] = 'd0;
+assign io_oeb[18:0] = 19'd0;
 
 endmodule	// tiny_user_project
 

verilog/rtl/user_defines.v

diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v
index b5188d2..0ee1921 100644
--- a/verilog/rtl/user_defines.v
+++ b/verilog/rtl/user_defines.v
@@ -87,4 +87,4 @@
 `define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_OUTPUT
 `define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_OUTPUT
 
-`endif // __USER_DEFINES_H
\ No newline at end of file
+`endif // __USER_DEFINES_H