| /root/ophelia_efpga/openlane/config.tcl |
| /root/ophelia_efpga/openlane/user_project_wrapper.sdc |
| /root/ophelia_efpga/openlane/efuse_ctrl/config.tcl |
| /root/ophelia_efpga/openlane/fpga_struct_block/config.tcl |
| /root/ophelia_efpga/openlane/fpga_struct_block/fpga_struct_block.sdc |
| /root/ophelia_efpga/sdf/efuse_ctrl.sdf |
| /root/ophelia_efpga/sdf/fpga_struct_block.sdf |
| /root/ophelia_efpga/sdf/user_project_wrapper.sdf |
| /root/ophelia_efpga/verilog/includes/includes.gl+sdf.caravel_user_project |
| /root/ophelia_efpga/verilog/includes/includes.gl.caravel_user_project |
| /root/ophelia_efpga/verilog/includes/includes.rtl.caravel_user_project |
| /root/ophelia_efpga/verilog/rtl/ariel_fpga_top_fromvhdl.v |
| /root/ophelia_efpga/verilog/rtl/fpga_tech.v |
| /root/ophelia_efpga/verilog/rtl/efuse_ctrl/efuse_array_fromvhdl.v |
| /root/ophelia_efpga/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v |
| /root/ophelia_efpga/verilog/rtl/fpga_struct_block/fpga_tech.v |
