verilog/rtl/efuse_ctrl/efuse_array_fromvhdl.v

/* Generated by Yosys 0.22 (git sha1 f109fa3d4, gcc 8.3.0-6 -fPIC -Os) */

(* top =  1  *)
module efuse_array(nPRESET, SENSE, PROG_ENA, SEL, DO);
  output [7:0] DO;
  wire [7:0] DO;
  input [7:0] PROG_ENA;
  wire [7:0] PROG_ENA;
  input [127:0] SEL;
  wire [127:0] SEL;
  input SENSE;
  wire SENSE;
  input nPRESET;
  wire nPRESET;
  assign DO = PROG_ENA;
endmodule