| design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY | |
| /run/media/tholin/Data/MPW/AS2650/openlane/wrapped_as2650,wrapped_as2650,22_12_10_00_43,flow completed,0h3m32s0ms,0h2m22s0ms,5500.0,2.16,2200.0,18.57,757.64,4752,0,0,0,0,0,0,0,-1,0,-1,-1,527212,49182,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,783782887.0,0.0,34.71,50.33,6.05,-1,30.55,4647,5079,59,491,0,0,0,4873,86,0,147,167,1071,240,83,1478,294,285,25,290,3236,0,3526,503875.2320000001,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,24.0,41.666666666666664,24.0,AREA 0,4,40,1,153.6,153.18,0.45,0.3,gf180mcu_fd_sc_mcu7t5v0,4 |