blob: 0782aeabcab77125eb9932003c95b47106d73296 [file] [log] [blame]
Project Chip ID is: 402703105
Setting Project Chip ID to: 1800c301
Step 1: Modify Layout of the user_id_programming subcell
Done!
Step 2: Add user project ID parameter to source verilog.
Done!
Step 3: Add user project ID parameter to gate-level verilog.
Done!
Step 4: Add user project ID text to top level layout.
Done!