added 74181 verilog sources

info.yaml

diff --git a/info.yaml b/info.yaml
index 65e82e8..feac095 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,11 +1,10 @@
 --- 
 # TinyTapeout project information
 project:
-  wokwi_id:    334445762078310996        # If using wokwi, set this to your project's ID
-#  source_files:        # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here
-#    - verilog/rtl/counter.v
-#    - verilog/rtl/decoder.v
-#  top_module:  "seven_segment_seconds"      # put the name of your top module here, make it unique by prepending your github username
+  wokwi_id:    0        # If using wokwi, set this to your project's ID
+  source_files:         # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here
+    - verilog/rtl/alu74181.v
+  top_module:  "thorkn_alu74181_top"      # put the name of your top module here, make it unique by prepending your github username
 
 # As everyone will have access to all designs, try to make it easy for someone new to your design to know what
 # it does and how to operate it.
@@ -21,7 +20,7 @@
   how_it_works: ""      # Longer description of how the project works
   how_to_test:  ""      # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
   external_hw:  ""      # Describe any external hardware needed
-  language:     "wokwi" # other examples include Verilog, Amaranth, VHDL, etc
+  language:     "Verilog" # other examples include Verilog, Amaranth, VHDL, etc
   doc_link:     ""      # URL to longer form documentation, eg the README.md in your repository
   clock_hz:     0       # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
   picture:      ""      # relative path to a picture in your repository

verilog/rtl/alu74181.v

diff --git a/verilog/rtl/alu74181.v b/verilog/rtl/alu74181.v
new file mode 100644
index 0000000..4bdf15a
--- /dev/null
+++ b/verilog/rtl/alu74181.v
@@ -0,0 +1,99 @@
+/*************************************************************************/
+/* 74181 - A historic 4 bit ALU                                          */
+/*************************************************************************/
+
+module thorkn_alu74181_top (
+
+  input [13:0] in,
+  output [7:0] out,
+);
+
+  top_alu74181 top_alu74181 (in[3:0], in[7:4], in[11:8], in[12], in[13], out[3:0], out[4], out[5], out[6], out[7]);
+  /************************** A     ,  B     ,  S      ,  CNb  ,  M    ,  F      ,  AEB  ,  X    ,  Y    ,  CN4b */
+endmodule
+
+/*************************************************************************/
+
+module top_alu74181 (
+
+  input [3:0] A, B, S,
+  input CNb, M,
+  output [3:0] F,
+  output AEB, X, Y, CN4b
+);
+
+  wire [3:0] E, D, C, Bb;
+
+  e_module e_mod (A, B, S, E);
+  d_module d_mod (A, B, S, D);
+  cla_module cla_mod (E, D, CNb, C, X, Y, CN4b);
+  sum_module sum_mod (E, D, C, M, F, AEB);
+
+endmodule
+
+/*************************************************************************/
+
+module e_module (
+
+  input [3:0] A, B, S,
+  output [3:0] E
+);
+
+  wire [3:0]  ABS3, ABbS2;
+
+  assign ABS3 = A&B&{4{S[3]}};
+  assign ABbS2 = A&~B&{4{S[2]}};
+  assign E = ~(ABS3|ABbS2);
+
+endmodule
+
+/*************************************************************************/
+
+module d_module (
+
+  input [3:0] A, B, S,
+  output [3:0] D
+);
+
+  wire [3:0]  BbS1, BS0;
+
+  assign BbS1 = ~B&{4{S[1]}};
+  assign BS0 = B&{4{S[0]}};
+  assign D = ~(BbS1|BS0|A);
+
+endmodule
+
+/*************************************************************************/
+
+module cla_module (
+
+  input [3:0] Gb, Pb,
+  input CNb,
+  output [3:0] C,
+  output X, Y, CN4b
+);
+
+  assign C[0] = ~CNb;
+  assign C[1] = ~(Pb[0]|(CNb&Gb[0]));
+  assign C[2] = ~(Pb[1]|(Pb[0]&Gb[1])|(CNb&Gb[0]&Gb[1]));
+  assign C[3] = ~(Pb[2]|(Pb[1]&Gb[2])|(Pb[0]&Gb[1]&Gb[2])|(CNb&Gb[0]&Gb[1]&Gb[2]));
+  assign X = ~&Gb;
+  assign Y = ~(Pb[3]|(Pb[2]&Gb[3])|(Pb[1]&Gb[2]&Gb[3])|(Pb[0]&Gb[1]&Gb[2]&Gb[3]));
+  assign CN4b = ~(Y&~(&Gb&CNb));
+
+endmodule
+
+/*************************************************************************/
+
+module sum_module (
+
+  input [3:0] E, D, C,
+  input M,
+  output [3:0] F,
+  output AEB
+);
+
+  assign F = (E ^ D) ^ (C|{4{M}});
+  assign AEB = &F;
+
+endmodule