| ############################################################################### |
| # Created by write_sdc |
| # Mon Dec 5 17:48:54 2022 |
| ############################################################################### |
| current_design Top_Module_4_ALU |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name __VIRTUAL_CLK__ -period 1000.0000 |
| set_clock_uncertainty 0.2500 __VIRTUAL_CLK__ |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Operation[0]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Operation[1]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Operation[2]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Operation[3]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[0]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[10]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[11]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[12]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[13]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[14]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[15]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[16]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[17]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[18]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[19]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[1]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[20]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[21]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[22]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[23]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[24]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[25]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[26]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[27]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[28]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[29]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[2]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[30]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[31]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[32]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[33]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[34]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[35]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[36]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[37]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[38]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[39]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[3]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[40]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[41]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[42]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[43]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[44]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[45]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[46]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[47]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[48]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[49]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[4]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[50]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[51]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[52]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[53]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[54]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[55]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[56]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[57]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[58]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[59]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[5]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[60]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[61]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[62]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[63]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[6]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[7]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[8]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {a_operand[9]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[0]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[10]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[11]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[12]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[13]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[14]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[15]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[16]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[17]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[18]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[19]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[1]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[20]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[21]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[22]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[23]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[24]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[25]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[26]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[27]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[28]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[29]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[2]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[30]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[31]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[32]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[33]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[34]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[35]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[36]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[37]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[38]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[39]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[3]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[40]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[41]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[42]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[43]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[44]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[45]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[46]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[47]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[48]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[49]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[4]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[50]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[51]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[52]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[53]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[54]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[55]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[56]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[57]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[58]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[59]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[5]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[60]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[61]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[62]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[63]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[6]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[7]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[8]}] |
| set_input_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {b_operand[9]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[0]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[10]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[11]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[12]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[13]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[14]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[15]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[16]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[17]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[18]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[19]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[1]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[20]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[21]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[22]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[23]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[24]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[25]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[26]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[27]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[28]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[29]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[2]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[30]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[31]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[32]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[33]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[34]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[35]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[36]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[37]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[38]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[39]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[3]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[40]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[41]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[42]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[43]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[44]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[45]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[46]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[47]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[48]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[49]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[4]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[50]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[51]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[52]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[53]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[54]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[55]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[56]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[57]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[58]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[59]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[5]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[60]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[61]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[62]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[63]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[6]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[7]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[8]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ALU_Output[9]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Exception[0]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Exception[1]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Exception[2]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Exception[3]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Overflow[0]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Overflow[1]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Overflow[2]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Overflow[3]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Underflow[0]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Underflow[1]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Underflow[2]}] |
| set_output_delay 200.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {Underflow[3]}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[63]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[62]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[61]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[60]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[59]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[58]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[57]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[56]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[55]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[54]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[53]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[52]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[51]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[50]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[49]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[48]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[47]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[46]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[45]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[44]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[43]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[42]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[41]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[40]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[39]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[38]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[37]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[36]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[35]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[34]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[33]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[32]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[31]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[30]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[29]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[28]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[27]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[26]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[25]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[24]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[23]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[22]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[21]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[20]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[19]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[18]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[17]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[16]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[15]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[14]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[13]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[12]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[11]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[10]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[9]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[8]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[7]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[6]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[5]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[4]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[3]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[2]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[1]}] |
| set_load -pin_load 0.0729 [get_ports {ALU_Output[0]}] |
| set_load -pin_load 0.0729 [get_ports {Exception[3]}] |
| set_load -pin_load 0.0729 [get_ports {Exception[2]}] |
| set_load -pin_load 0.0729 [get_ports {Exception[1]}] |
| set_load -pin_load 0.0729 [get_ports {Exception[0]}] |
| set_load -pin_load 0.0729 [get_ports {Overflow[3]}] |
| set_load -pin_load 0.0729 [get_ports {Overflow[2]}] |
| set_load -pin_load 0.0729 [get_ports {Overflow[1]}] |
| set_load -pin_load 0.0729 [get_ports {Overflow[0]}] |
| set_load -pin_load 0.0729 [get_ports {Underflow[3]}] |
| set_load -pin_load 0.0729 [get_ports {Underflow[2]}] |
| set_load -pin_load 0.0729 [get_ports {Underflow[1]}] |
| set_load -pin_load 0.0729 [get_ports {Underflow[0]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {Operation[3]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {Operation[2]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {Operation[1]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {Operation[0]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[63]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[62]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[61]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[60]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[59]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[58]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[57]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[56]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[55]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[54]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[53]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[52]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[51]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[50]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[49]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[48]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[47]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[46]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[45]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[44]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[43]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[42]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[41]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[40]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[39]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[38]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[37]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[36]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[35]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[34]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[33]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[32]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[31]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[30]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[29]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[28]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[27]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[26]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[25]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[24]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[23]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[22]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[21]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[20]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[19]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[18]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[17]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[16]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[15]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[14]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[13]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[12]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[11]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[10]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[9]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[8]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[7]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[6]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[5]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[4]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[3]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[2]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[1]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {a_operand[0]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[63]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[62]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[61]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[60]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[59]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[58]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[57]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[56]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[55]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[54]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[53]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[52]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[51]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[50]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[49]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[48]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[47]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[46]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[45]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[44]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[43]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[42]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[41]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[40]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[39]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[38]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[37]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[36]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[35]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[34]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[33]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[32]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[31]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[30]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[29]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[28]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[27]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[26]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[25]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[24]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[23]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[22]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[21]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[20]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[19]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[18]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[17]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[16]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[15]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[14]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[13]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[12]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[11]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[10]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[9]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[8]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[7]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[6]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[5]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[4]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[3]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[2]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[1]}] |
| set_driving_cell -lib_cell gf180mcu_fd_sc_mcu7t5v0__inv_1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {b_operand[0]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_fanout 4.0000 [current_design] |
