Delete verilog/rtl/backups directory
diff --git a/verilog/rtl/backups/cntr_example.v b/verilog/rtl/backups/cntr_example.v
deleted file mode 100644
index c9dd035..0000000
--- a/verilog/rtl/backups/cntr_example.v
+++ /dev/null
@@ -1,146 +0,0 @@
-// Copyright 2007 Altera Corporation. All rights reserved.
-// Altera products are protected under numerous U.S. and foreign patents,
-// maskwork rights, copyrights and other intellectual property laws.
-//
-// This reference design file, and your use thereof, is subject to and governed
-// by the terms and conditions of the applicable Altera Reference Design
-// License Agreement (either as signed by you or found at www.altera.com). By
-// using this reference design file, you indicate your acceptance of such terms
-// and conditions between you and Altera Corporation. In the event that you do
-// not agree with such terms and conditions, you may not use the reference
-// design file and please promptly destroy any copies you have made.
-//
-// This reference design file is being provided on an "as-is" basis and as an
-// accommodation and therefore all warranties, representations or guarantees of
-// any kind (whether express, implied or statutory) including, without
-// limitation, warranties of merchantability, non-infringement, or fitness for
-// a particular purpose, are specifically disclaimed. By making this reference
-// design file available, Altera expressly does not recommend, suggest or
-// require that this reference design file be used in combination with any
-// other product not provided by Altera.
-/////////////////////////////////////////////////////////////////////////////
-
-// baeckler - 06-16-2006
-// Modified by Jun (Jerry) Yin - 12-01-2022
-// Standard issue binary counter with all of the register secondary
-// hardware. (1 cell per bit)
-
-
-module cntr_example #(
- parameter BITS = 32
-)(
-`ifdef USE_POWER_PINS
- inout vdd, // User area 1 1.8V supply
- inout vss, // User area 1 digital ground
-`endif
-
- // Wishbone Slave ports (WB MI A)
- input wire wb_clk_i,
- input wire wb_rst_i,
- input wire wbs_stb_i,
- input wire wbs_cyc_i,
- input wire wbs_we_i,
- //input [3:0] wbs_sel_i,
- //input [31:0] wbs_dat_i,
- //input [31:0] wbs_adr_i,
- //output wbs_ack_o,
- //output [31:0] wbs_dat_o,
-
- // Logic Analyzer Signals
- //input [63:0] la_data_in,
- //output [63:0] la_data_out,
- //input [63:0] la_oenb,
-
- // IOs
- input [`MPRJ_IO_PADS-1:0] io_in,
- output [`MPRJ_IO_PADS-1:0] io_out,
- //output [`MPRJ_IO_PADS-1:0] io_oeb,
-
- // IRQ
- //output [2:0] irq
-);
- wire clk;
- wire rst;
-
- wire [`MPRJ_IO_PADS-1:0] io_in;
- wire [`MPRJ_IO_PADS-1:0] io_out;
- //wire [`MPRJ_IO_PADS-1:0] io_oeb;
-
- //wire [31:0] rdata;
- //wire [31:0] wdata;
- wire [BITS-1:0] count;
-
- //wire valid;
- //wire [3:0] wstrb;
- //wire [31:0] la_write;
-
- // WB MI A
- //assign valid = wbs_cyc_i && wbs_stb_i;
- //assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- //assign wbs_dat_o = rdata;
- //assign wdata = wbs_dat_i;
-
- // IO
- assign io_out = count;
- //assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
-
- // IRQ
- //assign irq = 3'b000; // Unused
-
- // LA
- //assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
- //assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- //assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
- //assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
- assign clk = wb_clk_i;
- assign rst = wb_rst_i;
-
- cntr #(
- .BITS(BITS)
- ) cntr(
- .clk(clk),
- .rst(rst),
- //.ready(wbs_ack_o),
- .ena(wbs_cyc_i),
- //.rdata(rdata),
- .sdata(io_in),
- //.wstrb(wstrb),
- //.la_write(la_write),
- //.la_input(la_data_in[63:32]),
- .sload(wbs_we_i),
- .sclear(wbs_stb_i),
- .q(io_out)
- );
-
-endmodule
-
-
-module cntr #(
- parameter BITS = 4
-)(
- input clk,
- input ena,
- input rst,
- input sload,
- input sclear,
- input [BITS-1:0] sdata,
- output [BITS-1:0] q
-);
-
- reg [BITS-1:0] q;
-
- always @(posedge clk or posedge rst) begin
- if (rst) q <= 0;
- else begin
- if (ena) begin
- if (sclear) q <= 0;
- else if (sload) q <= sdata;
- else q <= q + 1'b1;
- end
- end
- end
-
-endmodule
-`default_nettype wire
\ No newline at end of file
diff --git a/verilog/rtl/backups/user_project_wrapper.v b/verilog/rtl/backups/user_project_wrapper.v
deleted file mode 100644
index 204f397..0000000
--- a/verilog/rtl/backups/user_project_wrapper.v
+++ /dev/null
@@ -1,147 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_project_wrapper
- *
- * This wrapper enumerates all of the pins available to the
- * user for the user project.
- *
- * An example user project is provided in this wrapper. The
- * example should be removed and replaced with the actual
- * user project.
- *
- *-------------------------------------------------------------
- */
-
-module user_project_wrapper #(
- parameter BITS = 32
-)(
-`ifdef USE_POWER_PINS
- inout vdd, // User area 5.0V supply
- inout vss, // User area ground
-`endif
-
- // Wishbone Slave ports (WB MI A)
- input wb_clk_i,
- input wb_rst_i,
- input wbs_stb_i,
- input wbs_cyc_i,
- input wbs_we_i,
- input [3:0] wbs_sel_i,
- input [31:0] wbs_dat_i,
- input [31:0] wbs_adr_i,
- output wbs_ack_o,
- output [31:0] wbs_dat_o,
-
- // Logic Analyzer Signals
- input [63:0] la_data_in,
- output [63:0] la_data_out,
- input [63:0] la_oenb,
-
- // IOs
- input [`MPRJ_IO_PADS-1:0] io_in,
- output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb,
-
- // Independent clock (on independent integer divider)
- input user_clock2,
-
- // User maskable interrupt signals
- output [2:0] user_irq
-);
-
-/*--------------------------------------*/
-/* User project is instantiated here */
-/*--------------------------------------*/
-
-/*user_proj_example mprj (
-`ifdef USE_POWER_PINS
- .vdd(vdd), // User area 1 1.8V power
- .vss(vss), // User area 1 digital ground
-`endif
-
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- // MGMT SoC Wishbone Slave
-
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
-
- // Logic Analyzer
-
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
-
- // IO Pads
-
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
-
- // IRQ
- .irq(user_irq)
-); */
-
-cntr_example cntr_example_1 (
-`ifdef USE_POWER_PINS
- .vdd(vdd), // User area 1 1.8V power
- .vss(vss), // User area 1 digital ground
-`endif
-
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- // MGMT SoC Wishbone Slave
-
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- //.wbs_sel_i(wbs_sel_i),
- //.wbs_adr_i(wbs_adr_i),
- //.wbs_dat_i(wbs_dat_i),
- //.wbs_ack_o(wbs_ack_o),
- //.wbs_dat_o(wbs_dat_o),
-
- // Logic Analyzer
-
- //.la_data_in(la_data_in),
- //.la_data_out(la_data_out),
- //.la_oenb (la_oenb),
-
- // IO Pads
-
- .io_in (io_in),
- .io_out(io_out),
- //.io_oeb(io_oeb),
-
- // IRQ
- //.irq(user_irq)
-);
-
-endmodule // user_project_wrapper
-
-`default_nettype wire
\ No newline at end of file
