blob: 30108af1d14cd0099fff95e584793eb8c9b1840e [file] [log] [blame]
module user_project_wrapper (user_clock2,
wb_clk_i,
wb_rst_i,
wbs_ack_o,
wbs_cyc_i,
wbs_stb_i,
wbs_we_i,
vss,
vdd,
io_in,
io_oeb,
io_out,
la_data_in,
la_data_out,
la_oenb,
user_irq,
wbs_adr_i,
wbs_dat_i,
wbs_dat_o,
wbs_sel_i);
input user_clock2;
input wb_clk_i;
input wb_rst_i;
output wbs_ack_o;
input wbs_cyc_i;
input wbs_stb_i;
input wbs_we_i;
input vss;
input vdd;
input [37:0] io_in;
output [37:0] io_oeb;
output [37:0] io_out;
input [63:0] la_data_in;
output [63:0] la_data_out;
input [63:0] la_oenb;
output [2:0] user_irq;
input [31:0] wbs_adr_i;
input [31:0] wbs_dat_i;
output [31:0] wbs_dat_o;
input [3:0] wbs_sel_i;
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
cntr_example cntr_example_1 (.vdd(vdd),
.vss(vss),
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.io_out({_08_,
_07_,
_06_,
_05_,
_04_,
_03_,
_02_,
_01_,
_17_,
_16_,
_15_,
_14_,
_13_,
_12_,
_11_,
_10_,
_09_,
_00_,
io_out[19],
io_out[18],
io_out[17],
io_out[16],
io_out[15],
io_out[14],
io_out[13],
io_out[12],
io_out[11],
io_out[10],
io_out[9],
io_out[8],
io_out[7],
io_out[6],
io_out[5],
io_out[4],
io_out[3],
io_out[2],
io_out[1],
io_out[0]}));
endmodule