| [INFO]: Run Directory: /home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14 |
| [INFO]: Preparing LEF files for the nom corner... |
| [INFO]: Running Synthesis (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/synthesis/1-synthesis.log)... |
| [INFO]: Running Single-Corner Static Timing Analysis (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/synthesis/2-sta.log)... |
| [INFO]: Creating a netlist with power/ground pins. |
| [INFO]: Running Initial Floorplanning (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/floorplan/3-initial_fp.log)... |
| [INFO]: Floorplanned with width 2955.68 and height 2951.76. |
| [INFO]: Running IO Placement (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/floorplan/4-place_io.log)... |
| [INFO]: Performing Manual Macro Placement (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/placement/5-macro_placement.log)... |
| [INFO]: Power planning with power {vdd} and ground {vss}... |
| [INFO]: Generating PDN (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/floorplan/6-pdn.log)... |
| [INFO]: Performing Random Global Placement (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/placement/7-global.log)... |
| [INFO]: Skipping Placement Resizer Design Optimizations. |
| [INFO]: Running Detailed Placement (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/placement/8-detailed.log)... |
| [INFO]: Skipping Placement Resizer Timing Optimizations. |
| [INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/routing/9-resizer.log)... |
| [INFO]: Running Detailed Placement (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/routing/10-diode_legalization.log)... |
| [INFO]: Running Global Routing (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/routing/11-global.log)... |
| [INFO]: Writing Verilog (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/routing/11-global_write_netlist.log)... |
| [INFO]: Running Detailed Routing (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/routing/13-detailed.log)... |
| [INFO]: No DRC violations after detailed routing. |
| [INFO]: Checking Wire Lengths (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/routing/14-wire_lengths.log)... |
| [INFO]: Running SPEF Extraction at the nom process corner (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/signoff/15-parasitics_extraction.nom.log)... |
| [INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/signoff/16-rcx_mcsta.nom.log)... |
| [INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/signoff/17-rcx_sta.log)... |
| [INFO]: Running Magic to generate various views... |
| [INFO]: Streaming out GDSII with Magic (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/signoff/18-gdsii.log)... |
| [INFO]: Generating MAGLEF views... |
| [INFO]: Running Magic Spice Export from LEF (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/signoff/19-spice.log)... |
| [INFO]: Writing Powered Verilog (logs: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/signoff/20-write_powered_def.log, ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/signoff/20-write_powered_verilog.log)... |
| [INFO]: Writing Verilog (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/signoff/20-write_powered_verilog.log)... |
| [INFO]: Running LVS (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/signoff/22-lvs.lef.log)... |
| [INFO]: Running Magic DRC (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/signoff/23-drc.log)... |
| [INFO]: Converting Magic DRC database to various tool-readable formats... |
| [INFO]: No DRC violations after GDS streaming out. |
| [INFO]: Running OpenROAD Antenna Rule Checker (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/logs/signoff/24-antenna.log)... |
| [INFO]: Saving current set of views in '../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/results/final'... |
| [INFO]: Saving current set of views in '../home/htf6ry/gf180-demo-fiveguys'... |
| [INFO]: Saving runtime environment... |
| [INFO]: Generating final set of reports... |
| [INFO]: Created manufacturability report at '../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/reports/manufacturability.rpt'. |
| [INFO]: Created metrics report at '../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/reports/metrics.csv'. |
| [WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/reports/signoff/17-rcx_sta.slew.rpt'. |
| [WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo-fiveguys/openlane/user_project_wrapper/runs/22_12_04_16_14/reports/signoff/17-rcx_sta.slew.rpt'. |
| [INFO]: There are no hold violations in the design at the typical corner. |
| [INFO]: There are no setup violations in the design at the typical corner. |
| [SUCCESS]: Flow complete. |
| [INFO]: Note that the following warnings have been generated: |
