| - status: 0 - openlane design prep |
| runtime_s: 1.93 |
| runtime_ts: 0h0m1s927ms |
| - status: 1 - synthesis - yosys |
| runtime_s: 2.46 |
| runtime_ts: 0h0m2s463ms |
| - status: 2 - sta - openroad |
| runtime_s: 0.83 |
| runtime_ts: 0h0m0s833ms |
| - status: 3 - floorplan initialization - openroad |
| runtime_s: 1.56 |
| runtime_ts: 0h0m1s561ms |
| - status: 4 - io_place - openlane |
| runtime_s: 0.31 |
| runtime_ts: 0h0m0s312ms |
| - status: 5 - tap/decap insertion - openroad |
| runtime_s: 0.86 |
| runtime_ts: 0h0m0s856ms |
| - status: 6 - pdn generation - openroad |
| runtime_s: 2.06 |
| runtime_ts: 0h0m2s60ms |
| - status: 7 - global placement - openroad |
| runtime_s: 8.21 |
| runtime_ts: 0h0m8s212ms |
| - status: 8 - resizer design optimizations - openroad |
| runtime_s: 1.53 |
| runtime_ts: 0h0m1s532ms |
| - status: 9 - detailed placement - openroad |
| runtime_s: 1.03 |
| runtime_ts: 0h0m1s34ms |
| - status: 10 - cts - openroad |
| runtime_s: 32.48 |
| runtime_ts: 0h0m32s475ms |
| - status: 11 - resizer timing optimizations - openroad |
| runtime_s: 1.35 |
| runtime_ts: 0h0m1s350ms |
| - status: 12 - resizer timing optimizations - openroad |
| runtime_s: 1.46 |
| runtime_ts: 0h0m1s461ms |
| - status: 14 - detailed placement - openroad |
| runtime_s: 1.1 |
| runtime_ts: 0h0m1s100ms |
| - status: 14 - diode insertion - openlane |
| runtime_s: 1.2 |
| runtime_ts: 0h0m1s197ms |
| - status: 15 - fill insertion - openroad |
| runtime_s: 1.52 |
| runtime_ts: 0h0m1s522ms |
| - status: 17 - write verilog - openroad |
| runtime_s: 1.01 |
| runtime_ts: 0h0m1s14ms |
| - status: 17 - global routing - openroad |
| runtime_s: 1.11 |
| runtime_ts: 0h0m1s110ms |
| - status: 18 - detailed_routing - openroad |
| runtime_s: 34.36 |
| runtime_ts: 0h0m34s356ms |
| - status: 19 - wire lengths - openlane |
| runtime_s: 0.76 |
| runtime_ts: 0h0m0s762ms |
| - status: 20 - parasitics extraction - openroad |
| runtime_s: 1.24 |
| runtime_ts: 0h0m1s242ms |
| - status: 21 - sta - openroad |
| runtime_s: 3.03 |
| runtime_ts: 0h0m3s29ms |
| - status: 22 - sta - openroad |
| runtime_s: 1.5 |
| runtime_ts: 0h0m1s504ms |
| - status: 23 - gdsii - magic |
| runtime_s: 8.38 |
| runtime_ts: 0h0m8s381ms |
| - status: 24 - spice extraction - magic |
| runtime_s: 16.66 |
| runtime_ts: 0h0m16s661ms |
| - status: 26 - write verilog - openroad |
| runtime_s: 1.11 |
| runtime_ts: 0h0m1s108ms |
| - status: 26 - write powered verilog - openlane |
| runtime_s: 1.23 |
| runtime_ts: 0h0m1s229ms |
| - status: 27 - lvs - netgen |
| runtime_s: 1.04 |
| runtime_ts: 0h0m1s40ms |
| - status: 28 - drc - magic |
| runtime_s: 165.58 |
| runtime_ts: 0h2m45s578ms |
| - status: 29 - antenna check - openroad |
| runtime_s: 1.05 |
| runtime_ts: 0h0m1s48ms |
| --- |
| - status: routed |
| runtime_s: 99.0 |
| runtime_ts: 0h1m39s0ms |
| - status: flow completed |
| runtime_s: 301.0 |
| runtime_ts: 0h5m1s0ms |
